diff --git a/library/xilinx/scripts/versal_xcvr_subsystem.tcl b/library/xilinx/scripts/versal_xcvr_subsystem.tcl
index 3fa4e612f8..82bcc94e3b 100644
--- a/library/xilinx/scripts/versal_xcvr_subsystem.tcl
+++ b/library/xilinx/scripts/versal_xcvr_subsystem.tcl
@@ -84,7 +84,7 @@ proc create_xcvr_subsystem {
   dict set phy_params CONFIG.REG_CONF_INTF {AXI_LITE}
   dict set phy_params CONFIG.NO_OF_QUADS ${num_quads}
   dict set phy_params CONFIG.NO_OF_INTERFACE {1}
-  dict set phy_params CONFIG.LOCATE_BUFG {CORE}
+  dict set phy_params CONFIG.LOCATE_BUFG {EXAMPLE_DESIGN}
   dict set phy_params CONFIG.INTF0_PRESET ${transceiver}-JESD204_${jesd_mode}
   dict set phy_params CONFIG.INTF0_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
   if {$direction != "RXTX"} {
@@ -163,6 +163,17 @@ proc create_xcvr_subsystem {
     }
   }
 
+  for {set i 0} {$i < $no_lanes} {incr i} {
+    set quad_idx [expr $i / 4]
+    set lane_idx [expr $i % 4]
+
+    dict set phy_params "CONFIG.QUAD${quad_idx}_CH${lane_idx}_ILORESET_EN" {true}
+    dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK0_LCPLLRESET_EN" {true}
+    dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK1_LCPLLRESET_EN" {true}
+    dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK0_LCPLL_LOCK_EN" {true}
+    dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK1_LCPLL_LOCK_EN" {true}
+  }
+
   # dict for {k v} $phy_params {puts "$k : $v"}
   set_property -dict $phy_params [get_bd_cells ${ip_name}]
 }
@@ -246,8 +257,12 @@ proc create_versal_jesd_xcvr_subsystem {
 
       create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
       ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
-      ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${rx_intf}_rx_usrclk
+      ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_rx/usrclk
       ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align
+
+      set quad_idx [expr $j / 4]
+      set lane_idx [expr $j % 4]
+      ad_connect ${ip_name}/xcvr/QUAD${quad_idx}_RX${lane_idx}_usrclk ${ip_name}/bufg_gt_rx/usrclk
     }
   }
 
@@ -272,7 +287,11 @@ proc create_versal_jesd_xcvr_subsystem {
 
       create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
       ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
-      ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${tx_intf}_tx_usrclk
+      ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_tx/usrclk
+
+      set quad_idx [expr $j / 4]
+      set lane_idx [expr $j % 4]
+      ad_connect ${ip_name}/xcvr/QUAD${quad_idx}_TX${lane_idx}_usrclk ${ip_name}/bufg_gt_tx/usrclk
     }
   }
 
@@ -290,15 +309,9 @@ proc create_versal_jesd_xcvr_subsystem {
     create_bd_pin -dir O ${ip_name}/tx_resetdone
   }
 
-  create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_sync
-  ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk
-  ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn
-  ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits
-
-
-  ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/xcvr/INTF${rx_intf}_rst_all_in
+  ad_connect ${ip_name}/gtreset_in ${ip_name}/xcvr/INTF${rx_intf}_rst_all_in
   if {$rx_intf != $tx_intf} {
-    ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/xcvr/INTF${tx_intf}_rst_all_in
+    ad_connect ${ip_name}/gtreset_in ${ip_name}/xcvr/INTF${tx_intf}_rst_all_in
   }
 
   foreach port {pll_and_datapath datapath} {
@@ -307,14 +320,43 @@ proc create_versal_jesd_xcvr_subsystem {
         continue
       }
       set intf [expr {$rx_tx == "rx" ? $rx_intf : $tx_intf}]
-      create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync
-      ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk
-      ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn
-      ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits
-      ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/xcvr/INTF${intf}_rst_${rx_tx}_${port}_in
+      ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/xcvr/INTF${intf}_rst_${rx_tx}_${port}_in
     }
   }
 
+  ad_ip_instance ilconcat ${ip_name}/lcplllock_concat
+  ad_ip_parameter ${ip_name}/lcplllock_concat CONFIG.NUM_PORTS [expr 2 * $num_quads]
+
+  for {set i 0} {$i < $num_quads} {incr i} {
+    if {$intf_cfg != "RX"} {
+      ad_connect ${ip_name}/gtreset_tx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk0_lcpllreset
+      ad_connect ${ip_name}/gtreset_tx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk1_lcpllreset
+    } else {
+      ad_connect ${ip_name}/gtreset_rx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk0_lcpllreset
+      ad_connect ${ip_name}/gtreset_rx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk1_lcpllreset
+    }
+    ad_connect ${ip_name}/xcvr/QUAD${i}_hsclk0_lcplllock ${ip_name}/lcplllock_concat/In[expr 2 * $i]
+    ad_connect ${ip_name}/xcvr/QUAD${i}_hsclk1_lcplllock ${ip_name}/lcplllock_concat/In[expr 2 * $i + 1]
+  }
+
+  ad_ip_instance ilreduced_logic ${ip_name}/lcplllock_and
+  ad_ip_parameter ${ip_name}/lcplllock_and CONFIG.C_SIZE [expr 2 * $num_quads]
+  ad_ip_parameter ${ip_name}/lcplllock_and CONFIG.C_OPERATION {and}
+
+  ad_connect ${ip_name}/lcplllock_concat/dout ${ip_name}/lcplllock_and/Op1
+
+  ad_ip_instance ilvector_logic ${ip_name}/lcplllock_not
+  ad_ip_parameter ${ip_name}/lcplllock_not CONFIG.C_SIZE {1}
+  ad_ip_parameter ${ip_name}/lcplllock_not CONFIG.C_OPERATION {not}
+
+  ad_connect ${ip_name}/lcplllock_not/Op1 ${ip_name}/lcplllock_and/Res
+
+  for {set i 0} {$i < [expr 4 * $num_quads]} {incr i} {
+    set quad_idx [expr $i / 4]
+    set lane_idx [expr $i % 4]
+    ad_connect ${ip_name}/lcplllock_not/Res ${ip_name}/xcvr/QUAD${quad_idx}_ch${lane_idx}_iloreset
+  }
+
   ad_connect ${ip_name}/xcvr/gtpowergood ${ip_name}/gtpowergood
   if {$intf_cfg != "TX"} {
     ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rst_rx_done_out ${ip_name}/rx_resetdone
diff --git a/projects/ad9081_fmca_ebz/vck190/system_bd.tcl b/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
index dc13abf18a..e4fff7c7e1 100644
--- a/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
+++ b/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -16,10 +16,6 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 set ADI_PHY_SEL 0
 set TRANSCEIVER_TYPE GTY
 
-adi_project_files ad9081_fmca_ebz_vck190 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
-
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
diff --git a/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl b/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl
index 0ca977c800..0c90ca36bc 100644
--- a/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl
+++ b/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2024-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -16,10 +16,6 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 set ADI_PHY_SEL 0
 set TRANSCEIVER_TYPE GTYP
 
-adi_project_files ad9081_fmca_ebz_vpk180 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
-
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
diff --git a/projects/ad9082_fmca_ebz/vck190/system_bd.tcl b/projects/ad9082_fmca_ebz/vck190/system_bd.tcl
index 5e4e898b05..18a418151e 100644
--- a/projects/ad9082_fmca_ebz/vck190/system_bd.tcl
+++ b/projects/ad9082_fmca_ebz/vck190/system_bd.tcl
@@ -1,10 +1,6 @@
 ###############################################################################
-## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-adi_project_files ad9082_fmca_ebz_vck190 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
-
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
diff --git a/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl b/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl
index 4381e8052b..0de3ee1735 100644
--- a/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl
+++ b/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl
@@ -1,10 +1,6 @@
 ###############################################################################
-## Copyright (C) 2024-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-adi_project_files ad9082_fmca_ebz_vpk180 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
-
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl