From 1a85bf827ff149ca1e83595868940cb825c9ee8a Mon Sep 17 00:00:00 2001 From: Capota Bianca Date: Mon, 28 Apr 2025 15:58:03 +0300 Subject: [PATCH 1/2] docs/projects/ad411x_ad717x: Fix links overview Signed-off-by: Capota Bianca --- docs/projects/ad411x_ad717x/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/projects/ad411x_ad717x/index.rst b/docs/projects/ad411x_ad717x/index.rst index fea92a7a3c..1772f8398d 100644 --- a/docs/projects/ad411x_ad717x/index.rst +++ b/docs/projects/ad411x_ad717x/index.rst @@ -6,10 +6,10 @@ AD411x-AD717x HDL project Overview ---------------------------------------------------------------------------------- -The :adi:`AD4111` /:adi:`AD4112` /:adi:`AD4114` /:adi:`AD4415`/ :adi:`AD4116` is +The :adi:`AD4111` /:adi:`AD4112` /:adi:`AD4114` /:adi:`AD4115`/ :adi:`AD4116` is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC), high impedance (≥1 MΩ) bipolar, ±10 V voltage inputs, and 0 mA to 20 mA -current inputs. The :adi:`AD4111` /:adi:`AD4112` /:adi:`AD4114` /:adi:`AD4415` / +current inputs. The :adi:`AD4111` /:adi:`AD4112` /:adi:`AD4114` /:adi:`AD4115` / :adi:`AD4116` also integrates key analog and digital signal conditioning blocks to configure eight individual setups for each analog input channel in use. From 8e55c3ff479cc787c053d5ad97e2887251b69c44 Mon Sep 17 00:00:00 2001 From: Capota Bianca Date: Mon, 28 Apr 2025 15:53:04 +0300 Subject: [PATCH 2/2] projects/ad411x_ad717x: Add READMEs Signed-off-by: Capota Bianca --- projects/ad411x_ad717x/README.md | 26 +++++++++++++++++++++++ projects/ad411x_ad717x/de10nano/README.md | 8 +++++++ 2 files changed, 34 insertions(+) create mode 100644 projects/ad411x_ad717x/README.md create mode 100644 projects/ad411x_ad717x/de10nano/README.md diff --git a/projects/ad411x_ad717x/README.md b/projects/ad411x_ad717x/README.md new file mode 100644 index 0000000000..e19a04c5ef --- /dev/null +++ b/projects/ad411x_ad717x/README.md @@ -0,0 +1,26 @@ +# AD411X-AD717X HDL Project + +- Evaluation boards product page: [EVAL-AD4111](https://www.analog.com/eval-ad4111), [EVAL-AD4112](https://www.analog.com/eval-ad4112), [EVAL-AD4114](https://www.analog.com/eval-ad4114), [EVAL-AD4115](https://www.analog.com/eval-ad4115), [EVAL-AD4116](https://www.analog.com/eval-ad4116), [EVAL-AD7172-2](https://www.analog.com/ad7172-2), [EVAL-AD7172-4](https://www.analog.com/ad7172-4), [EVAL-AD7173-8](https://www.analog.com/ad7173-8), [EVAL-AD7175-2](https://www.analog.com/ad7175-2), [EVAL-AD7175-8](https://www.analog.com/ad7175-8), [EVAL-AD7176-2](https://www.analog.com/ad7176-2), [EVAL-AD7177-2](https://www.analog.com/ad7177-2) +- System documentation: https://wiki.analog.com/resources/tools-software/product-support-software/ad717x_ad411x_mbed_example +- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad411x_ad717x/index.html + +## Supported parts + +| Part name | Description | +|---------------------------------------------|------------------------------------------------------------------------------------------------------| +| [AD4111](https://www.analog.com/ad4111) | Single Supply, 24-Bit, Sigma-Delta ADC with ±10 V and 0 mA to 20 mA Inputs, Open Wire Detection | +| [AD4112](https://www.analog.com/ad4112) | Single Supply, 24-Bit, Sigma-Delta ADC with ±10 V and 0 mA to 20 mA Inputs | +| [AD4114](https://www.analog.com/ad4114) | Single Supply, Multichannel, 31.25 kSPS, 24-Bit, Sigma-Delta ADC with ±10 V Inputs | +| [AD4115](https://www.analog.com/ad4115) | Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with ±10 V Inputs | +| [AD4116](https://www.analog.com/ad4116) | Single Supply, 24-Bit, Sigma-Delta ADC with ±10 V, 10 MΩ Inputs and Buffered Low Level Inputs | +| [AD7172-2](https://www.analog.com/ad7172-2) | Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers | +| [AD7172-4](https://www.analog.com/ad7172-4) | Low Power, with 4- or 8-channel, 24-bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers | +| [AD7173-8](https://www.analog.com/ad7173-8) | Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC | +| [AD7175-2](https://www.analog.com/ad7175-2) | 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers | +| [AD7175-8](https://www.analog.com/ad7175-8) | 24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers | +| [AD7176-2](https://www.analog.com/ad7176-2) | 24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling | +| [AD7177-2](https://www.analog.com/ad7177-2) | 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers | + +## Building the project + +Please enter the folder for the FPGA carrier you want to use and read the README.md. \ No newline at end of file diff --git a/projects/ad411x_ad717x/de10nano/README.md b/projects/ad411x_ad717x/de10nano/README.md new file mode 100644 index 0000000000..e607ca3b5d --- /dev/null +++ b/projects/ad411x_ad717x/de10nano/README.md @@ -0,0 +1,8 @@ +# AD411X-AD717X/DE10NANO HDL Project + +## Building the project + +``` +cd projects/ad411x_ad717x/de10nano +make +``` \ No newline at end of file