projects: ad9209_fmca_ebz: vck190: Expose LCPLL reset to axi_gpio

Signed-off-by: Bogdan Luncan <[email protected]>

Author: bluncan

projects/ad9209_fmca_ebz/vck190/system_top.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -111,16 +111,19 @@ module system_top  #(
   wire  [ 7:0]              rx_data_p_loc;
   wire  [ 7:0]              rx_data_n_loc;
 
+  wire                      ref_clk;
   wire                      clkin10;
   wire                      rx_device_clk;
 
-  wire                      gt_reset;
+  wire                      mst_reset;
+  wire                      gt_lcpll_reset;
   wire                      rx_reset_pll_and_datapath;
   wire                      rx_reset_datapath;
   wire                      rx_resetdone;
   wire                      gt_powergood;
   wire                      gt_reset_s;
   wire                      mst_resetdone;
+  wire                      gt_lcpllresetdone;
 
   // instantiations
   IBUFDS_GTE5 i_ibufds_ref_clk (
@@ -193,9 +196,12 @@ module system_top  #(
 
   assign gpio_i[64] = rx_resetdone;
   assign gpio_i[66] = mst_resetdone;
+  assign gpio_i[67] = gt_lcpllresetdone;
   assign gt_reset   = gpio_o[67];
   assign rx_reset_pll_and_datapath = gpio_o[68];
   assign rx_reset_datapath = gpio_o[70];
+  assign gt_lcpll_reset = gpio_o[72];
+  assign mst_reset = gpio_o[73];
 
   generate
   if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
@@ -221,11 +227,9 @@ module system_top  #(
 
   // Unused GPIOs
   assign gpio_i[59:57] = gpio_o[59:57];
-  assign gpio_i[94:72] = gpio_o[94:72];
+  assign gpio_i[94:74] = gpio_o[94:74];
   assign gpio_i[31:10] = gpio_o[31:10];
 
-  /* Reset should only be asserted if powergood is high */
-  assign gt_reset_s    = gt_reset & gt_powergood;
   assign mst_resetdone = rx_resetdone;
 
   system_wrapper i_system_wrapper (
@@ -268,11 +272,14 @@ module system_top  #(
     .rx_1_p (rx_data_p_loc[7:4]),
     .rx_1_n (rx_data_n_loc[7:4]),
 
-    .gt_reset (gt_reset_s),
+    .gt_reset (mst_reset & gt_powergood),
+    .gt_lcpllreset (gt_lcpll_reset),
     .gt_reset_rx_datapath (rx_reset_datapath),
     .gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath),
     .gt_powergood (gt_powergood),
     .rx_resetdone (rx_resetdone),
+    .gt_lcpllresetdone (gt_lcpllresetdone),
+
     .ref_clk_q0 (ref_clk),
     .ref_clk_q1 (ref_clk),
     .rx_device_clk (rx_device_clk),