adrv9026: Add ORX support in NLS mode

Signed-off-by: AndrDragomir <[email protected]>

Author: AndrDragomir

Diff for: projects/adrv9026/common/adrv9026_bd.tcl

@@ -14,6 +14,7 @@ M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
+LIB_DEPS += axi_clkgen
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_sysid
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc

Diff for: projects/adrv9026/vcu118/Makefile

@@ -94,3 +94,6 @@ set_property -dict {PACKAGE_PIN AP37 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
 
 create_clock -name ref_clk   -period  4.00 [get_ports ref_clk_p]
 create_clock -name core_clk  -period  4.00 [get_ports core_clk_p]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_core_clk_ibufds_1/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets core_clk]

Diff for: projects/adrv9026/vcu118/system_constr.xdc

@@ -20,6 +20,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project adrv9026_vcu118 0 [list \
   JESD_MODE           [get_env_param JESD_MODE      8B10B ] \
+  LINK_SHARING        [get_env_param LINK_SHARING       1 ] \
   TX_LANE_RATE        [get_env_param TX_LANE_RATE    9.83 ] \
   RX_LANE_RATE        [get_env_param RX_LANE_RATE    9.83 ] \
   TX_NUM_LINKS        [get_env_param RX_NUM_LINKS       1 ] \
@@ -30,6 +31,9 @@ adi_project adrv9026_vcu118 0 [list \
   RX_JESD_M           [get_env_param RX_JESD_M          8 ] \
   RX_JESD_L           [get_env_param RX_JESD_L          4 ] \
   RX_JESD_S           [get_env_param RX_JESD_S          1 ] \
+  RX_OS_JESD_M        [get_env_param RX_OS_JESD_M       0 ] \
+  RX_OS_JESD_L        [get_env_param RX_OS_JESD_L       0 ] \
+  RX_OS_JESD_S        [get_env_param RX_OS_JESD_S       0 ] \
 ]
 
 adi_project_files adrv9026_vcu118 [list \
@@ -38,6 +42,6 @@ adi_project_files adrv9026_vcu118 [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ]
 
-## To improve timing of the BRAM buffers
+set_property strategy Performance_RefinePlacement [get_runs impl_1]
 
 adi_project_run adrv9026_vcu118

Diff for: projects/adrv9026/vcu118/system_project.tcl

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -166,8 +166,6 @@ module system_top (
 
   assign gpio_i[25:17] = gpio_o[25:17];
 
-  assign rx_os_sync = 1'b0;
-
   // instantiations
 
   IBUFDS_GTE4 i_ibufds_rx_ref_clk (
@@ -192,7 +190,7 @@ module system_top (
     .OB (rx_sync_n));
 
   OBUFDS i_obufds_rx_os_sync (
-    .I (rx_os_sync),
+    .I (~rx_os_sync),
     .O (rx_os_sync_p),
     .OB (rx_os_sync_n));
 
@@ -320,8 +318,11 @@ module system_top (
     .rx_data_3_n (rx_data_n[3]),
     .rx_data_3_p (rx_data_p[3]),
     .rx_ref_clk_0 (ref_clk),
+    .rx_os_ref_clk_0 (ref_clk),
     .rx_sync_0 (rx_sync),
+    .rx_os_sync (rx_os_sync),
     .rx_sysref_0 (sysref),
+    .rx_os_sysref (sysref),
     .tx_data_0_n (tx_data_n[0]),
     .tx_data_0_p (tx_data_p[0]),
     .tx_data_1_n (tx_data_n[1]),

Diff for: projects/adrv9026/vcu118/system_top.v

@@ -14,6 +14,7 @@ M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
+LIB_DEPS += axi_clkgen
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_sysid
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc

Diff for: projects/adrv9026/zcu102/Makefile

@@ -9,6 +9,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project adrv9026_zcu102 0 [list \
   JESD_MODE           [get_env_param JESD_MODE      8B10B ] \
+  LINK_SHARING        [get_env_param LINK_SHARING       1 ] \
   TX_LANE_RATE        [get_env_param TX_LANE_RATE    9.83 ] \
   RX_LANE_RATE        [get_env_param RX_LANE_RATE    9.83 ] \
   TX_NUM_LINKS        [get_env_param RX_NUM_LINKS       1 ] \
@@ -19,6 +20,9 @@ adi_project adrv9026_zcu102 0 [list \
   RX_JESD_M           [get_env_param RX_JESD_M          8 ] \
   RX_JESD_L           [get_env_param RX_JESD_L          4 ] \
   RX_JESD_S           [get_env_param RX_JESD_S          1 ] \
+  RX_OS_JESD_M        [get_env_param RX_OS_JESD_M       0 ] \
+  RX_OS_JESD_L        [get_env_param RX_OS_JESD_L       0 ] \
+  RX_OS_JESD_S        [get_env_param RX_OS_JESD_S       0 ] \
 ]
 adi_project_files adrv9026_zcu102 [list \
   "system_top.v" \

Diff for: projects/adrv9026/zcu102/system_project.tcl

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -124,7 +124,6 @@ module system_top (
 
   assign gpio_i[94:69] = gpio_o[94:69];
   assign gpio_i[31:21] = gpio_o[31:21];
-  assign rx_os_sync = 1'b0;
 
   // instantiations
 
@@ -150,7 +149,7 @@ module system_top (
     .OB (rx_sync_n));
 
   OBUFDS i_obufds_rx_os_sync (
-    .I (rx_os_sync),
+    .I (~rx_os_sync),
     .O (rx_os_sync_p),
     .OB (rx_os_sync_n));
 
@@ -235,8 +234,11 @@ module system_top (
     .rx_data_3_n (rx_data_n[3]),
     .rx_data_3_p (rx_data_p[3]),
     .rx_ref_clk_0 (ref_clk),
+    .rx_os_ref_clk_0 (ref_clk),
     .rx_sync_0 (rx_sync),
+    .rx_os_sync (rx_os_sync),
     .rx_sysref_0 (sysref),
+    .rx_os_sysref (sysref),
     .spi0_sclk (spi_clk),
     .spi0_csn (spi_csn),
     .spi0_miso (spi_miso),