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projects/daq2: Add README files
Signed-off-by: Elena-Hadarau_adi <[email protected]>
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‎projects/daq2/README.md

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# DAQ2 HDL Project
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- Evaluation board product page: [EVAL-AD-FMCDAQ2-EBZ](https://www.analog.com/eval-ad-fmcdaq2-ebz)
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- System documentation: https://wiki.analog.com/resources/eval/user-guides/ad-fmcdaq2-ebz
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- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/daq2/index.html
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## Supported parts
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| Part name | Description |
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|-----------------------------------------|---------------------------------------------------------------------------------------|
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| [AD9680](https://www.analog.com/ad9680) | 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter |
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| [AD9144](https://www.analog.com/ad9144) | Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter |
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## Building the project
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Please enter the folder for the FPGA carrier you want to use and read the README.md.

‎projects/daq2/Readme.md

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‎projects/daq2/a10soc/README.md

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# DAQ2/A10SOC HDL Project
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## Building the project
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```
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cd projects/daq2/a10soc
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make
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```
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Corresponding device tree: [socfpga_arria10_socdk_daq2.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_daq2.dts)

‎projects/daq2/kc705/README.md

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# DAQ2/KC705 HDL Project
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/daq2/kc705
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make
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```
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This device operates in single link JESD204B mode, meaning 8b10b link layer encoding, using the ADI IP as Physical layer.
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All of the RX link modes can be found in the [AD9680 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9680.pdf), Table 26. We offer support for only a few of them.
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All of the TX link modes can be found in the [AD9144 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9144.pdf), Table 35. We offer support for only a few of them.
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If other configurations are desired, then the parameters from the HDL project (see below) need to be changed, as well as the Linux/no-OS project configurations.
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The overwritable parameters from the environment are:
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- [RX/TX]_JESD_M - [RX/TX] number of converters per link
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- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
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- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame
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### Example configurations
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#### Default configuration
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This specific command is equivalent to running `make` only:
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```
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make RX_JESD_M=2 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=2 \
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TX_JESD_L=4 \
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TX_JESD_S=1
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```
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Corresponding device tree: [kc705_fmcdaq2.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/kc705_fmcdaq2.dts)

‎projects/daq2/kcu105/README.md

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# DAQ2/KCU105 HDL Project
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/daq2/kcu105
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make
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```
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This device operates in single link JESD204B mode, meaning 8b10b link layer encoding, using the ADI IP as Physical layer.
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All of the RX link modes can be found in the [AD9680 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9680.pdf), Table 26. We offer support for only a few of them.
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All of the TX link modes can be found in the [AD9144 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9144.pdf), Table 35. We offer support for only a few of them.
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If other configurations are desired, then the parameters from the HDL project (see below) need to be changed, as well as the Linux/no-OS project configurations.
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The overwritable parameters from the environment are:
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- [RX/TX]_JESD_M - [RX/TX] number of converters per link
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- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
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- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame
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### Example configurations
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#### Default configuration
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This specific command is equivalent to running `make` only:
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```
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make RX_JESD_M=2 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=2 \
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TX_JESD_L=4 \
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TX_JESD_S=1
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```
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Corresponding device tree: [kcu105_fmcdaq2.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/kcu105_fmcdaq2.dts)

‎projects/daq2/zc706/README.md

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# DAQ2/ZC706 HDL Project
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/daq2/zc706
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make
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```
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This device operates in single link JESD204B mode, meaning 8b10b link layer encoding, using the ADI IP as Physical layer.
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All of the RX link modes can be found in the [AD9680 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9680.pdf), Table 26. We offer support for only a few of them.
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All of the TX link modes can be found in the [AD9144 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9144.pdf), Table 35. We offer support for only a few of them.
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If other configurations are desired, then the parameters from the HDL project (see below) need to be changed, as well as the Linux/no-OS project configurations.
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The overwritable parameters from the environment are:
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- [RX/TX]_JESD_M - [RX/TX] number of converters per link
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- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
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- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame
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### Example configurations
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#### Default configuration
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This specific command is equivalent to running `make` only:
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```
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make RX_JESD_M=2 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=2 \
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TX_JESD_L=4 \
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TX_JESD_S=1
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```
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Corresponding device tree: [zynq-zc706-adv7511-fmcdaq2.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zc706-adv7511-fmcdaq2.dts)

‎projects/daq2/zcu102/README.md

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# DAQ2/ZCU102 HDL Project
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/daq2/zcu102
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make
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```
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This device operates in single link JESD204B mode, meaning 8b10b link layer encoding, using the ADI IP as Physical layer.
13+
14+
All of the RX link modes can be found in the [AD9680 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9680.pdf), Table 26. We offer support for only a few of them.
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All of the TX link modes can be found in the [AD9144 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9144.pdf), Table 35. We offer support for only a few of them.
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If other configurations are desired, then the parameters from the HDL project (see below) need to be changed, as well as the Linux/no-OS project configurations.
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The overwritable parameters from the environment are:
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- [RX/TX]_JESD_M - [RX/TX] number of converters per link
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- [RX/TX]_JESD_L - [RX/TX] number of lanes per link
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- [RX/TX]_JESD_S - [RX/TX] number of samples per converter per frame
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### Example configurations
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#### Default configuration
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This specific command is equivalent to running `make` only:
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```
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make RX_JESD_M=2 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=2 \
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TX_JESD_L=4 \
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TX_JESD_S=1
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```
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Corresponding device tree: [zynqmp-zcu102-rev10-fmcdaq2.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2.dts)
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#### TX, RX M=4 L=4
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```
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make RX_JESD_M=4 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=4 \
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TX_JESD_L=4 \
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TX_JESD_S=1
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```
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Corresponding device tree: [zynqmp-zcu102-rev10-fmcdaq2_m4_l4.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2_m4_l4.dts)

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