NET:ETH:ALTERA: SM Ethernet 10G : Base branch creation

Altera Ethernet X-Tile drivers with support for Agilex5 Ethernet transceivers

Signed-off-by: Krishna Kumar S R <[email protected]>

Author: KrishnaSimmadhari

Documentation/devicetree/bindings/phy/intel,qsfp-mem.txt

@@ -0,0 +1,16 @@
+* Intel QSFP Memory controller subsystem
+
+Required properties:
+- compatible: Should be "intel,qsfp-mem"
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+
+Example:
+
+		qsfp_eth0: qsfp-eth0 {
+			   compatible = "intel,qsfp-mem";
+			   reg-names = "qsfp-mem-controller";
+			   reg = <0x00000001 0x80112000 0x00001000>,
+			   status = "okay";
+		};

SECURITY.md

@@ -0,0 +1,5 @@
+ # Security Policy #
+ Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the    solution, impact, severity and mitigation.
+
+ ## Reporting a Vulnerability ##
+ Please report any security vulnerabilities in this project **[utilizing the guidelines here](https://www.intel.com/content/www/  us/en/security-center/vulnerability-handling-guidelines.html)**.

arch/arm64/boot/dts/intel/Makefile

@@ -1,7 +1,19 @@
 # SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
+dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_n6000_10G_ptp.dtb \
+				socfpga_agilex5_eth_1p10g.dtb \
+				socfpga_n6000_10G_rel3_ptp.dtb \
+				socfpga_n6000_25G_ptp.dtb \
+				socfpga_n6000_25G_rel3_ptp.dtb \
+				socfpga_fm87_ftile_10g.dtb \
+				socfpga_agilex_n6000.dtb \
 				socfpga_agilex_socdk.dtb \
 				socfpga_agilex_socdk_atfboot.dtb \
+				socfpga_fm87_ftile_10g_1port.dtb \
+				socfpga_fm87_ftile_25g_ptp.dtb \
+				socfpga_fm87_ftile_10g_2port_ptp.dtb \
+				socfpga_fm87_ftile_25g_2port_ptp.dtb \
+				socfpga_fm87_ftile_25g_2port_mcq_ptp.dtb \
+				socfpga_fm87_ftile_25g_1port_mcq_ptp.dtb \
 				socfpga_agilex_socdk_nand.dtb \
 				socfpga_agilex3_socdk.dtb \
 				socfpga_agilex5_socdk.dtb \

arch/arm64/boot/dts/intel/fm87_agilex_ftile.dtsi

@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2022, Intel Corporation
+ */
+
+/ {
+	model = "SoCFPGA Agilex SoCDK";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		hps0 {
+			label = "hps_led0";
+			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		hps1 {
+			label = "hps_led1";
+			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		hps2 {
+			label = "hps_led2";
+			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0 0 0>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy@0 {
+			reg = <4>;
+
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <900>; /* 0ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+		};
+	};
+};
+
+&mmc {
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	disable-over-current;
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+
+		m25p,fast-read;
+		cdns,page-size = <256>;
+		cdns,block-size = <16>;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x03FE0000>;
+			};
+
+			qspi_rootfs: partition@3FE0000 {
+				label = "Root Filesystem - JFFS2";
+				reg = <0x03FE0000 0x0C020000>;
+			};
+		};
+	};
+};
+
+&temp_volt {
+	voltage {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		input@2 {
+			label = "0.8V VCC";
+			reg = <2>;
+		};
+
+		input@3 {
+			label = "1.8V VCCIO_SDM";
+			reg = <3>;
+		};
+
+		input@4 {
+			label = "1.8V VCCPT";
+			reg = <4>;
+		};
+
+		input@5 {
+			label = "1.2V VCCCRCORE";
+			reg = <5>;
+		};
+
+		input@6 {
+			label = "0.9V VCCH";
+			reg = <6>;
+		};
+
+		input@7 {
+			label = "0.8V VCCL";
+			reg = <7>;
+		};
+	};
+
+	temperature {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		input@0 {
+			label = "Main Die SDM";
+			reg = <0x0>;
+		};
+
+		input@10000 {
+			label = "Main Die corner bottom left max";
+			reg = <0x10000>;
+		};
+
+		input@20000 {
+			label = "Main Die corner top left max";
+			reg = <0x20000>;
+		};
+
+		input@30000 {
+			label = "Main Die corner bottom right max";
+			reg = <0x30000>;
+		};
+
+		input@40000 {
+			label = "Main Die corner top right max";
+			reg = <0x40000>;
+		};
+	};
+};

arch/arm64/boot/dts/intel/fm87_ftile_10g_1port.dtsi

@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2022, Intel Corporation
+ */
+
+/* Add this piece of dtsi fragment as #include "fm87_ftile_25g_ptp.dtsi"
+ * in the file socfpga_fm87_ftile_25g_ptp.dts. Compile it in the kernel along with
+ * socfpga_agilex.dtsi
+ */
+
+/{
+	soc {
+		agilex_hps_bridges: bus@80000000 {
+			compatible = "simple-bus";
+			reg =	<0x80000000 0x60000000>,
+					<0xf9000000 0x00100000>;
+			reg-names = "axi_h2f", "axi_h2f_lw";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges =	<0x00000000 0x00000000 0xf9000000 0x00001000>,
+						<0x00000001 0x00000000 0x80000000 0x04000000>,
+						<0x00000001 0x00000000 0x84040000 0x00000040>,
+						<0x00000001 0x00000000 0x84040100 0x00000140>,
+						<0x00000001 0x04040050 0x84040050 0x00000010>,
+						<0x00000001 0x04040040 0x84040040 0x00000010>,
+						<0x00000001 0x00000000 0x84050000 0x00010000>,
+						<0x00000001 0x00000000 0x84060000 0x00010000>,
+						<0x00000001 0x00000000 0x84070000 0x00010000>;
+
+
+			qsfp_eth0: qsfp-eth0 {
+				compatible = "sff,qsfp";
+				i2c-bus = <&i2c0>;
+				qsfpdd_initmode-gpio = <&qsfpdd_ctrl_pio 1 GPIO_ACTIVE_HIGH>;
+				qsfpdd_modseln-gpio = <&qsfpdd_ctrl_pio 2 GPIO_ACTIVE_LOW>;
+				qsfpdd_modprsn-gpio = <&qsfpdd_status_pio 0 GPIO_ACTIVE_LOW>;
+				qsfpdd_resetn-gpio = <&qsfpdd_ctrl_pio 0 GPIO_ACTIVE_HIGH>;
+				qsfpdd_intn-gpio = <&qsfpdd_status_pio 1 GPIO_ACTIVE_LOW>;
+				agilex_hps_spim = <&qsfpdd_ctrl_pio 3 GPIO_ACTIVE_HIGH>;
+				maximum-power-milliwatt = <1000>;
+				status = "okay";
+			};
+
+			qsfpdd_status_pio: gpio@4040050 {
+			compatible = "altr,pio-1.0";
+				reg = <0x00000001 0x04040050 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 22 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				status = "okay";
+			};
+
+			qsfpdd_ctrl_pio: gpio@4040040 {
+				compatible = "altr,pio-1.0";
+				reg = <0x00000001 0x04040040 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 23 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				altr,interrupt_type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				status = "okay";
+			};
+		};
+
+		clocks {
+			tod_in_clock: tod_in_clock {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+				clock-frequency = <156250000>;
+				clock-output-names = "tod_in_clock";
+			};
+		};
+
+		hssiss_0_hssiss: hssiss_0_hssiss {
+			compatible = "intel, hssiss-1.0";
+			reg-names = "sscsr";
+			reg = <0x80000000 0x04000000>;
+			reset-mode ="reg";
+		};
+
+		hssi_0_eth: hssi_0_eth {
+			compatible = "altr,hssi-ftile-1.0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			tile_chan = <0x8>;
+			hssi_port = <0x8>;
+			phy-mode = "10gbase-r";
+			hssiss = <&hssiss_0_hssiss>;
+			pma_type = <0x0>; // FGT - 0x00, FHT = 0x1000
+			monitor_poll_interval = <10>;
+			ui-adj-interval=<250>;
+			altr,tx-pma-delay-ns = <0xD>;
+			altr,rx-pma-delay-ns = <0x8>;
+			altr,tx-pma-delay-fns = <0x24D>;
+			altr,rx-pma-delay-fns = <0x3E97>;
+			altr,tx-external-phy-delay-ns = <0x0>;
+			altr,rx-external-phy-delay-ns = <0x0>;
+			fec-cw-pos-rx = <0x0>;
+			fec-type="no-fec";
+			interrupt-parent = <&intc>;
+			interrupt-names = "dma0_tx_irq", "dma0_rx_irq";
+			interrupts = <0 24 4>, <0 25 4>;
+			qsfp-lane = <0x0>;
+			status = "okay";
+			num_channels = <1>;
+			fixed-link {
+				speed =<10000>;
+				full-duplex;
+			};
+			dma_0 {
+				reg-names =	"tx_pref",
+							"tx_csr",
+							"tx_fifo",
+							"rx_pref",
+							"rx_csr",
+							"rx_fifo";
+				reg =	<0x84480000 0x00000020>,
+						<0x84480020 0x00000020>,
+						<0x84480040 0x00000020>,
+						<0x84480080 0x00000020>,
+						<0x844800A0 0x00000020>,
+						<0x844800C0 0x00000010>;
+				rx-fifo-depth = <0x4000>;
+				tx-fifo-depth = <0x1000>;
+				rx-fifo-almost-full = <0x2000>;
+				rx-fifo-almost-empty = <0x1000>;
+			};
+		};
+	};
+};