Skip to content

Commit a57e215

Browse files
rodfrazer-intelrodfrazer-intel
committed
Initial commit
Signed-off-by: Rod Frazer <[email protected]>
1 parent 95dcf82 commit a57e215

File tree

324 files changed

+66115
-18
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

324 files changed

+66115
-18
lines changed

‎ACKNOWLEDGEMENTS

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
--------------------------------------------------------------------------------
2+
This project makes use of the following open source projects:
3+
--------------------------------------------------------------------------------
4+
5+
PROJECT: arm-trusted-firmware
6+
LOCATION: https://github.com/altera-opensource/arm-trusted-firmware
7+
LICENSE: BSD-3-Clause
8+
9+
PROJECT: u-boot-socfpga
10+
LOCATION: https://github.com/altera-opensource/u-boot-socfpga
11+
LICENSE: GPL-2.0
12+
13+
PROJECT: linux-socfpga
14+
LOCATION: https://github.com/altera-opensource/linux-socfpga
15+
LICENSE: GPL-2.0
16+
17+
PROJECT: toybox
18+
LOCATION: https://github.com/landley/toybox
19+
LICENSE: 0BSD
20+
21+
PROJECT: musl libc library and aarch64-linux-musleabi-cross cross compiler
22+
LOCATION: https://landley.net/toybox/downloads/binaries/toolchains/latest/aarch64-linux-musleabi-cross.tar.xz
23+
LICENSE: MIT
24+
25+
--------------------------------------------------------------------------------
26+
This project makes use of the following projects distributed in the Quartus
27+
software release from Altera:
28+
--------------------------------------------------------------------------------
29+
30+
PROJECT: niosv-hal
31+
LOCATION: Quartus installation
32+
LICENSE: MIT
33+
34+
PROJECT: newlib library and riscv32-unknown-elf-gcc cross compiler
35+
LOCATION: Quartus installation
36+
LICENSE: various MIT-like and BSD-like

‎CONTRIBUTING

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
To report an issue or request a change or feature request, please open a GitHub issue or pull request.

‎LICENSE

Lines changed: 12 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,16 @@
1-
MIT License
1+
MIT No Attribution
22

3-
Copyright (c) 2024 altera-fpga
3+
Copyright 2024 Intel Corporation
44

5-
Permission is hereby granted, free of charge, to any person obtaining a copy
6-
of this software and associated documentation files (the "Software"), to deal
7-
in the Software without restriction, including without limitation the rights
8-
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9-
copies of the Software, and to permit persons to whom the Software is
10-
furnished to do so, subject to the following conditions:
11-
12-
The above copyright notice and this permission notice shall be included in all
13-
copies or substantial portions of the Software.
5+
Permission is hereby granted, free of charge, to any person obtaining a copy of
6+
this software and associated documentation files (the "Software"), to deal in
7+
the Software without restriction, including without limitation the rights to
8+
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
9+
the Software, and to permit persons to whom the Software is furnished to do so.
1410

1511
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16-
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17-
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18-
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19-
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20-
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21-
SOFTWARE.
12+
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
13+
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
14+
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
15+
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16+
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

‎README.md

Lines changed: 65 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,66 @@
11
# agilex5-demo-hps2fpga-interfaces
2-
Altera Agilex 5 HPS-to-FPGA Interface Demos
2+
<!-- SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation -->
3+
<!-- SPDX-License-Identifier: MIT-0 -->
4+
5+
- **id**:
6+
- **title**: agilex5-demo-hps2fpga-interfaces
7+
- **source**: GitHub
8+
- **family**: Agilex 5
9+
- **quartus_version**: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
10+
- **devkit**: Agilex 5 FPGA E-Series 065B Premium Development Kit, and others
11+
- **device_part**: A5ED065BB32AE5SR0, A5ED065BB32AE4SR0, A5ED065BB32AE6SR0
12+
- **description**: Agilex 5 HPS-to-FPGA interfaces demos.
13+
- **rich_description**: This project is a demonstration and evaluation example that shows how users can implement and interact with the various hardware interfaces between the Hard Processing System (SoC) and FPGA fabric on the Agilex 5 FPGA device family.
14+
- **url**: https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces
15+
- **downloadURL**: https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces
16+
17+
## Project documentation
18+
19+
The project documentation index is available [**here**](./documentation/01_index.md).
20+
21+
## Project build instructions
22+
23+
The project build instructions are documented [**here**](./documentation/17_building_project.md).
24+
25+
## Currently supported boards
26+
27+
| Repo Directory | Board Info |
28+
| :--- | :--- |
29+
| brd_altera_a5e065_premium_es | **Company:** Altera, An Intel Company<br>**Board Name:** Agilex* 5 FPGA E-Series 065B Premium Development Kit<br>**OPN:** DK-A5E065BB32AES1<br>**Comment:** ES device |
30+
| brd_arrow_axe5_eagle_es | **Company:** Arrow Electronics, Inc.<br>**Board Name:** Arrow AXE5-Eagle Development Platform<br>**OPN:** AXE5-EAGLE-ES<br>**Comment:** ES device |
31+
| brd_criticallink_mitysbc_es | **Company:** Critical Link, LLC<br>**Board Name:** MitySBC-A5E Single Board Computer<br>**OPN:** A5ED-B9-C7F-RC-SBC-X<br>**Comment:** ES device |
32+
| brd_macnica_sulfur_es_125 | **Company:** Macnica, Inc.<br>**Board Name:** Macnica Mpression Sulfur Kit / Type A<br>**OPN:** ALTSULFUR_A5ED065B_E5_ES0_typeA<br>**Comment:** ES device - 125MHz SDM_OSC_CLK |
33+
| brd_macnica_sulfur_es_25 | **Company:** Macnica, Inc.<br>**Board Name:** Macnica Mpression Sulfur Kit / Type A<br>**OPN:** ALTSULFUR_A5ED065B_E5_ES0_typeA<br>**Comment:** ES device - 25MHz SDM_OSC_CLK |
34+
35+
**Trademarks and disclaimers**\
36+
All trademarks are the property of their respective owners.\
37+
All brands or product names are the property of their respective holders.
38+
39+
## Getting Started
40+
41+
The primary use case for this demo is to download the prebuilt binary image for the board of interest and program it into the SDM QSPI flash on the board and execute the various demos. The project documentation referenced above explains what the demos do and how they do it and source code for all the hardware and software demos is provided within the repo.
42+
43+
The prebuilt binary images are uploaded to the release section of the repo:\
44+
[https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/releases](https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/releases)
45+
46+
Locate the archive of the JIC image for your board and download it.
47+
48+
Extract the archive:
49+
```text
50+
[]$ unzip <jic-archive>
51+
```
52+
53+
Program the JIC image into the SDM QSPI flash:
54+
```text
55+
[]$ quartus_pgm -m jtag -c <cable-number> -o pi\;<jic-image>
56+
```
57+
58+
If your board is already programmed with an image that configures the HPS onto the JTAG chain, then you may need to point the JIC image programming into the second device location:
59+
```text
60+
[]$ quartus_pgm -m jtag -c <cable-number> -o pi\;<jic-image>@2
61+
```
62+
63+
It may be necessary to slow down the JTAG clock while programming the JIC image into the flash device if you experience programming failures. Do that like this:
64+
```text
65+
[]$ jtagconfig --setparam <cable-number> JtagClock 16M
66+
```

‎SECURITY.md

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# Security Policy
2+
Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation.
3+
4+
## Reporting a Vulnerability
5+
Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html).
6+

‎brd_altera_a5e065_premium_es/hw_base/DDR4-1866M_933MHz_CL13_alloff_component_1CS_DDP_32Gb_2Gx16.qprs

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
1+
<?xml version="1.0" encoding="UTF-8"?>
2+
<ip><presets version="12.1">
3+
<preset name="DDR4-1866M_933MHz_CL13_alloff_component_1CS_DDP_32Gb_2Gx16" kind="emif_ph2_phy_arch_fp" version="All" description="Custom Preset">
4+
<parameter name="SHOW_INTERNAL_SETTINGS" value="false" />
5+
<parameter name="MEM_TECHNOLOGY" value="MEM_TECHNOLOGY_DDR4" />
6+
<parameter name="MEM_FORMAT" value="MEM_FORMAT_DISCRETE" />
7+
<parameter name="MEM_DEVICE_DQ_WIDTH" value="16" />
8+
<parameter name="MEM_RANKS_PER_DIMM" value="0" />
9+
<parameter name="PHY_MEMCLK_FREQ_MHZ" value="933.0" />
10+
<parameter name="DDR4_MEM_DEVICE_PACKAGE" value="2D1R" />
11+
<parameter name="DDR4_MEM_DEVICE_NUM_DIE_PER_COMP" value="2" />
12+
<parameter name="DDR4_MEM_DEVICE_NUM_RANK_PER_COMP" value="1" />
13+
<parameter name="DDR4_MEM_DEVICE_IS_3DS" value="false" />
14+
<parameter name="DDR4_MEM_DEVICE_DIE_DENSITY_GBITS" value="16" />
15+
<parameter name="DDR4_MEM_DEVICE_SPD137_RCD_CA_DRV" value="0" />
16+
<parameter name="DDR4_MEM_DEVICE_SPD138_RCD_CK_DRV" value="0" />
17+
<parameter name="DDR4_MEM_DEVICE_DIE_DQ_WIDTH" value="8" />
18+
<parameter name="DDR4_MEM_DEVICE_DQ_WIDTH" value="16" />
19+
<parameter name="DDR4_MEM_DEVICE_COMPONENT_DQ_WIDTH" value="16" />
20+
<parameter name="DDR4_MEM_DEVICE_DQ_PER_DQS" value="8" />
21+
<parameter name="DDR4_MEM_DEVICE_CHIP_ID_WIDTH" value="0" />
22+
<parameter name="DDR4_MEM_DEVICE_COMPONENT_DENSITY_GBITS" value="32" />
23+
<parameter name="DDR4_MEM_DEVICE_LOGICAL_RANK_DENSITY_GBITS" value="16" />
24+
<parameter name="DDR4_MEM_DEVICE_BANK_GROUP_ADDR_WIDTH" value="2" />
25+
<parameter name="DDR4_MEM_DEVICE_BANK_ADDR_WIDTH" value="2" />
26+
<parameter name="DDR4_MEM_DEVICE_ROW_ADDR_WIDTH" value="17" />
27+
<parameter name="DDR4_MEM_DEVICE_COL_ADDR_WIDTH" value="10" />
28+
<parameter name="DDR4_MEM_DEVICE_CK_WIDTH" value="1" />
29+
<parameter name="DDR4_MEM_DEVICE_READ_DBI_EN" value="false" />
30+
<parameter name="DDR4_MEM_DEVICE_DM_WRITE_DBI" value="NODM_NOWDBI" />
31+
<parameter name="DDR4_MEM_DEVICE_DM_EN" value="false" />
32+
<parameter name="DDR4_MEM_DEVICE_WRITE_DBI_EN" value="false" />
33+
<parameter name="DDR4_MEM_DEVICE_WR_PREAMBLE_CYC" value="0" />
34+
<parameter name="DDR4_MEM_DEVICE_RD_PREAMBLE_CYC" value="0" />
35+
<parameter name="DDR4_MEM_DEVICE_BURST_LENGTH" value="8" />
36+
<parameter name="DDR4_MEM_DEVICE_AC_PARITY_EN" value="false" />
37+
<parameter name="DDR4_MEM_DEVICE_SPEEDBIN" value="1866M" />
38+
<parameter name="DDR4_MEM_DEVICE_CL_CYC" value="13" />
39+
<parameter name="DDR4_MEM_DEVICE_CWL_CYC" value="10" />
40+
<parameter name="DDR4_MEM_DEVICE_AL_CYC" value="0" />
41+
<parameter name="DDR4_MEM_DEVICE_WR_CRC_EN" value="false" />
42+
<parameter name="DDR4_MEM_DEVICE_FINE_GRANULARITY_REFRESH_MODE" value="1" />
43+
<parameter name="DDR4_MEM_DEVICE_GEARDOWN_MODE" value="" />
44+
<parameter name="DDR4_MEM_DEVICE_DATA_RATE_BIN" value="1866" />
45+
<parameter name="DDR4_MEM_DEVICE_AC_PARITY_LATENCY_MODE" value="0" />
46+
<parameter name="DDR4_MEM_DEVICE_RCD_PARITY_CONTROL_WORD" value="13" />
47+
<parameter name="DDR4_MEM_DEVICE_RCD_PARITY_LATENCY_CYC" value="0" />
48+
<parameter name="DDR4_MEM_DEVICE_TREFI_US" value="7.8" />
49+
<parameter name="DDR4_MEM_DEVICE_TRAS_NS" value="34.0" />
50+
<parameter name="DDR4_MEM_DEVICE_TRCD_NS" value="13.92" />
51+
<parameter name="DDR4_MEM_DEVICE_TRP_NS" value="13.92" />
52+
<parameter name="DDR4_MEM_DEVICE_TRC_NS" value="47.92" />
53+
<parameter name="DDR4_MEM_DEVICE_TCCD_L_CYC" value="5" />
54+
<parameter name="DDR4_MEM_DEVICE_TCCD_S_CYC" value="4" />
55+
<parameter name="DDR4_MEM_DEVICE_TRRD_L_CYC" value="5" />
56+
<parameter name="DDR4_MEM_DEVICE_TRRD_S_CYC" value="4" />
57+
<parameter name="DDR4_MEM_DEVICE_TFAW_NS" value="23.0" />
58+
<parameter name="DDR4_MEM_DEVICE_TWTR_L_CYC" value="7" />
59+
<parameter name="DDR4_MEM_DEVICE_TWTR_L_CRC_DM_CYC" value="5" />
60+
<parameter name="DDR4_MEM_DEVICE_TWTR_S_CYC" value="3" />
61+
<parameter name="DDR4_MEM_DEVICE_TWTR_S_CRC_DM_CYC" value="5" />
62+
<parameter name="DDR4_MEM_DEVICE_TRTP_CYC" value="7" />
63+
<parameter name="DDR4_MEM_DEVICE_TWR_NS" value="15.0" />
64+
<parameter name="DDR4_MEM_DEVICE_TWR_CRC_DM_CYC" value="5" />
65+
<parameter name="DDR4_MEM_DEVICE_TMRD_CYC" value="8" />
66+
<parameter name="DDR4_MEM_DEVICE_TCKSRE_CYC" value="10" />
67+
<parameter name="DDR4_MEM_DEVICE_TCKSRX_CYC" value="10" />
68+
<parameter name="DDR4_MEM_DEVICE_TCKE_CYC" value="5" />
69+
<parameter name="DDR4_MEM_DEVICE_TCKESR_CYC" value="6" />
70+
<parameter name="DDR4_MEM_DEVICE_TMPRR_CYC" value="1" />
71+
<parameter name="DDR4_MEM_DEVICE_TRFC_NS" value="550.0" />
72+
<parameter name="DDR4_MEM_DEVICE_TDIVW_TOTAL_UI" value="0.2" />
73+
<parameter name="DDR4_MEM_DEVICE_TDQSCK_PS" value="0" />
74+
<parameter name="DDR4_MEM_DEVICE_TDQSQ_UI" value="0.16" />
75+
<parameter name="DDR4_MEM_DEVICE_TDQSS_CYC" value="0.0" />
76+
<parameter name="DDR4_MEM_DEVICE_TDSH_CYC" value="0.18" />
77+
<parameter name="DDR4_MEM_DEVICE_TDSS_CYC" value="0.18" />
78+
<parameter name="DDR4_MEM_DEVICE_TDVWP_UI" value="0.66" />
79+
<parameter name="DDR4_MEM_DEVICE_TIH_DC_MV" value="75" />
80+
<parameter name="DDR4_MEM_DEVICE_TIH_PS" value="125" />
81+
<parameter name="DDR4_MEM_DEVICE_TIS_AC_MV" value="100" />
82+
<parameter name="DDR4_MEM_DEVICE_TIS_PS" value="100" />
83+
<parameter name="DDR4_MEM_DEVICE_TQH_UI" value="0.76" />
84+
<parameter name="DDR4_MEM_DEVICE_TQSH_CYC" value="0.4" />
85+
<parameter name="DDR4_MEM_DEVICE_TWLH_CYC" value="0.13" />
86+
<parameter name="DDR4_MEM_DEVICE_TWLS_CYC" value="0.13" />
87+
<parameter name="DDR4_MEM_DEVICE_VDIVW_TOTAL_MV" value="136" />
88+
<parameter name="DDR4_MEM_DEVICE_TRFC_DLR_NS" value="190.0" />
89+
<parameter name="DDR4_MEM_DEVICE_TRRD_DLR_CYC" value="4" />
90+
<parameter name="DDR4_MEM_DEVICE_TFAW_DLR_NS" value="17.152" />
91+
<parameter name="DDR4_MEM_DEVICE_TCCD_DLR_NS" value="4.288" />
92+
<parameter name="DDR4_MEM_DEVICE_TXP_CYC" value="6" />
93+
<parameter name="DDR4_MEM_DEVICE_TXS_NS" value="560.0" />
94+
<parameter name="DDR4_MEM_DEVICE_TXS_DLL_CYC" value="597" />
95+
<parameter name="DDR4_MEM_DEVICE_TCPDED_CYC" value="4" />
96+
<parameter name="DDR4_MEM_DEVICE_TMOD_CYC" value="24" />
97+
<parameter name="DDR4_MEM_DEVICE_TZQCS_CYC" value="128" />
98+
<parameter name="DDR4_MEM_DEVICE_TZQINIT_CYC" value="1024" />
99+
<parameter name="DDR4_MEM_DEVICE_TZQOPER_CYC" value="512" />
100+
<parameter name="DDR4_MEM_DEVICE_TCK_CL_CWL_MIN_NS" value="1.071" />
101+
<parameter name="DDR4_MEM_DEVICE_TCK_CL_CWL_MAX_NS" value="1.25" />
102+
<parameter name="DDR4_MEM_DEVICE_TRAS_MAX_NS" value="70200.0" />
103+
<parameter name="DDR4_MEM_DEVICE_TCCD_L_NS" value="5.36" />
104+
<parameter name="DDR4_MEM_DEVICE_TRRD_S_NS" value="4.288" />
105+
<parameter name="DDR4_MEM_DEVICE_TRRD_L_NS" value="5.36" />
106+
<parameter name="DDR4_MEM_DEVICE_TFAW_CYC" value="22.0" />
107+
<parameter name="DDR4_MEM_DEVICE_TWTR_L_NS" value="7.5040000000000004" />
108+
<parameter name="DDR4_MEM_DEVICE_TWTR_L_CRC_DM_NS" value="5.36" />
109+
<parameter name="DDR4_MEM_DEVICE_TWTR_S_NS" value="3.216" />
110+
<parameter name="DDR4_MEM_DEVICE_TWTR_S_CRC_DM_NS" value="5.36" />
111+
<parameter name="DDR4_MEM_DEVICE_TRTP_NS" value="7.5040000000000004" />
112+
<parameter name="DDR4_MEM_DEVICE_TWR_CRC_DM_NS" value="5.36" />
113+
<parameter name="DDR4_MEM_DEVICE_TCKSRE_NS" value="10.72" />
114+
<parameter name="DDR4_MEM_DEVICE_TCKSRX_NS" value="10.72" />
115+
<parameter name="DDR4_MEM_DEVICE_TCKE_NS" value="5.36" />
116+
<parameter name="DDR4_MEM_DEVICE_TXP_NS" value="6.432" />
117+
<parameter name="DDR4_MEM_DEVICE_TMOD_NS" value="25.728" />
118+
<parameter name="DDR4_MEM_DEVICE_CAL_MODE" value="0" />
119+
</preset>
120+
</presets></ip>

0 commit comments

Comments
 (0)