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| 1 | +# menu-T on hw_emac |
| 2 | +<!-- SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation --> |
| 3 | +<!-- SPDX-License-Identifier: MIT-0 --> |
| 4 | + |
| 5 | +Return to [**Index**](01_index.md) |
| 6 | + |
| 7 | +Hardware projects referenced from this document: |
| 8 | +* common_pd_subsystems/hw_emac |
| 9 | + |
| 10 | +u-boot software applications referenced from this document: |
| 11 | +* common_sw/u-boot_standalone_apps/emac.c |
| 12 | + |
| 13 | +Linux software applications referenced from this document: |
| 14 | +* common_sw/linux_apps/emac.c |
| 15 | + |
| 16 | +## Overview |
| 17 | + |
| 18 | +The menu-T demo demonstrates the functionality of the HPS EMAC peripheral. It does this by connecting the HPS EMAC peripheral to an FPGA based design that contains a GMII loopback peripheral. This allows the HPS EMAC core to transmit packets to itself through the FPGA core logic design. |
| 19 | + |
| 20 | +## Hardware system |
| 21 | + |
| 22 | +The menu-T, emac demo, connects the HPS EMAC to a custom Platform Designer peripheral that provides a loopback for the GMII interface exposed into the FPGA logic. |
| 23 | + |
| 24 | +| hw_emac top level | |
| 25 | +| :---: | |
| 26 | +|  | |
| 27 | + |
| 28 | +Inside the emac subsystem, we instantiate a component that splits the hps_gp_in and hps_gp_out interfaces from the hps_gp conduit. The hps_gp_in interface receives input from a constant component. We also see the hps_emac_loop core that provides the GMII loopback functionality. |
| 29 | + |
| 30 | +| emac subsystem | |
| 31 | +| :---: | |
| 32 | +|  | |
| 33 | + |
| 34 | + |
| 35 | +## Software demo - u-boot standalone - menu-T |
| 36 | + |
| 37 | +In the u-boot standalone application we bit bang the HPS EMAC registers to send packets through the HPS EMAC peripheral. |
| 38 | + |
| 39 | +A 32KB buffer in HPS EMIF memory is filled with randomized data and each 1KB block is edited to create a viable Ethernet frame header with destination and source MAC addresses and a valid length field. Then a transmit descriptor ring is created in the HPS EMIF memory to point to the 32 transmit packets and a receive descriptor ring is created in the HPS EMIF memory to point to a 32KB buffer that can receive the 32 1KB packets that are transmitted. The HPS EMAC is then configured to enable its DMA and packet transmission and reception. Once the transmit and receive descriptor rings are completed, the 32KB receive buffer is compare against the 32KB transmit buffer to validate the proper transmission and reception of the test data. |
| 40 | + |
| 41 | +The packet construction, transmission and reception described above is transmitted through the HPS EMAC using two different PHY interface configurations in the system manager. The first configuration sets the PHY interface in the RESET state which requires us to configure the HPS EMAC to use its internal loopback to loop the transmitted packets back into itself. The second configuration sets the PHY interface to the GMII state which connects the HPS EMAC to the FPGA logic design and the FPGA logic performs the loopback into the HPS EMAC for us. |
| 42 | + |
| 43 | +The output from this demo is shown below. The value of the signature read back from the hps_gp_in constant is displayed. The time to transmit and receive the 32KB buffer through the internal HPS EMAC loopback and the FPGA based GMII loopback is displayed. And the time to flush the data cache and perform the buffer comparison is also displayed. |
| 44 | + |
| 45 | +```text |
| 46 | +HPS EMAC Demo |
| 47 | +
|
| 48 | +HPS_GP_IN signature value = 0x43414D45 : EMAC |
| 49 | +
|
| 50 | +No errors detected... |
| 51 | +
|
| 52 | + DCACHE FLUSH TIME: 20320.000ns |
| 53 | + BUFFER COMPARE TIME: 215917.500ns |
| 54 | +HPS EMAC INTERNAL LOOP TIME: 251872.500ns : 0.121GB/s |
| 55 | + DCACHE FLUSH TIME: 20325.000ns |
| 56 | + BUFFER COMPARE TIME: 217412.500ns |
| 57 | + GMII LOOP TIME: 251082.500ns : 0.121GB/s |
| 58 | +
|
| 59 | +Press any key to exit this demo. |
| 60 | +``` |
| 61 | + |
| 62 | +## Software demo - Linux - menu-T |
| 63 | + |
| 64 | +The Linux version of this demo is essentially the same as the u-boot standalone application except in Linux we must map a virtual address to access the physical addresses of the peripherals. We use the uio driver to facilitate that for us. |
| 65 | + |
| 66 | +We also cannot control the phy_intf_sel register in the system manager from user space, so the Linux version determines what state the PHY interface is configured for and runs the demo based on that configuration. |
| 67 | + |
| 68 | +The output from this demo is shown below. The value of the signature read back from the hps_gp_in constant is displayed. The time to transmit and receive the 32KB buffer through the internal HPS EMAC loopback or the FPGA based GMII loopback is displayed based on the phy_intf_sel configuration. And the time to perform the buffer comparison is also displayed. |
| 69 | + |
| 70 | +This is the result from running through the internal HPS EMAC loopback: |
| 71 | +```text |
| 72 | +HPS EMAC Demo |
| 73 | +
|
| 74 | +HPS_GP_IN signature value = 0x43414D45 : EMAC |
| 75 | +
|
| 76 | +No errors detected... |
| 77 | +
|
| 78 | + BUFFER COMPARE TIME: 14805695.000ns |
| 79 | +HPS EMAC INTERNAL LOOP TIME: 253562.500ns : 0.120GB/s |
| 80 | +
|
| 81 | + This demo used the HPS EMAC internal loopback because the |
| 82 | + phy_intf_sel field of the tsn0 register in the system manager was |
| 83 | + NOT configured for GMII mode. The tsn0 register at 0x10D12044 can be |
| 84 | + read from user mode but it requires secure/privileged state to write |
| 85 | + that register. |
| 86 | +
|
| 87 | + To run this demo with the GMII loopback provided in the FPGA logic |
| 88 | + design, reboot the board and run the hps emac demo in the u-boot |
| 89 | + environment first and then boot into Linux and run this demo again. |
| 90 | + When the u-boot version of this demo runs, it runs using the |
| 91 | + internal HPS EMAC loopback first and then uses the GMII loopback and |
| 92 | + leaves the phy_intf_sel configuration set to GMII. |
| 93 | +
|
| 94 | +Press any key to exit this demo. |
| 95 | +``` |
| 96 | + |
| 97 | +This is the result from running through the GMII loopback in the FPGA logic: |
| 98 | +```text |
| 99 | +HPS EMAC Demo |
| 100 | +
|
| 101 | +HPS_GP_IN signature value = 0x43414D45 : EMAC |
| 102 | +
|
| 103 | +No errors detected... |
| 104 | +
|
| 105 | + BUFFER COMPARE TIME: 23352462.500ns |
| 106 | + GMII LOOP TIME: 249302.500ns : 0.122GB/s |
| 107 | +
|
| 108 | + This demo used the GMII loopback provided in the FPGA logic because |
| 109 | + the phy_intf_sel field of the tsn0 register in the system manager |
| 110 | + was configured for GMII mode. The tsn0 register at 0x10D12044 can be |
| 111 | + read from user mode but it requires secure/privileged state to write |
| 112 | + that register. |
| 113 | +
|
| 114 | + To run this demo with the HPS EMAC internal loopback, reboot the |
| 115 | + board and DO NOT run the hps emac demo in the u-boot environment |
| 116 | + before booting into Linux and run this demo again. When the u-boot |
| 117 | + version of this demo runs, it runs using the internal HPS EMAC |
| 118 | + loopback first and then uses the GMII loopback and leaves the |
| 119 | + phy_intf_sel configuration set to GMII. |
| 120 | +
|
| 121 | +Press any key to exit this demo. |
| 122 | +``` |
| 123 | + |
| 124 | +--- |
| 125 | +Return to [**Index**](01_index.md) |
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