Python代码bug for循环局部变量i多次使用

[Yang-Xijie]

Verilog-OJ/assets/2to1mux.yml

Lines 247 to 277 in 109225e

	for i in range(0, local_time_max + 1):
	if sig_inst['data'][cur_step_ptr][0] > i:
	# maintain current value
	for i in range(0, width):
	waves[i] += "."
	else:
	new_wave = self.parseValue(sig_inst['data'][cur_step_ptr][1])
	if new_wave == cur_wave:
	waves[i] += "."
	else:
	# do bitwise comparation
	if cur_wave == "SOMETHING_NEVER_HAPPEN":
	# new_wave_bin[0] is MSB
	new_wave_bin = self.toBinRepr(new_wave, width)
	for i in range(0, width):
	waves[i] += new_wave_bin[::-1][i]
	else:
	cur_wave_bin = self.toBinRepr(cur_wave, width)
	new_wave_bin = self.toBinRepr(new_wave, width)
	for i in range(0, width):
	old = cur_wave_bin[::-1][i]
	new = new_wave_bin[::-1][i]
	if old != new:
	waves[i] += new
	else:
	waves[i] += '.'
	cur_wave = new_wave
	cur_step_ptr += 1

在上面的代码中，for i in range(0, local_time_max + 1): 使用变量i作为局部变量。但是下方多次再次使用i作为局部变量。在大多数module中，这并未引发问题，VCD文件可以转为WaveJSON。一个出现问题的例子如下：

top_module = "population_count"
    signal_names = ["in", "out"]
    code_reference = """
module population_count(
    input [2:0] in,
    output [1:0] out
);
    assign out = in[2] + in[1] + in[0];
endmodule
    """

    code_student = code_reference

    testbench = """
module testbench();
    reg [2:0] in;
    wire [1:0] out;
    population_count PopCount(in, out);
    
    initial begin
        $dumpfile(`DUMP_FILE_NAME);
        $dumpvars;
    end

    integer i;
    initial begin
        for (i = 0; i < 8; i = i + 1) begin
            #1 in = i;
        end
    end
endmodule
    """

解决方案

将（247行）

for i in range(0, local_time_max + 1): 
    if sig_inst['data'][cur_step_ptr][0] > i: 

改为

for time_i in range(0, local_time_max + 1): 
    if sig_inst['data'][cur_step_ptr][0] > time_i: 

将（254行）

if new_wave == cur_wave: 
    waves[i] += "." 

改为

if new_wave == cur_wave:
    for i in range(0, width):
        waves[i] += "."

其他保持不变。

---

不方便提issue，因为在所有题目中都有。

[libreliu]

谢谢反馈！我们之后找个时间统一来处理处理 XD