add XedaException and catch in CLI

[openxc7] prtimitive CHIPDB generation logic

restore oritingal nextpnr and openfpgaloader flows

separate openxc7 flow

[ghdl synth] fix elaboration args

WIP: support for openxc7/f4pga flows for AMD FPGAs

fix vivado test

[vivado_synth] improved handling of user XDC and TCL

fix cocotb nvc

[vivado_synth] add out_of_context option for project-based synth flow

[remote] default serialization

tweak yosys FPGA flow and fix outdated flag

yosys: initial support for [yosys-slang] plugin

convert str value for list fields to a list by splitting around ','

[Vivado] Revert Vivado path changes

Python 2.13

[nvc] add more settings

fixes and cleanup

new NVC VHDL simulator flow

fix fpga parsing

[VivadoSim] more robust quoting

fix typo

[Vivado.sim] re-enable checks for tb.top

[tests] prepate fake_tools dir to $PATH

[Vivado][Yosys] Quote source filename in case their paths contain spaces

improve yosys settings and parsing

Update pydantic requirement from <2.0,>=1.10 to >=1.10,<3.0

Update cattrs requirement from <24.0,>=22.2 to >=22.2,<25.0

Update attrs requirement from <24.0,>=22.1 to >=22.1,<25.0