minor update

Author: tinebp

hw/syn/xilinx/xrt/Makefile

@@ -91,7 +91,6 @@ VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
 
 # register compilation hooks
 VPP_FLAGS += --xp "vivado_prop:run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=${SRC_DIR}/pre_opt_hook.tcl"
-VPP_FLAGS += --xp "vivado_prop:run.impl_1.STEPS.ROUTE_DESIGN.TCL.POST=${SRC_DIR}/post_route_hook.tcl"
 
 # load platform settings
 include $(SRC_DIR)/platforms.mk
@@ -184,6 +183,7 @@ ifeq ($(TARGET), hw)
 	cp $(BUILD_DIR)/_x/reports/link/syn/ulp_vortex_afu_1_0_synth_1_ulp_vortex_afu_1_0_utilization_synth.rpt $(BUILD_DIR)/bin
 	cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_utilization_placed.rpt $(BUILD_DIR)/bin
 	cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin
+	cp $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/hier_utilization.rpt $(BUILD_DIR)/bin
 endif
 
 chipscope:

hw/syn/xilinx/xrt/post_route_hook.tcl

@@ -1,2 +1,4 @@
 set tool_dir $::env(TOOL_DIR)
-source ${tool_dir}/xilinx_async_bram_patch.tcl
+source ${tool_dir}/xilinx_async_bram_patch.tcl
+
+report_utilization -file hier_utilization.rpt -hierarchical -hierarchical_percentages