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perf(dsr1): update B200 FP4 SGLang image to v0.5.21-cu130
Pin lmsysorg/sglang:v0.5.21-cu130 by digest and replace the removed --cuda-graph-max-bs and --disable-piecewise-cuda-graph flags with their v0.5.19 alias targets --cuda-graph-max-bs-decode and --cuda-graph-backend-prefill=disabled. 将 B200 FP4 SGLang 镜像更新至按摘要固定的 lmsysorg/sglang:v0.5.21-cu130, 并将已移除的 --cuda-graph-max-bs 与 --disable-piecewise-cuda-graph 替换为 v0.5.19 中它们所映射的 --cuda-graph-max-bs-decode 与 --cuda-graph-backend-prefill=disabled。 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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‎inferencex-e2e/benchmarks/single_node/srt-slurm-recipes/dsr1/sglang/b200-fp4/8k1k.yaml‎

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name: dsr1-fp4-b200-sglang-8k1k
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model:
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path: hf:nvidia/DeepSeek-R1-0528-FP4-V2
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container: lmsysorg/sglang:v0.5.19-cu130
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container: lmsysorg/sglang:v0.5.21-cu130@sha256:b1259f3ea3275f66237c498ea388919729018bc9f01c3d638391e06e2cf3f469
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precision: fp4
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resources:
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gpu_type: b200
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trust-remote-code: true
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tensor-parallel-size: 4
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data-parallel-size: 1
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cuda-graph-max-bs: 256
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cuda-graph-max-bs-decode: 256
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max-running-requests: 256
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mem-fraction-static: 0.85
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kv-cache-dtype: fp8_e4m3
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enable-flashinfer-allreduce-fusion: true
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scheduler-recv-interval: 10
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enable-symm-mem: true
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disable-piecewise-cuda-graph: true
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cuda-graph-backend-prefill: disabled
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attention-backend: trtllm_mla
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moe-runner-backend: flashinfer_trtllm
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stream-interval: 10

‎inferencex-e2e/configs/nvidia-master.yaml‎

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ep: 8
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dp-attn: true
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dsr1-fp4-b200-sglang:
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image: lmsysorg/sglang:v0.5.19-cu130
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image: lmsysorg/sglang:v0.5.21-cu130@sha256:b1259f3ea3275f66237c498ea388919729018bc9f01c3d638391e06e2cf3f469
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model: nvidia/DeepSeek-R1-0528-FP4-V2
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model-prefix: dsr1
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runner: cluster:b200-nscale

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