fix(configs): select each GB200 DSR1 FP8 low-latency variant explicitly

The low-latency row named disagg-tp8-stp-variants.yaml without a selector, so one job submitted all three zip variants under a 4-node, 1-decode-worker label. Each variant now runs only the concurrencies it is tuned for, with its selector and its 7 TP8 decode workers on 16 nodes: zip_override_lowlat[0] (c8) at 4 and 8, zip_override_lowlat[1] (c16-32) at 16. zip_override_lowlat[2] is tuned for concurrency 64, which the entry never ran, so it has no row.

Author: adibarra

inferencex-e2e/configs/nvidia-master.yaml

@@ -2656,20 +2656,32 @@ dsr1-fp8-gb200-dynamo-sglang:
     - isl: 8192
       osl: 1024
       search-space:
-     # "Low latency" (1 prefill worker at TP8 and 1 decode worker at TP8)
-      - conc-list: [4, 8, 16]
+     # "Low latency" (1 prefill worker at TP8 and 7 decode workers at TP8)
+      - conc-list: [4, 8]
         # https://github.com/NVIDIA/srt-slurm/blob/sa-submission-q2-2026/recipes/gb200-fp8/8k1k/low-latency.yaml
-        srt-recipe: disagg-tp8-stp-variants.yaml
+        srt-recipe: disagg-tp8-stp-variants.yaml:zip_override_lowlat[0]
         prefill:
           num-worker: 1
           tp: 8
           ep: 1
           dp-attn: false
         decode:
+          num-worker: 7
+          tp: 8
+          ep: 1
+          dp-attn: false
+      - conc-list: [16]
+        srt-recipe: disagg-tp8-stp-variants.yaml:zip_override_lowlat[1]
+        prefill:
           num-worker: 1
           tp: 8
           ep: 1
           dp-attn: false
+        decode:
+          num-worker: 7
+          tp: 8
+          ep: 1
+          dp-attn: false
 
       # "Mid curve" (5 prefill workers at DEP8 and 1 decode worker at DEP32)
       - conc-list: [512, 1024, 2048, 6144]