@@ -71,6 +71,7 @@ rediscovering the same issue.
 | `FUZZX_ALLOW_M012_ADD_SHL_LADDER=1` | unset | Alias to re-enable the broader `add/shl` ladder shape for [m012](known-miscompiles/m012-add-shl-ladder/NOTES.md). |
 | `FUZZX_ALLOW_M013_PRIVATE_MEMORY_FSHL=1` | unset | Re-enable three-or-more private-memory/funnel-shift ops for [m013](known-miscompiles/m013-private-memory-fshl/NOTES.md). |
 | `FUZZX_ALLOW_M014_SHL_ADD_CTPOP=1` | unset | Re-enable four-step `shl/add` chains feeding `ctpop` for [m014](known-miscompiles/m014-shl-add-ctpop/NOTES.md). |
+| `FUZZX_ALLOW_M015_SCALAR_FSHL_ZERO=1` | unset | Re-enable zero-count `fshl` generation for [m015](known-miscompiles/m015-scalar-fshl-zero/NOTES.md). |
 
 ## Layout
 
@@ -107,6 +108,7 @@ Version | Description |
 | LLVM 23.0.0git | [m012-add-shl-ladder](known-miscompiles/m012-add-shl-ladder/NOTES.md): `-O0` scalarizes a divergent `add/shl` ladder through `v_readfirstlane_b32`. |
 | ROCm 7.1.1 / LLVM 23.0.0git | [m013-private-memory-fshl](known-miscompiles/m013-private-memory-fshl/NOTES.md): `-O0` lowers fixed private-memory allocas through a dynamic scratch stack sequence that can return intermittent wrong values. |
 | LLVM 23.0.0git | [m014-shl-add-ctpop](known-miscompiles/m014-shl-add-ctpop/NOTES.md): `-O0` scalarizes a four-step `shl/add` chain feeding `ctpop` through lane 0. |
+| LLVM 23.0.0git | [m015-scalar-fshl-zero](known-miscompiles/m015-scalar-fshl-zero/NOTES.md): `-O0` lowers scalar `fshl.i32(x, y, 0)` through a 64-bit shift-by-`-1` sequence that returns zero. |
 
 ## LLVM Source Builds
 
 
@@ -402,6 +402,24 @@ ConstantInt *ci64(LLVMContext &Ctx, uint64_t V) {
   return ConstantInt::get(Type::getInt64Ty(Ctx), V);
 }
 
+bool allowM015ScalarFshlZero() {
+  static const bool Allow =
+      envFlag("FUZZX_ALLOW_M015_SCALAR_FSHL_ZERO", false);
+  return Allow;
+}
+
+Value *suppressM015FshlZeroShift(IRBuilder<> &B, Value *Shift) {
+  if (allowM015ScalarFshlZero())
+    return Shift;
+
+  LLVMContext &Ctx = B.getContext();
+  if (auto *CI = dyn_cast<ConstantInt>(Shift))
+    return CI->isZero() ? ci32(Ctx, 1) : Shift;
+
+  Value *IsZero = B.CreateICmpEQ(Shift, ci32(Ctx, 0));
+  return B.CreateSelect(IsZero, ci32(Ctx, 1), Shift);
+}
+
 Constant *vectorConstant(LLVMContext &Ctx, ArrayRef<uint32_t> Values,
                          bool ShiftAmounts = false) {
   SmallVector<Constant *, 4> Constants;
@@ -690,6 +708,8 @@ Value *emitRotate(IRBuilder<> &B, Module &M, Value *V, const Op &O,
   LLVMContext &Ctx = B.getContext();
   Type *I32 = Type::getInt32Ty(Ctx);
   Value *Shift = B.CreateAnd(B.CreateXor(V, ci32(Ctx, u32(O.B))), ci32(Ctx, 31));
+  if (ID == Intrinsic::fshl)
+    Shift = suppressM015FshlZeroShift(B, Shift);
   return B.CreateCall(Intrinsic::getOrInsertDeclaration(&M, ID, {I32}),
                       {V, ci32(Ctx, u32(O.A)), Shift});
 }
@@ -810,7 +830,8 @@ Value *emitOp(IRBuilder<> &B, Module &M, Value *V, Value *Idx, const Op &O) {
   case 29:
     return B.CreateCall(Intrinsic::getOrInsertDeclaration(&M, Intrinsic::fshl, {I32}),
                         {V, ci32(Ctx, u32(O.A)),
-                         ci32(Ctx, static_cast<uint32_t>(O.B & 31u))});
+                         suppressM015FshlZeroShift(
+                             B, ci32(Ctx, static_cast<uint32_t>(O.B & 31u)))});
   case 30:
     return B.CreateCall(Intrinsic::getOrInsertDeclaration(&M, Intrinsic::fshr, {I32}),
                         {ci32(Ctx, u32(O.A)), V,
@@ -844,6 +865,7 @@ Value *emitOp(IRBuilder<> &B, Module &M, Value *V, Value *Idx, const Op &O) {
                         {V, ConstantInt::getFalse(Ctx)});
   case 42: {
     Value *Shift = B.CreateAnd(V, ci32(Ctx, 31));
+    Shift = suppressM015FshlZeroShift(B, Shift);
     return B.CreateCall(Intrinsic::getOrInsertDeclaration(&M, Intrinsic::fshl, {I32}),
                         {V, ci32(Ctx, u32(O.A)), Shift});
   }
 
@@ -0,0 +1,52 @@
+# m015: scalar `fshl` by zero returns zero at `-O0`
+
+## Reproducer
+
+```bash
+amdgpu/known-miscompiles/run_ll_reproducer.sh \
+  amdgpu/known-miscompiles/m015-scalar-fshl-zero/reduced.ll
+```
+
+With the instrumented LLVM build at `amdgpu/build/llvm-fuzzer`, the reduced
+testcase produces:
+
+```text
+input=0x00000003
+O0=0x00000000
+O2=0x00000003
+mismatch=true
+```
+
+ROCm 7.1.1 does not reproduce this mismatch; both optimization levels return
+`0x00000003`.
+
+## Root Cause Notes
+
+The original fuzzer finding was
+`amdgpu/findings/cxx-diff-1778937697-1007403`. The first divergent value was an
+`llvm.fshl.i32` with a constant zero shift amount. At `-O2`, the operation is
+simplified to the left input, which is the defined result for
+`llvm.fshl.i32(x, y, 0)`.
+
+At `-O0`, AMDGPU scalarizes the left input into SGPRs and lowers the zero-count
+`fshl` through a 64-bit shift sequence. The generated scalar sequence computes a
+second shift count of `-1`:
+
+```asm
+s_lshr_b32 s4, s6, 1
+s_mov_b32 s0, 0x5040305
+s_mov_b32 s1, s6
+s_lshr_b64 s[0:1], s[0:1], 1
+s_mov_b32 s1, s4
+s_mov_b32 s4, -1
+s_lshr_b64 s[0:1], s[0:1], s4
+```
+
+That final `s_lshr_b64` by `-1` zeros the value in this reproducer. A direct
+VGPR-source `fshl(load, const, 0)` matches, and `fshr(const, scalar, 0)` also
+matches, so the suppression is limited to generated `fshl` zero-count shapes.
+
+## Fuzzer Suppression
+
+The directed C++ fuzzer avoids generating zero-count `llvm.fshl.i32` by default.
+Set `FUZZX_ALLOW_M015_SCALAR_FSHL_ZERO=1` to re-enable this bug class.
@@ -0,0 +1,33 @@
+; RUN-INPUTS: 3
+; RUN-LLVM-BUILD: build/llvm-fuzzer
+target triple = "amdgcn-amd-amdhsa"
+
+define protected amdgpu_kernel void @fuzz_kernel(ptr addrspace(1) %in, ptr addrspace(1) %out, i32 %n) #0 {
+entry:
+  %wg = call i32 @llvm.amdgcn.workgroup.id.x()
+  %wi = call i32 @llvm.amdgcn.workitem.id.x()
+  %base = mul i32 %wg, 256
+  %idx32 = add i32 %base, %wi
+  %active = icmp ult i32 %idx32, %n
+  br i1 %active, label %body, label %exit
+
+body:
+  %idx = zext i32 %idx32 to i64
+  %inptr = getelementptr i32, ptr addrspace(1) %in, i64 %idx
+  %loaded = load i32, ptr addrspace(1) %inptr, align 4
+  %scalar = call i32 @llvm.amdgcn.readfirstlane(i32 %loaded)
+  %result = call i32 @llvm.fshl.i32(i32 %scalar, i32 84148997, i32 0)
+  %outptr = getelementptr i32, ptr addrspace(1) %out, i64 %idx
+  store i32 %result, ptr addrspace(1) %outptr, align 4
+  br label %exit
+
+exit:
+  ret void
+}
+
+declare noundef i32 @llvm.amdgcn.workgroup.id.x()
+declare noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x()
+declare i32 @llvm.amdgcn.readfirstlane(i32)
+declare i32 @llvm.fshl.i32(i32, i32, i32)
+
+attributes #0 = { convergent nounwind "amdgpu-flat-work-group-size"="1,256" "target-cpu"="gfx950" "uniform-work-group-size"="true" }