Skip to content

Commit 047a926

Browse files
committed
JuliaFormatter v1 instead of v2
1 parent dff4f65 commit 047a926

File tree

2 files changed

+3
-3
lines changed

2 files changed

+3
-3
lines changed

src/Electrical/Analog/ideal_components.jl

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -440,7 +440,7 @@ G will therefore be 0 when the input is false [0] and G_on when the input is tru
440440

441441
@equations begin
442442
state ~ input.u
443-
G ~ state*Gon
444-
i ~ G*v
443+
G ~ state * Gon
444+
i ~ G * v
445445
end
446446
end

test/Electrical/analog.jl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -413,7 +413,7 @@ end
413413

414414
# Tests
415415
@test all(diode_current .>= -1e-3)
416-
@test capacitor_voltage[end] .≈ 8.26 rtol=3e-1
416+
@test capacitor_voltage[end].8.26 rtol=3e-1
417417

418418
# For visual inspection
419419
# plt = plot(sol; idxs = [diode.i, resistor.i, capacitor.v],

0 commit comments

Comments
 (0)