From e6c048da0a04fd0ee3a5521758e198c73c0afb03 Mon Sep 17 00:00:00 2001 From: Will Stuckey Date: Sun, 2 Feb 2020 12:46:22 -0500 Subject: [PATCH 01/10] initial commit --- fpga_new/.gitignore | 86 ++++++++ .../rc_ports/rc_ports.cache/wt/webtalk_pa.xml | 53 +++++ .../rc_ports.srcs/sources_1/new/AsyncFIFO.v | 26 +++ fpga_new/rc_ports/rc_ports.xpr | 203 ++++++++++++++++++ 4 files changed, 368 insertions(+) create mode 100644 fpga_new/.gitignore create mode 100644 fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml create mode 100644 fpga_new/rc_ports/rc_ports.srcs/sources_1/new/AsyncFIFO.v create mode 100644 fpga_new/rc_ports/rc_ports.xpr diff --git a/fpga_new/.gitignore b/fpga_new/.gitignore new file mode 100644 index 000000000..7134ebea7 --- /dev/null +++ b/fpga_new/.gitignore @@ -0,0 +1,86 @@ +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######################################################################################################### +######### +#Exclude all +######### +* +!*/ +!.gitignore +########################################################################### +## VIVADO +########################################################################### +######### +#Source files: +######### +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.bd +!*.edif +######### +#IP files +######### +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +######### +#System Generator +######### +!*.mdl +!*.slx +!*.bxml +######### +#Simulation logic analyzer +######### +!*.wcfg +!*.coe +######### +#MIG +######### +!*.prj +!*.mem +######### +#Project files +######### +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +######### +#Constraint files +######### +#Do NOT ignore *.xdc files +!*.xdc +######### +#TCL - files +######### +!*.tcl +######### +#Journal - files +######### +!*.jou +######### +#Reports +######### +!*.rpt +!*.txt +!*.vdi +######### +#C-files +######### +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp diff --git a/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml b/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml new file mode 100644 index 000000000..a6535de2d --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml @@ -0,0 +1,53 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/AsyncFIFO.v b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/AsyncFIFO.v new file mode 100644 index 000000000..67b83e31c --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/AsyncFIFO.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/02/2020 12:08:15 AM +// Design Name: +// Module Name: AsyncFIFO +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module AsyncFIFO( + + ); +endmodule diff --git a/fpga_new/rc_ports/rc_ports.xpr b/fpga_new/rc_ports/rc_ports.xpr new file mode 100644 index 000000000..64ce0694c --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.xpr @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + From 48ed80e2c10b7738be09ee24d0eff71a2726ae55 Mon Sep 17 00:00:00 2001 From: Will Stuckey Date: Sun, 2 Feb 2020 12:49:13 -0500 Subject: [PATCH 02/10] added FF sync impl and SPI templates --- fpga_new/.gitignore | 1 + .../rc_ports.srcs/sources_1/new/FfSync.sv | 72 +++++++++++++++++++ .../rc_ports.srcs/sources_1/new/SpiMaster.sv | 26 +++++++ .../rc_ports.srcs/sources_1/new/SpiSlave.sv | 26 +++++++ 4 files changed, 125 insertions(+) create mode 100644 fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FfSync.sv create mode 100644 fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiMaster.sv create mode 100644 fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiSlave.sv diff --git a/fpga_new/.gitignore b/fpga_new/.gitignore index 7134ebea7..be6e818d7 100644 --- a/fpga_new/.gitignore +++ b/fpga_new/.gitignore @@ -17,6 +17,7 @@ #Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. !*.vhd !*.v +!*.sv !*.bd !*.edif ######### diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FfSync.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FfSync.sv new file mode 100644 index 000000000..8387a72e7 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FfSync.sv @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Will Stuckey +// +// Create Date: 02/02/2020 12:08:15 AM +// Design Name: Flip-Flop Synchronizer +// Module Name: FfSync +// Project Name: RoboCup +// Target Devices: Artix 7 Family +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: none +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`ifndef DEFAULT_SYNC_WIDTH + `define DEFAULT_SYNC_WIDTH 1 +`endif + +`ifndef DEFAULT_SYNC_DEPTH + `define DEFAULT_SYNC_DEPTH 2 +`endif + +module FfSync #( + parameter SYNC_WIDTH=`DEFAULT_SYNC_WIDTH, + parameter SYNC_DEPTH=`DEFAULT_SYNC_DEPTH + )( + input [SYNC_WIDTH-1:0] d_in, clk, rst_n, + output [SYNC_WIDTH-1:0] d_out + ); + + // ffsync buf, use unpacked array for dyn gen, apply directive to prevent SRL inference + (* srl_style = "register" *) + reg [SYNC_WIDTH-1:0] sync_buf [SYNC_DEPTH-1:0]; + + // initial sync stage and reset + always_ff @(posedge clk or negedge rst_n) + begin : FIRST_SYNC_STAGE + if (rst_n == 0) begin + sync_buf[0] <= 0; + end + else begin + sync_buf[0] <= d_in; + end + end + + // dynamically generate sync chain + genvar ff_depth_index; + for (ff_depth_index = 1; ff_depth_index < SYNC_DEPTH; ff_depth_index++) + begin: SYNC_CHAIN_GEN + if (SYNC_DEPTH < 2) + begin: E_INVAL_DEPTH + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. SYNC_DEPTH must be >= 2.", SYNC_DEPTH); + end + else begin + always_ff @(posedge clk) + begin: SYNC_CHAIN_ELEMENT + sync_buf[ff_depth_index] <= sync_buf[ff_depth_index-1]; + end + end + end + + // output + assign d_out = sync_buf[SYNC_DEPTH-1]; + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiMaster.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiMaster.sv new file mode 100644 index 000000000..3295f02c3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiMaster.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/02/2020 12:08:15 AM +// Design Name: +// Module Name: SpiMaster +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SpiMaster( + + ); +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiSlave.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiSlave.sv new file mode 100644 index 000000000..7e6b54986 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiSlave.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/02/2020 12:08:15 AM +// Design Name: +// Module Name: SpiSlave +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SpiSlave( + + ); +endmodule From 24e331ccaa989fd6a4c5c8493b67769e661c33f8 Mon Sep 17 00:00:00 2001 From: Will Stuckey Date: Thu, 6 Feb 2020 10:37:53 -0500 Subject: [PATCH 03/10] boiler plate for gray code pointer FIFO submod --- .../rc_ports/rc_ports.cache/wt/webtalk_pa.xml | 31 ++++++----- .../rc_ports.srcs/sources_1/new/FifoGcp.sv | 54 +++++++++++++++++++ fpga_new/rc_ports/rc_ports.xpr | 33 ++++++++---- 3 files changed, 93 insertions(+), 25 deletions(-) create mode 100644 fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoGcp.sv diff --git a/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml b/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml index a6535de2d..7373035bc 100644 --- a/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml +++ b/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,36 +17,39 @@ This means code written to parse this file will need to be revisited each subseq - + + - + - - - - + + + + - + - + + - - + + - + + - + - +
diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoGcp.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoGcp.sv new file mode 100644 index 000000000..f0cbed77b --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoGcp.sv @@ -0,0 +1,54 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: William Stuckey +// +// Create Date: 02/06/2020 09:55:39 AM +// Design Name: FIFO Gray Code Pointer +// Module Name: FifoGcp +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: none +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FifoGcp #( + parameter SUPPORTED_DEPTH = 0, + localparam BIN_ADDR_WIDTH = $clog2(SUPPORTED_DEPTH), + localparam BIN_ADDR_MSB = BIN_ADDR_WIDTH - 1, + localparam GC_PTR_WIDTH = BIN_ADDR_WIDTH + 1, + localparam GC_PTR_MSB = GC_PTR_WIDTH - 1 + )( + input clk, + input rst_n, + input inc, + + output logic [BIN_ADDR_MSB:0] bin_ptr, + output logic [GC_PTR_MSB:0] gc_ptr + ); + + generate + if (SUPPORTED_DEPTH <= 0) + begin: DEPTH_NOT_SET_ELABORATION_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. SUPPORTED_DEPTH must be > 0.", SUPPORTED_DEPTH); + end + endgenerate + + generate + if ((SUPPORTED_DEPTH & (SUPPORTED_DEPTH - 1)) != 0) + begin: DEPTH_NOT_POW2_ELABORATION_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. SUPPORTED_DEPTH must be a power of 2.", SUPPORTED_DEPTH); + end + endgenerate + + + +endmodule: FifoGcp diff --git a/fpga_new/rc_ports/rc_ports.xpr b/fpga_new/rc_ports/rc_ports.xpr index 64ce0694c..0fe2f7f37 100644 --- a/fpga_new/rc_ports/rc_ports.xpr +++ b/fpga_new/rc_ports/rc_ports.xpr @@ -1,9 +1,9 @@ - + - +