diff --git a/fpga_new/.gitignore b/fpga_new/.gitignore new file mode 100644 index 000000000..13d6c1234 --- /dev/null +++ b/fpga_new/.gitignore @@ -0,0 +1,92 @@ +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######################################################################################################### +######### +#Exclude all +######### +* +!*/ +!.gitignore +########################################################################### +## VIVADO +########################################################################### +######### +#Source files: +######### +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.sv +!*.bd +!*.edif +######### +#IP files +######### +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +######### +#System Generator +######### +!*.mdl +!*.slx +!*.bxml +######### +#Simulation logic analyzer +######### +!*.wcfg +!*.coe +######### +#MIG +######### +!*.prj +!*.mem +######### +#Project files +######### +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +######### +#Constraint files +######### +#Do NOT ignore *.xdc files +!*.xdc +######### +#TCL - files +######### +!*.tcl +######### +#Journal - files +######### +!*.jou +######### +#Reports +######### +!*.rpt +!*.txt +!*.vdi +######### +#C-files +######### +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp +######### +#Other files +######### +!*.run +!*.job \ No newline at end of file diff --git a/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml b/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml new file mode 100644 index 000000000..3efe6b11d --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.cache/wt/webtalk_pa.xml @@ -0,0 +1,133 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/fpga_new/rc_ports/rc_ports.ip_user_files/README.txt b/fpga_new/rc_ports/rc_ports.ip_user_files/README.txt new file mode 100644 index 000000000..023052cab --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_1.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_1.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_10.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_10.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_11.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_11.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_12.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_12.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_13.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_13.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_14.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_14.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_15.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_15.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_16.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_16.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_17.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_17.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_18.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_18.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_19.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_19.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_2.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_2.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_20.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_20.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_21.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_21.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_22.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_22.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_23.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_23.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_24.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_24.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_25.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_25.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_25.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_26.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_26.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_26.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_27.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_27.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_27.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_28.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_28.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_28.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_29.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_29.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_3.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_3.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_30.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_30.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_31.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_31.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_32.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_32.xml new file mode 100644 index 000000000..761f290d7 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_33.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_33.xml new file mode 100644 index 000000000..761f290d7 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_34.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_34.xml new file mode 100644 index 000000000..761f290d7 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_4.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_4.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_5.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_5.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_6.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_6.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_7.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_7.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_8.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_8.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_9.xml b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_9.xml new file mode 100644 index 000000000..64a4ddcc3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.tcl b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.tcl new file mode 100644 index 000000000..40332222d --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.tcl @@ -0,0 +1,167 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 2 + create_project -in_memory -part xc7a50tcsg324-3 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.cache/wt [current_project] + set_property parent.project_path C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.xpr [current_project] + set_property ip_output_repo C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.dcp + link_design -top FixedMult -part xc7a50tcsg324-3 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force FixedMult_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file FixedMult_drc_opted.rpt -pb FixedMult_drc_opted.pb -rpx FixedMult_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force FixedMult_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file FixedMult_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file FixedMult_utilization_placed.rpt -pb FixedMult_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file FixedMult_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force FixedMult_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force FixedMult_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file FixedMult_drc_routed.rpt -pb FixedMult_drc_routed.pb -rpx FixedMult_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file FixedMult_methodology_drc_routed.rpt -pb FixedMult_methodology_drc_routed.pb -rpx FixedMult_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file FixedMult_power_routed.rpt -pb FixedMult_power_summary_routed.pb -rpx FixedMult_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file FixedMult_route_status.rpt -pb FixedMult_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file FixedMult_timing_summary_routed.rpt -pb FixedMult_timing_summary_routed.pb -rpx FixedMult_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file FixedMult_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file FixedMult_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file FixedMult_bus_skew_routed.rpt -pb FixedMult_bus_skew_routed.pb -rpx FixedMult_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force FixedMult_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.vdi b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.vdi new file mode 100644 index 000000000..0424a909f --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.vdi @@ -0,0 +1,493 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Feb 18 13:59:06 2020 +# Process ID: 2660 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1 +# Command line: vivado.exe -log FixedMult.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FixedMult.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.vdi +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source FixedMult.tcl -notrace +Command: link_design -top FixedMult -part xc7a50tcsg324-3 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a50tcsg324-3 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 544.418 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 32 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 623.141 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 623.141 ; gain = 322.992 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.932 . Memory (MB): peak = 673.816 ; gain = 50.602 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 911fd973 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1159.488 ; gain = 485.672 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 911fd973 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1352.203 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: d4885a71 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 1352.203 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 7f529cef + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.101 . Memory (MB): peak = 1352.203 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 7f529cef + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1352.203 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 7f529cef + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.129 . Memory (MB): peak = 1352.203 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 7f529cef + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.132 . Memory (MB): peak = 1352.203 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1352.203 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 11454bf66 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.151 . Memory (MB): peak = 1352.203 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 11454bf66 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1352.203 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 11454bf66 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1352.203 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1352.203 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 11454bf66 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1352.203 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1352.203 ; gain = 729.063 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1352.203 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file FixedMult_drc_opted.rpt -pb FixedMult_drc_opted.pb -rpx FixedMult_drc_opted.rpx +Command: report_drc -file FixedMult_drc_opted.rpt -pb FixedMult_drc_opted.pb -rpx FixedMult_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1353.867 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 512d0151 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1353.867 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1353.867 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1307b772d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.912 . Memory (MB): peak = 1363.105 ; gain = 9.238 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 14075649b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.986 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 14075649b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.988 . Memory (MB): peak = 1370.168 ; gain = 16.301 +Phase 1 Placer Initialization | Checksum: 14075649b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 14075649b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.994 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: c572f008 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 +Phase 2 Global Placement | Checksum: c572f008 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: c572f008 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 9b683471 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 163063de4 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 163063de4 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 +Phase 3 Detail Placement | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1370.168 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 176d1a58d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 +Ending Placer Task | Checksum: fb7e9310 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1370.168 ; gain = 16.301 +INFO: [Common 17-83] Releasing license: Implementation +43 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1370.168 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.157 . Memory (MB): peak = 1385.043 ; gain = 14.875 +INFO: [Common 17-1381] The checkpoint 'C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file FixedMult_io_placed.rpt +report_io: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.100 . Memory (MB): peak = 1385.043 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file FixedMult_utilization_placed.rpt -pb FixedMult_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file FixedMult_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1385.043 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +50 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1385.043 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1389.285 ; gain = 4.242 +INFO: [Common 17-1381] The checkpoint 'C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: aa5191bf ConstDB: 0 ShapeSum: 512d0151 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1172c08d9 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1484.582 ; gain = 81.270 +Post Restoration Checksum: NetGraph: b5f0b853 NumContArr: 613b5086 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1172c08d9 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1490.563 ; gain = 87.250 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1172c08d9 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1490.563 ; gain = 87.250 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 137dbaa05 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1492.453 ; gain = 89.141 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 459 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 459 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: e87ebcbd + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1494.648 ; gain = 91.336 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: c8b877ca + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1494.648 ; gain = 91.336 +Phase 4 Rip-up And Reroute | Checksum: c8b877ca + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1494.648 ; gain = 91.336 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: c8b877ca + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1494.648 ; gain = 91.336 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: c8b877ca + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1494.648 ; gain = 91.336 +Phase 6 Post Hold Fix | Checksum: c8b877ca + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1494.648 ; gain = 91.336 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.205453 % + Global Horizontal Routing Utilization = 0.233863 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 33.3333%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 33.3333%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: c8b877ca + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1494.648 ; gain = 91.336 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: c8b877ca + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.656 ; gain = 93.344 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e2eff4fb + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.656 ; gain = 93.344 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.656 ; gain = 93.344 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +59 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.656 ; gain = 107.371 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1496.656 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1506.516 ; gain = 9.859 +INFO: [Common 17-1381] The checkpoint 'C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file FixedMult_drc_routed.rpt -pb FixedMult_drc_routed.pb -rpx FixedMult_drc_routed.rpx +Command: report_drc -file FixedMult_drc_routed.rpt -pb FixedMult_drc_routed.pb -rpx FixedMult_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file FixedMult_methodology_drc_routed.rpt -pb FixedMult_methodology_drc_routed.pb -rpx FixedMult_methodology_drc_routed.rpx +Command: report_methodology -file FixedMult_methodology_drc_routed.rpt -pb FixedMult_methodology_drc_routed.pb -rpx FixedMult_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file FixedMult_power_routed.rpt -pb FixedMult_power_summary_routed.pb -rpx FixedMult_power_routed.rpx +Command: report_power -file FixedMult_power_routed.rpt -pb FixedMult_power_summary_routed.pb -rpx FixedMult_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file FixedMult_route_status.rpt -pb FixedMult_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file FixedMult_timing_summary_routed.rpt -pb FixedMult_timing_summary_routed.pb -rpx FixedMult_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file FixedMult_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file FixedMult_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FixedMult_bus_skew_routed.rpt -pb FixedMult_bus_skew_routed.pb -rpx FixedMult_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -3, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Tue Feb 18 14:00:04 2020... diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_bus_skew_routed.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_bus_skew_routed.pb new file mode 100644 index 000000000..3390588d5 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_bus_skew_routed.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_bus_skew_routed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_bus_skew_routed.rpt new file mode 100644 index 000000000..958347a00 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 14:00:04 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file FixedMult_bus_skew_routed.rpt -pb FixedMult_bus_skew_routed.pb -rpx FixedMult_bus_skew_routed.rpx +| Design : FixedMult +| Device : 7a50t-csg324 +| Speed File : -3 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_clock_utilization_routed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_clock_utilization_routed.rpt new file mode 100644 index 000000000..095f82130 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_clock_utilization_routed.rpt @@ -0,0 +1,93 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 14:00:04 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_clock_utilization -file FixedMult_clock_utilization_routed.rpt +| Design : FixedMult +| Device : 7a50t-csg324 +| Speed File : -3 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_control_sets_placed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_control_sets_placed.rpt new file mode 100644 index 000000000..cf580f3bc --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_control_sets_placed.rpt @@ -0,0 +1,77 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 13:59:36 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file FixedMult_control_sets_placed.rpt +| Design : FixedMult +| Device : xc7a50t +-------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 0 | +| Minimum number of control sets | 0 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 0 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_opted.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_opted.pb new file mode 100644 index 000000000..a6bfab595 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_opted.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_opted.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_opted.rpt new file mode 100644 index 000000000..808e1adbc --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_opted.rpt @@ -0,0 +1,144 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 13:59:32 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_drc -file FixedMult_drc_opted.rpt -pb FixedMult_drc_opted.pb -rpx FixedMult_drc_opted.rpx +| Design : FixedMult +| Device : xc7a50tcsg324-3 +| Speed File : -3 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 19 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| DPIP-1 | Warning | Input pipelining | 8 | +| DPOP-1 | Warning | PREG Output pipelining | 4 | +| DPOP-2 | Warning | MREG Output pipelining | 4 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +97 out of 97 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: x[31:0], y[31:0], z[31:0], overflow. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +97 out of 97 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: x[31:0], y[31:0], z[31:0], overflow. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +DPIP-1#1 Warning +Input pipelining +DSP result0 input result0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP result0 input result0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP result0__0 input result0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP result0__0 input result0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP result0__1 input result0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP result0__1 input result0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP result0__2 input result0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP result0__2 input result0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP result0 output result0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP result0__0 output result0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP result0__1 output result0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP result0__2 output result0__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP result0 multiplier stage result0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP result0__0 multiplier stage result0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP result0__1 multiplier stage result0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP result0__2 multiplier stage result0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_routed.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_routed.pb new file mode 100644 index 000000000..a6bfab595 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_routed.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_routed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_routed.rpt new file mode 100644 index 000000000..76dd5d547 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_drc_routed.rpt @@ -0,0 +1,144 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 14:00:01 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_drc -file FixedMult_drc_routed.rpt -pb FixedMult_drc_routed.pb -rpx FixedMult_drc_routed.rpx +| Design : FixedMult +| Device : xc7a50tcsg324-3 +| Speed File : -3 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 19 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| DPIP-1 | Warning | Input pipelining | 8 | +| DPOP-1 | Warning | PREG Output pipelining | 4 | +| DPOP-2 | Warning | MREG Output pipelining | 4 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +97 out of 97 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: x[31:0], y[31:0], z[31:0], overflow. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +97 out of 97 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: x[31:0], y[31:0], z[31:0], overflow. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +DPIP-1#1 Warning +Input pipelining +DSP result0 input result0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP result0 input result0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP result0__0 input result0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP result0__0 input result0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP result0__1 input result0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP result0__1 input result0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP result0__2 input result0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP result0__2 input result0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP result0 output result0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP result0__0 output result0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP result0__1 output result0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP result0__2 output result0__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP result0 multiplier stage result0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP result0__0 multiplier stage result0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP result0__1 multiplier stage result0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP result0__2 multiplier stage result0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_io_placed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_io_placed.rpt new file mode 100644 index 000000000..f7ecddb4c --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 13:59:36 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_io -file FixedMult_io_placed.rpt +| Design : FixedMult +| Device : xc7a50t +| Speed File : -3 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 97 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | x[31] | High Range | IO_L9N_T1_DQS_AD3N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| A18 | x[29] | High Range | IO_L10N_T1_AD11N_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | x[30] | High Range | IO_L10P_T1_AD11P_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | x[25] | High Range | IO_L12N_T1_MRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C16 | x[10] | High Range | IO_L20P_T3_A20_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C17 | x[9] | High Range | IO_L20N_T3_A19_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | x[26] | High Range | IO_L12P_T1_MRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| D17 | x[17] | High Range | IO_L16N_T2_A27_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| D18 | x[7] | High Range | IO_L21N_T3_DQS_A18_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | x[28] | High Range | IO_L11P_T1_SRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E16 | x[27] | High Range | IO_L11N_T1_SRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E17 | x[18] | High Range | IO_L16P_T2_A28_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| E18 | x[8] | High Range | IO_L21P_T3_DQS_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | x[22] | High Range | IO_L14P_T2_SRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F16 | x[21] | High Range | IO_L14N_T2_SRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | x[5] | High Range | IO_L22N_T3_A16_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | x[19] | High Range | IO_L15N_T2_DQS_ADV_B_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| G16 | x[23] | High Range | IO_L13N_T2_MRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G17 | x[13] | High Range | IO_L18N_T2_A23_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| G18 | x[6] | High Range | IO_L22P_T3_A17_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | x[20] | High Range | IO_L15P_T2_DQS_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H15 | x[11] | High Range | IO_L19N_T3_A21_VREF_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H16 | x[24] | High Range | IO_L13P_T2_MRCC_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H17 | x[14] | High Range | IO_L18P_T2_A24_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | x[15] | High Range | IO_L17N_T2_A25_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J14 | x[12] | High Range | IO_L19P_T3_A22_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J15 | x[1] | High Range | IO_L24N_T3_RS0_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | x[4] | High Range | IO_L23P_T3_FOE_B_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| J18 | x[3] | High Range | IO_L23N_T3_FWE_B_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | x[16] | High Range | IO_L17P_T2_A26_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 1.80 | | | | | | | | | +| K15 | x[2] | High Range | IO_L24P_T3_RS1_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K16 | x[0] | High Range | IO_25_15 | INPUT | LVCMOS18* | 15 | | | | NONE | | UNFIXED | | | | NONE | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | y[18] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | y[14] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | z[30] | High Range | IO_L10P_T1_D14_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| M17 | z[29] | High Range | IO_L10N_T1_D15_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| N4 | y[17] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N5 | y[24] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N6 | y[13] | High Range | IO_L18N_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | z[28] | High Range | IO_L11P_T1_SRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| N16 | z[27] | High Range | IO_L11N_T1_SRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| N17 | overflow | High Range | IO_L9P_T1_DQS_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | y[20] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| P3 | y[21] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| P4 | y[22] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| P5 | y[23] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | z[24] | High Range | IO_L13P_T2_MRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| P17 | z[26] | High Range | IO_L12P_T1_MRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| P18 | z[31] | High Range | IO_L9N_T1_DQS_D13_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R1 | y[16] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R2 | y[19] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R3 | y[28] | High Range | IO_L11P_T1_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | y[11] | High Range | IO_L19N_T3_VREF_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R6 | y[12] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R7 | y[4] | High Range | IO_L23P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R8 | y[2] | High Range | IO_L24P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | z[0] | High Range | IO_25_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | z[23] | High Range | IO_L13N_T2_MRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R16 | z[20] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R17 | z[25] | High Range | IO_L12N_T1_MRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | y[15] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| T3 | y[27] | High Range | IO_L11N_T1_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T4 | y[25] | High Range | IO_L12N_T1_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T5 | y[26] | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T6 | y[3] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | y[1] | High Range | IO_L24N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T9 | z[2] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T10 | z[1] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T11 | z[12] | High Range | IO_L19P_T3_A10_D26_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| T13 | z[4] | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T14 | z[22] | High Range | IO_L14P_T2_SRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T15 | z[21] | High Range | IO_L14N_T2_SRCC_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T16 | z[19] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| U6 | y[5] | High Range | IO_L22N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U7 | y[6] | High Range | IO_L22P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U8 | y[0] | High Range | IO_25_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U9 | y[8] | High Range | IO_L21P_T3_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | z[11] | High Range | IO_L19N_T3_A09_D25_VREF_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U12 | z[10] | High Range | IO_L20P_T3_A08_D24_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U13 | z[3] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U14 | z[6] | High Range | IO_L22P_T3_A05_D21_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| U16 | z[14] | High Range | IO_L18P_T2_A12_D28_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U17 | z[16] | High Range | IO_L17P_T2_A14_D30_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| U18 | z[15] | High Range | IO_L17N_T2_A13_D29_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | y[31] | High Range | IO_L9N_T1_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | y[29] | High Range | IO_L10N_T1_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V5 | y[30] | High Range | IO_L10P_T1_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V6 | y[9] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V7 | y[10] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | +| V9 | y[7] | High Range | IO_L21N_T3_DQS_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V10 | z[8] | High Range | IO_L21P_T3_DQS_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V11 | z[7] | High Range | IO_L21N_T3_DQS_A06_D22_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V12 | z[9] | High Range | IO_L20N_T3_A07_D23_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | z[5] | High Range | IO_L22N_T3_A04_D20_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V15 | z[18] | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V16 | z[17] | High Range | IO_L16N_T2_A15_D31_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V17 | z[13] | High Range | IO_L18N_T2_A11_D27_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_methodology_drc_routed.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_methodology_drc_routed.pb new file mode 100644 index 000000000..0d6626b7c Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_methodology_drc_routed.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_methodology_drc_routed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_methodology_drc_routed.rpt new file mode 100644 index 000000000..fc1905d76 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_methodology_drc_routed.rpt @@ -0,0 +1,55 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 14:00:03 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_methodology -file FixedMult_methodology_drc_routed.rpt -pb FixedMult_methodology_drc_routed.pb -rpx FixedMult_methodology_drc_routed.rpx +| Design : FixedMult +| Device : xc7a50tcsg324-3 +| Speed File : -3 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 4 ++----------+----------+-----------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------+------------+ +| SYNTH-10 | Warning | Wide multiplier | 4 | ++----------+----------+-----------------+------------+ + +2. REPORT DETAILS +----------------- +SYNTH-10#1 Warning +Wide multiplier +Detected multiplier at result0 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks. +Related violations: + +SYNTH-10#2 Warning +Wide multiplier +Detected multiplier at result0__0 of size 16x16, it is decomposed from a wide multipler into 4 DSP blocks. +Related violations: + +SYNTH-10#3 Warning +Wide multiplier +Detected multiplier at result0__1 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks. +Related violations: + +SYNTH-10#4 Warning +Wide multiplier +Detected multiplier at result0__2 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks. +Related violations: + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_opt.dcp b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_opt.dcp new file mode 100644 index 000000000..5d989e70c Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_opt.dcp differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_physopt.dcp b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_physopt.dcp new file mode 100644 index 000000000..457e73562 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_physopt.dcp differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_placed.dcp b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_placed.dcp new file mode 100644 index 000000000..0f94fb128 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_placed.dcp differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_power_routed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_power_routed.rpt new file mode 100644 index 000000000..e0866c99c --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_power_routed.rpt @@ -0,0 +1,143 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 14:00:03 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_power -file FixedMult_power_routed.rpt -pb FixedMult_power_summary_routed.pb -rpx FixedMult_power_routed.rpx +| Design : FixedMult +| Device : xc7a50tcsg324-3 +| Design State : routed +| Grade : extended +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+----------------------------------+ +| Total On-Chip Power (W) | 36.904 (Junction temp exceeded!) | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 36.420 | +| Device Static (W) | 0.485 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 0.0 | +| Junction Temperature (C) | 125.0 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+----------------------------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.810 | 209 | --- | --- | +| LUT as Logic | 0.693 | 176 | 32600 | 0.54 | +| CARRY4 | 0.117 | 28 | 8150 | 0.34 | +| Others | 0.000 | 4 | --- | --- | +| Signals | 2.146 | 459 | --- | --- | +| DSPs | 3.246 | 4 | 120 | 3.33 | +| I/O | 30.218 | 97 | 210 | 46.19 | +| Static Power | 0.485 | | | | +| Total | 36.904 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 6.798 | 6.458 | 0.341 | +| Vccaux | 1.800 | 2.506 | 2.453 | 0.053 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 14.194 | 14.193 | 0.001 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.010 | 0.000 | 0.010 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-----------+-----------+ +| Name | Power (W) | ++-----------+-----------+ +| FixedMult | 36.420 | ++-----------+-----------+ + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_power_summary_routed.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_power_summary_routed.pb new file mode 100644 index 000000000..7facdb412 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_power_summary_routed.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_route_status.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_route_status.pb new file mode 100644 index 000000000..c02af4d51 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_route_status.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_route_status.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_route_status.rpt new file mode 100644 index 000000000..7047ba393 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 667 : + # of nets not needing routing.......... : 206 : + # of internally routed nets........ : 206 : + # of routable nets..................... : 461 : + # of fully routed nets............. : 461 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_routed.dcp b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_routed.dcp new file mode 100644 index 000000000..1d6814751 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_routed.dcp differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_timing_summary_routed.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_timing_summary_routed.pb new file mode 100644 index 000000000..4526e931e --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_timing_summary_routed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_timing_summary_routed.rpt new file mode 100644 index 000000000..e151bc852 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_timing_summary_routed.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 14:00:04 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file FixedMult_timing_summary_routed.rpt -pb FixedMult_timing_summary_routed.pb -rpx FixedMult_timing_summary_routed.rpx -warn_on_violation +| Design : FixedMult +| Device : 7a50t-csg324 +| Speed File : -3 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_utilization_placed.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_utilization_placed.pb new file mode 100644 index 000000000..73dc111ce Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_utilization_placed.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_utilization_placed.rpt b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_utilization_placed.rpt new file mode 100644 index 000000000..cefcc4596 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult_utilization_placed.rpt @@ -0,0 +1,202 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Feb 18 13:59:36 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_utilization -file FixedMult_utilization_placed.rpt -pb FixedMult_utilization_placed.pb +| Design : FixedMult +| Device : 7a50tcsg324-3 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 176 | 0 | 32600 | 0.54 | +| LUT as Logic | 176 | 0 | 32600 | 0.54 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 65200 | 0.00 | +| Register as Flip Flop | 0 | 0 | 65200 | 0.00 | +| Register as Latch | 0 | 0 | 65200 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 49 | 0 | 8150 | 0.60 | +| SLICEL | 35 | 0 | | | +| SLICEM | 14 | 0 | | | +| LUT as Logic | 176 | 0 | 32600 | 0.54 | +| using O5 output only | 0 | | | | +| using O6 output only | 175 | | | | +| using O5 and O6 | 1 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 0 | 0 | 65200 | 0.00 | +| Register driven from within the Slice | 0 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 0 | | 8150 | 0.00 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 75 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 75 | 0.00 | +| RAMB18 | 0 | 0 | 150 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| DSPs | 4 | 0 | 120 | 3.33 | +| DSP48E1 only | 4 | | | | ++----------------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 97 | 0 | 210 | 46.19 | +| IOB Master Pads | 46 | | | | +| IOB Slave Pads | 48 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT1 | 64 | LUT | +| IBUF | 64 | IO | +| LUT3 | 61 | LUT | +| LUT2 | 49 | LUT | +| OBUF | 33 | IO | +| CARRY4 | 28 | CarryLogic | +| DSP48E1 | 4 | Block Arithmetic | +| LUT6 | 3 | LUT | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/gen_run.xml b/fpga_new/rc_ports/rc_ports.runs/impl_1/gen_run.xml new file mode 100644 index 000000000..ff0cea36b --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/gen_run.xml @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/htr.txt b/fpga_new/rc_ports/rc_ports.runs/impl_1/htr.txt new file mode 100644 index 000000000..2d02fcb75 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log FixedMult.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source FixedMult.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/init_design.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/init_design.pb new file mode 100644 index 000000000..701218c23 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/init_design.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/opt_design.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/opt_design.pb new file mode 100644 index 000000000..62c3e9919 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/opt_design.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/phys_opt_design.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/phys_opt_design.pb new file mode 100644 index 000000000..d476d85f3 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/phys_opt_design.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/place_design.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/place_design.pb new file mode 100644 index 000000000..535c804ab Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/place_design.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/route_design.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/route_design.pb new file mode 100644 index 000000000..fb65467a3 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/route_design.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/vivado.jou b/fpga_new/rc_ports/rc_ports.runs/impl_1/vivado.jou new file mode 100644 index 000000000..0c0aa6531 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Feb 18 13:59:06 2020 +# Process ID: 2660 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1 +# Command line: vivado.exe -log FixedMult.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FixedMult.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1/FixedMult.vdi +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source FixedMult.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.runs/impl_1/vivado.pb b/fpga_new/rc_ports/rc_ports.runs/impl_1/vivado.pb new file mode 100644 index 000000000..ee16d5be0 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/impl_1/vivado.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.dcp b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.dcp new file mode 100644 index 000000000..e558defa7 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.dcp differ diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.tcl b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.tcl new file mode 100644 index 000000000..28b17fb8b --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.tcl @@ -0,0 +1,51 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7a50tcsg324-3 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.cache/wt [current_project] +set_property parent.project_path C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo c:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib -sv C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top FixedMult -part xc7a50tcsg324-3 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef FixedMult.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file FixedMult_utilization_synth.rpt -pb FixedMult_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.vds b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.vds new file mode 100644 index 000000000..c724b3c0f --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.vds @@ -0,0 +1,274 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Feb 17 20:12:36 2020 +# Process ID: 19596 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1 +# Command line: vivado.exe -log FixedMult.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FixedMult.tcl +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.vds +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source FixedMult.tcl -notrace +Command: synth_design -top FixedMult -part xc7a50tcsg324-3 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2600 +WARNING: [Synth 8-1921] elaboration system task fatal violates IEEE 1800 syntax [C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv:38] +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 517.480 ; gain = 217.750 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'FixedMult' [C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv:23] + Parameter DATA_WIDTH bound to: 32 - type: integer + Parameter RADIX bound to: 15 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'FixedMult' (1#1) [C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv:23] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 563.969 ; gain = 264.238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 563.969 ; gain = 264.238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a50tcsg324-3 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 563.969 ; gain = 264.238 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a50tcsg324-3 +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 563.969 ; gain = 264.238 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 2 ++---Multipliers : + 32x32 Multipliers := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module FixedMult +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 2 ++---Multipliers : + 32x32 Multipliers := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 120 (col length:60) +BRAMs: 150 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 4 [C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv:45] +DSP Report: Generating DSP result0, operation Mode is: A*B. +DSP Report: operator result0 is absorbed into DSP result0. +DSP Report: operator result0 is absorbed into DSP result0. +DSP Report: Generating DSP result0, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator result0 is absorbed into DSP result0. +DSP Report: operator result0 is absorbed into DSP result0. +DSP Report: Generating DSP result0, operation Mode is: A*B. +DSP Report: operator result0 is absorbed into DSP result0. +DSP Report: operator result0 is absorbed into DSP result0. +DSP Report: Generating DSP result0, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator result0 is absorbed into DSP result0. +DSP Report: operator result0 is absorbed into DSP result0. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 733.750 ; gain = 434.020 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +DSP: Preliminary Mapping Report (see note below) ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FixedMult | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|FixedMult | (PCIN>>17)+A*B | 16 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|FixedMult | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|FixedMult | (PCIN>>17)+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | ++------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 736.574 ; gain = 436.844 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 736.574 ; gain = 436.844 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+--------+------+ +| |Cell |Count | ++------+--------+------+ +|1 |CARRY4 | 28| +|2 |DSP48E1 | 4| +|3 |LUT1 | 64| +|4 |LUT2 | 49| +|5 |LUT3 | 61| +|6 |LUT6 | 3| +|7 |IBUF | 64| +|8 |OBUF | 33| ++------+--------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 306| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 736.578 ; gain = 436.848 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 749.711 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 32 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 846.375 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +12 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 846.375 ; gain = 546.645 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 846.375 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file FixedMult_utilization_synth.rpt -pb FixedMult_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon Feb 17 20:13:01 2020... diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult_utilization_synth.pb b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult_utilization_synth.pb new file mode 100644 index 000000000..7a03d139d Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult_utilization_synth.pb differ diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult_utilization_synth.rpt b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult_utilization_synth.rpt new file mode 100644 index 000000000..4e329d561 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult_utilization_synth.rpt @@ -0,0 +1,176 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Feb 17 20:13:01 2020 +| Host : DESKTOP-8GBCOGE running 64-bit major release (build 9200) +| Command : report_utilization -file FixedMult_utilization_synth.rpt -pb FixedMult_utilization_synth.pb +| Design : FixedMult +| Device : 7a50tcsg324-3 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 177 | 0 | 32600 | 0.54 | +| LUT as Logic | 177 | 0 | 32600 | 0.54 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 65200 | 0.00 | +| Register as Flip Flop | 0 | 0 | 65200 | 0.00 | +| Register as Latch | 0 | 0 | 65200 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 75 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 75 | 0.00 | +| RAMB18 | 0 | 0 | 150 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| DSPs | 4 | 0 | 120 | 3.33 | +| DSP48E1 only | 4 | | | | ++----------------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 97 | 0 | 210 | 46.19 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT1 | 64 | LUT | +| IBUF | 64 | IO | +| LUT3 | 61 | LUT | +| LUT2 | 49 | LUT | +| OBUF | 33 | IO | +| CARRY4 | 28 | CarryLogic | +| DSP48E1 | 4 | Block Arithmetic | +| LUT6 | 3 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/gen_run.xml b/fpga_new/rc_ports/rc_ports.runs/synth_1/gen_run.xml new file mode 100644 index 000000000..36d7a4aaf --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/synth_1/gen_run.xml @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/htr.txt b/fpga_new/rc_ports/rc_ports.runs/synth_1/htr.txt new file mode 100644 index 000000000..046cc8031 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log FixedMult.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source FixedMult.tcl diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/vivado.jou b/fpga_new/rc_ports/rc_ports.runs/synth_1/vivado.jou new file mode 100644 index 000000000..e41963e02 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Feb 17 20:12:36 2020 +# Process ID: 19596 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1 +# Command line: vivado.exe -log FixedMult.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FixedMult.tcl +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1/FixedMult.vds +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source FixedMult.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.runs/synth_1/vivado.pb b/fpga_new/rc_ports/rc_ports.runs/synth_1/vivado.pb new file mode 100644 index 000000000..1e37ffeff Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.runs/synth_1/vivado.pb differ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FifoModule_tb.tcl b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FifoModule_tb.tcl new file mode 100644 index 000000000..1094e45dc --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FifoModule_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FifoModule_tb_vlog.prj b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FifoModule_tb_vlog.prj new file mode 100644 index 000000000..d007978e6 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FifoModule_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +sv xil_defaultlib \ +"../../../../rc_ports.srcs/sources_1/new/FifoModule.sv" \ +"../../../../rc_ports.srcs/sources_1/new/FifoModule_tb.sv" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedAddSub_tb.tcl b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedAddSub_tb.tcl new file mode 100644 index 000000000..1094e45dc --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedAddSub_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedAddSub_tb_vlog.prj b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedAddSub_tb_vlog.prj new file mode 100644 index 000000000..93e5a70cb --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedAddSub_tb_vlog.prj @@ -0,0 +1,11 @@ +# compile verilog/system verilog design source files +sv xil_defaultlib \ +"../../../../rc_ports.srcs/sources_1/new/FixedAdd.sv" \ +"../../../../rc_ports.srcs/sources_1/new/FixedSub.sv" \ +"../../../../rc_ports.srcs/sim_1/new/FixedAddSub_tb.sv" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedMult_tb.tcl b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedMult_tb.tcl new file mode 100644 index 000000000..1094e45dc --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedMult_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedMult_tb_vlog.prj b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedMult_tb_vlog.prj new file mode 100644 index 000000000..6e7a645ed --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/FixedMult_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +sv xil_defaultlib \ +"../../../../rc_ports.srcs/sources_1/new/FixedMult.sv" \ +"../../../../rc_ports.srcs/sim_1/new/FixedMult_tb.sv" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/glbl.v b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 000000000..be6423350 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.jou b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 000000000..8babb30a9 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Feb 18 18:46:12 2020 +# Process ID: 2276 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_10420.backup.jou b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_10420.backup.jou new file mode 100644 index 000000000..239edeb66 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_10420.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Feb 16 17:24:59 2020 +# Process ID: 10420 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_1680.backup.jou b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_1680.backup.jou new file mode 100644 index 000000000..28d88f0e4 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_1680.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Feb 17 12:36:08 2020 +# Process ID: 1680 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_17624.backup.jou b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_17624.backup.jou new file mode 100644 index 000000000..783462229 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_17624.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Feb 9 20:37:14 2020 +# Process ID: 17624 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_19948.backup.jou b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_19948.backup.jou new file mode 100644 index 000000000..c028f1854 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_19948.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Feb 16 17:15:24 2020 +# Process ID: 19948 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_9484.backup.jou b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_9484.backup.jou new file mode 100644 index 000000000..7e709b837 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk_9484.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Feb 17 16:03:55 2020 +# Process ID: 9484 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xelab.pb b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 000000000..ce255b2ee Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/Compile_Options.txt b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/Compile_Options.txt new file mode 100644 index 000000000..2f88909a9 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "78c8093eb3024dbba0dabf31fc6976ea" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "FifoModule_tb_behav" "xil_defaultlib.FifoModule_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/TempBreakPointFile.txt b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/TempBreakPointFile.txt new file mode 100644 index 000000000..fdbc612e3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/obj/xsim_1.c b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/obj/xsim_1.c new file mode 100644 index 000000000..fb74d5ea1 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/obj/xsim_1.c @@ -0,0 +1,122 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_3(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[22] = {(funcp)execute_7, (funcp)execute_8, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_3, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 22; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/FifoModule_tb_behav/xsim.reloc", (void **)funcTab, 22); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/FifoModule_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/FifoModule_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstantiate(); + +extern void implicit_HDL_SCcleanup(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/FifoModule_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/FifoModule_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/FifoModule_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 000000000..637f47921 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/xsim_webtalk.tcl b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 000000000..e4634ac0e --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,43 @@ +webtalk_init -webtalk_dir C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sun Feb 16 17:14:13 2020" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2019.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2708876" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "37a26be8-2375-4bfb-b313-30b0c73668f4" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "78c8093eb3024dbba0dabf31fc6976ea" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "11" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-10510U CPU @ 1.80GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2304 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key SystemVerilog -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "74 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "3 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "25" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.75_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "43768_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2002139768 -regid "" -xml C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/xsim.mem b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/xsim.mem new file mode 100644 index 000000000..f5adb0cde Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FifoModule_tb_behav/xsim.mem differ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/Compile_Options.txt b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/Compile_Options.txt new file mode 100644 index 000000000..5e309cbfe --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "78c8093eb3024dbba0dabf31fc6976ea" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "FixedAddSub_tb_behav" "xil_defaultlib.FixedAddSub_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/TempBreakPointFile.txt b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/TempBreakPointFile.txt new file mode 100644 index 000000000..fdbc612e3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/obj/xsim_1.c b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/obj/xsim_1.c new file mode 100644 index 000000000..54a3774d6 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/obj/xsim_1.c @@ -0,0 +1,120 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_5(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[20] = {(funcp)execute_5, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_16, (funcp)execute_17, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 20; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/FixedAddSub_tb_behav/xsim.reloc", (void **)funcTab, 20); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/FixedAddSub_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/FixedAddSub_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstantiate(); + +extern void implicit_HDL_SCcleanup(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/FixedAddSub_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/FixedAddSub_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/FixedAddSub_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 000000000..94bc1ff8e --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/xsim_webtalk.tcl b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 000000000..bf361b4eb --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Mon Feb 17 12:35:58 2020" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2019.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2708876" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "37a26be8-2375-4bfb-b313-30b0c73668f4" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "78c8093eb3024dbba0dabf31fc6976ea" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "24" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-10510U CPU @ 1.80GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2304 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "4 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6012_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2715852754 -regid "" -xml C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/xsim.mem b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/xsim.mem new file mode 100644 index 000000000..5b432b3f6 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedAddSub_tb_behav/xsim.mem differ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/Compile_Options.txt b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/Compile_Options.txt new file mode 100644 index 000000000..68eb9e637 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "78c8093eb3024dbba0dabf31fc6976ea" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "FixedMult_tb_behav" "xil_defaultlib.FixedMult_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/TempBreakPointFile.txt b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/TempBreakPointFile.txt new file mode 100644 index 000000000..fdbc612e3 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/obj/xsim_1.c b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/obj/xsim_1.c new file mode 100644 index 000000000..e5a887d11 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/obj/xsim_1.c @@ -0,0 +1,115 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_3, (funcp)execute_11, (funcp)execute_12, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/FixedMult_tb_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/FixedMult_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/FixedMult_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstantiate(); + +extern void implicit_HDL_SCcleanup(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/FixedMult_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/FixedMult_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/FixedMult_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 000000000..18f8ec7fe --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/xsim.mem b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/xsim.mem new file mode 100644 index 000000000..3519befa3 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xsim.dir/FixedMult_tb_behav/xsim.mem differ diff --git a/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xvlog.pb b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 000000000..cd1d8efb4 Binary files /dev/null and b/fpga_new/rc_ports/rc_ports.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/fpga_new/rc_ports/rc_ports.srcs/sim_1/new/FixedAddSub_tb.sv b/fpga_new/rc_ports/rc_ports.srcs/sim_1/new/FixedAddSub_tb.sv new file mode 100644 index 000000000..2d68c2699 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sim_1/new/FixedAddSub_tb.sv @@ -0,0 +1,70 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/16/2020 02:36:20 PM +// Design Name: Fixed Point Add and Sub testbench +// Module Name: FixedAddSub_tb +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: +// +// Revision: 0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FixedAddSub_tb #( + DATA_WIDTH = 32, + RADIX = 15 +); + +reg [DATA_WIDTH-1:0] x; +reg [DATA_WIDTH-1:0] y; +wire [DATA_WIDTH-1:0] zSub; +wire [DATA_WIDTH-1:0] zAdd; +wire overflowAdd; +wire overflowSub; + +FixedAdd #( + .DATA_WIDTH(DATA_WIDTH), + .RADIX(RADIX) +) dutAdd ( + .x(x), + .y(y), + .z(zAdd), + .overflow(overflowAdd) +); + +FixedSub #( + .DATA_WIDTH(DATA_WIDTH), + .RADIX(RADIX) +) dutSub ( + .x(x), + .y(y), + .z(zSub), + .overflow(overflowSub) +); + +initial begin + x = 10; + y = 5; + #1; + x = 32'h0FFFFFFF; + y = 32'hFFFFFFFF; + #1; + x = 32'h7FFFFFFF; + y = 32'h7FFFFFFF; + #1; + x = -32'h7FFFFFFF; + y = 32'h7FFFFFFF; + #1 $finish; +end + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sim_1/new/FixedMult_tb.sv b/fpga_new/rc_ports/rc_ports.srcs/sim_1/new/FixedMult_tb.sv new file mode 100644 index 000000000..bb49a55da --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sim_1/new/FixedMult_tb.sv @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/16/2020 02:36:20 PM +// Design Name: Fixed Point Multiplier Testbench +// Module Name: FixedMult_tb +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: +// +// Revision: 0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FixedMult_tb #( + DATA_WIDTH = 32, + RADIX =15 + ); + +reg [DATA_WIDTH-1:0] x; +reg [DATA_WIDTH-1:0] y; +wire [DATA_WIDTH-1:0] z; +wire overflow; + + +FixedMult #( + .DATA_WIDTH(DATA_WIDTH), + .RADIX(RADIX) +) dutMult ( + .x(x), + .y(y), + .z(z), + .overflow(overflow) +); + + +initial begin + x = 10; + y = 5; + #1; //Testing overflow: + x = 32'h0FFFFFFF; + y = 32'hFFFFFFFF; + #1; + x = 32'h7FFFFFFF; + y = 32'h7FFFFFFF; + #1; + x = -32'h7FFFFFFF; + y = 32'h7FFFFFFF; + #1; + x = 2; + y = 32'h7FFFFFFF; + #1; + x = 2; + y = 32'h40000000; + #1; + x = 2; + y = -32'h40000000; + #1; + x = 2; + y = -32'h3ffffffe; + #1 $finish; +end + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/AsyncFifo.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/AsyncFifo.sv new file mode 100644 index 000000000..9f585cf00 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/AsyncFifo.sv @@ -0,0 +1,158 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Will Stuckey +// +// Create Date: 02/02/2020 07:48:54 PM +// Design Name: Asynchronous FIFO +// Module Name: AsyncFifo +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: FfSync.sv +// +// Revision: 0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`ifndef _ASYNC_FIFO_ +`define _ASYNC_FIFO_ + +// used below to prevent the fifo buf from being inferenced into BRAM +// not sure if it causes issues with CDC for DP_BRAM +`define FORCE_NO_BRAM_INFERENCE + +`ifndef DEFAULT_SYNC_DEPTH + `define DEFAULT_SYNC_DEPTH 2 +`endif + +module AsyncFifo #( + FIFO_DATA_WIDTH=1, + localparam FIFO_DATA_WIDTH_MSB = (FIFO_DATA_WIDTH - 1), + + FIFO_DEPTH=16, + localparam FIFO_DEPTH_I = (FIFO_DEPTH - 1), + localparam ADDR_WIDTH = $clog2(FIFO_DEPTH), + localparam ADDR_MSB = (ADDR_WIDTH - 1), + + SYNC_DEPTH=`DEFAULT_SYNC_DEPTH + )( + input clk_wr_domain, + input rst_n_wr_domain, + input wr_en, + input [FIFO_DATA_WIDTH_MSB:0] d_in, + output logic wr_full, + output logic wr_err, + + input clk_rd_domain, + input rst_n_rd_domain, + input rd_en, + output logic [FIFO_DATA_WIDTH_MSB:0] d_out, + output logic rd_empty, + output logic rd_err + ); + + // prevent DP_BRAM inferencing here for CDC + // this define can be commented out at the top of the file + // to permit inferencing + `ifdef FORCE_NO_BRAM_INFERENCE + (* ram_style = "registers" *) + `endif + reg [FIFO_DATA_WIDTH_MSB:0] fifo_mem [0:FIFO_DEPTH_I]; + + ///////////////////////////////////////////////////////////////// + // WRITE DOMAIN ACTION + ///////////////////////////////////////////////////////////////// + + reg [ADDR_MSB:0] wr_addr; + + always_ff @(posedge clk_wr_domain or negedge rst_n_wr_domain) + begin: WRITE_BUFFER + if (wr_en && !wr_full && !wr_err) + begin + fifo_mem[wr_addr] <= d_in; + end + end + + always_ff @(posedge clk_wr_domain or negedge rst_n_wr_domain) + begin: WRITE_FLAGS + if (rst_n_wr_domain == 0) + begin: RESET_WRITE_FLAGS + wr_err <= 0; + end + else + begin: CHECK_INVALID_WRITE + if (wr_en && wr_full) + begin: SET_INVALID_READ_FLAG + wr_err <= 1'b1; + end + end + end + + ///////////////////////////////////////////////////////////////// + // WRITE DOMAIN CONTROL + ///////////////////////////////////////////////////////////////// + + ///////////////////////////////////////////////////////////////// + // READ DOMAIN ACTION + ///////////////////////////////////////////////////////////////// + + reg [ADDR_MSB:0] rd_addr; + + always_comb + begin: READ_BUFFER + if (rd_en && !rd_empty && !rd_err) begin + d_out = fifo_mem[rd_addr]; + end + else begin + d_out = 0; + end + end + + always_ff @(posedge clk_rd_domain or negedge rst_n_rd_domain) + begin: READ_FLAGS + if (rst_n_rd_domain == 0) + begin: RESET_READ_FLAGS + rd_err <= 0; + end + else + begin: CHECK_INVALID_READ + if (rd_en && rd_empty) + begin: SET_INVALID_READ_FLAG + rd_err <= 1'b1; + end + end + end + + ///////////////////////////////////////////////////////////////// + // READ DOMAIN CONTROL + ///////////////////////////////////////////////////////////////// + + ///////////////////////////////////////////////////////////////// + // POINTER CLOCK DOMAIN SYNCHRONIZATION + ///////////////////////////////////////////////////////////////// + + FfSync #( + .SYNC_WIDTH(FIFO_DATA_WIDTH), + .SYNC_DEPTH(SYNC_DEPTH) + ) rd_to_wd_sync ( + .clk(clk_wr_domain), + .rst(rst_n_wr_domain), + .d_in(), + .d_out() + ); + + FfSync #( + .SYNC_WIDTH(FIFO_DATA_WIDTH), + .SYNC_DEPTH(SYNC_DEPTH) + ) wd_to_rd_sync ( + + ); + +endmodule + +`endif diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FfSync.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FfSync.sv new file mode 100644 index 000000000..58dd7a630 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FfSync.sv @@ -0,0 +1,74 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Will Stuckey +// +// Create Date: 02/02/2020 12:08:15 AM +// Design Name: Flip-Flop Synchronizer +// Module Name: FfSync +// Project Name: RoboCup +// Target Devices: Artix 7 Family +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: none +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`ifndef DEFAULT_SYNC_WIDTH + `define DEFAULT_SYNC_WIDTH 1 +`endif + +`ifndef DEFAULT_SYNC_DEPTH + `define DEFAULT_SYNC_DEPTH 2 +`endif + +module FfSync #( + parameter SYNC_WIDTH=`DEFAULT_SYNC_WIDTH, + parameter SYNC_DEPTH=`DEFAULT_SYNC_DEPTH + )( + input clk, + input rst_n, + input [SYNC_WIDTH-1:0] d_in, + output [SYNC_WIDTH-1:0] d_out + ); + + // ffsync buf, use unpacked array for dyn gen, apply directive to prevent SRL inference + (* srl_style = "register" *) + reg [SYNC_WIDTH-1:0] sync_buf [SYNC_DEPTH-1:0]; + + // initial sync stage and reset + always_ff @(posedge clk or negedge rst_n) + begin : FIRST_SYNC_STAGE + if (rst_n == 0) begin + sync_buf[0] <= 0; + end + else begin + sync_buf[0] <= d_in; + end + end + + // dynamically generate sync chain + genvar ff_depth_index; + for (ff_depth_index = 1; ff_depth_index < SYNC_DEPTH; ff_depth_index++) + begin: SYNC_CHAIN_GEN + if (SYNC_DEPTH < 2) + begin: E_INVAL_DEPTH + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. SYNC_DEPTH must be >= 2.", SYNC_DEPTH); + end + else begin + always_ff @(posedge clk) + begin: SYNC_CHAIN_ELEMENT + sync_buf[ff_depth_index] <= sync_buf[ff_depth_index-1]; + end + end + end + + // output + assign d_out = sync_buf[SYNC_DEPTH-1]; + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoGcp.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoGcp.sv new file mode 100644 index 000000000..f0cbed77b --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoGcp.sv @@ -0,0 +1,54 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: William Stuckey +// +// Create Date: 02/06/2020 09:55:39 AM +// Design Name: FIFO Gray Code Pointer +// Module Name: FifoGcp +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: none +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FifoGcp #( + parameter SUPPORTED_DEPTH = 0, + localparam BIN_ADDR_WIDTH = $clog2(SUPPORTED_DEPTH), + localparam BIN_ADDR_MSB = BIN_ADDR_WIDTH - 1, + localparam GC_PTR_WIDTH = BIN_ADDR_WIDTH + 1, + localparam GC_PTR_MSB = GC_PTR_WIDTH - 1 + )( + input clk, + input rst_n, + input inc, + + output logic [BIN_ADDR_MSB:0] bin_ptr, + output logic [GC_PTR_MSB:0] gc_ptr + ); + + generate + if (SUPPORTED_DEPTH <= 0) + begin: DEPTH_NOT_SET_ELABORATION_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. SUPPORTED_DEPTH must be > 0.", SUPPORTED_DEPTH); + end + endgenerate + + generate + if ((SUPPORTED_DEPTH & (SUPPORTED_DEPTH - 1)) != 0) + begin: DEPTH_NOT_POW2_ELABORATION_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. SUPPORTED_DEPTH must be a power of 2.", SUPPORTED_DEPTH); + end + endgenerate + + + +endmodule: FifoGcp diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoModule.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoModule.sv new file mode 100644 index 000000000..a241fb795 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoModule.sv @@ -0,0 +1,101 @@ +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/10/2020 12:08:15 AM +// Design Name: Fifo Module +// Module Name: FifoModule +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: +// +// Revision:0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`ifndef _FIFO_MODULE_ +`define _FIFO_MODULE_ + +module FifoModule #( + MAX_SIZE = 10, + DATA_BIT_WIDTH = 32, + ALMOST_FULL_SIZE = 8, + ALMOST_EMPTY_SIZE = 2, + localparam COUNT_SIZE = $clog2(MAX_SIZE) +)( + input clk, + input [DATA_BIT_WIDTH - 1:0] dataIn, + input rd, + input wr, + output logic [DATA_BIT_WIDTH-1:0] dataOut, + input rst, + output empty, + output full, + output almost_full, + output almost_empty +); + + +reg [COUNT_SIZE - 1:0] count = 0; +reg [DATA_BIT_WIDTH - 1:0] queue [0:MAX_SIZE - 1]; +reg [COUNT_SIZE - 1:0] front = 0; + +assign empty = (count == 0)? 1'b1:0; +assign full = (count == MAX_SIZE)? 1'b1:0; +assign almost_empty = (count <= ALMOST_EMPTY_SIZE)? 1'b1:0; +assign almost_full = (count >= ALMOST_FULL_SIZE)? 1'b1:0; + +generate + if (MAX_SIZE <= 1) + begin: INVALID_MAX_SIZE_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. MAX_SIZE must be > 1.", MAX_SIZE); + end + + if (DATA_BIT_WIDTH <= 0) + begin: INVALID_DATA_WIDTH_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. DATA_BIT_WIDTH must be > 0.", DATA_BIT_WIDTH); + end + + if (ALMOST_FULL_SIZE > MAX_SIZE || ALMOST_FULL_SIZE <= 0) + begin: INVALID_ALMOST_FULL_SIZE_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. ALMOST_FULL_SIZE must be <= FULL and > 0.", ALMOST_FULL_SIZE); + end + + if (ALMOST_EMPTY_SIZE < 0) + begin: INVALID_ALMOST_EMPTY_SIZE_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. ALMOST_FULL_SIZE must be >= 0.", ALMOST_EMPTY_SIZE); + end + +endgenerate + + +always_ff @(posedge clk) begin + if (rst) + begin: RESET + front <= 0; + count <= 0; + end else begin + + if (rd == 1'b1 && count != 0) + begin: READ + count = count - 1; + dataOut = queue[front]; + front = (front + 1) % MAX_SIZE; + end + + if (wr == 1'b1 && count < MAX_SIZE) + begin: WRITE + queue[(front + count) % MAX_SIZE] = dataIn; + count = count + 1; + end + end +end + +endmodule + +`endif \ No newline at end of file diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoModule_tb.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoModule_tb.sv new file mode 100644 index 000000000..718190efa --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FifoModule_tb.sv @@ -0,0 +1,127 @@ +`timescale 1ns/10ps + +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/10/2020 12:08:15 AM +// Design Name: Fifo Module Testbench +// Module Name: FifoModule_tb +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: FifoModule.sv +// +// Revision:0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module FifoModule_tb #( + localparam MAX_SIZE = 9, + localparam DATA_BIT_WIDTH = 32, + localparam ALMOST_FULL_SIZE = 8, + localparam ALMOST_EMPTY_SIZE = 2 +); + +reg clk, rd, wr, rst; +reg [DATA_BIT_WIDTH - 1:0] dataIn; + +wire empty, full, almost_full, almost_empty; +wire [DATA_BIT_WIDTH - 1:0] dataOut; + +FifoModule #( + .DATA_BIT_WIDTH(DATA_BIT_WIDTH), + .MAX_SIZE(MAX_SIZE), + .ALMOST_EMPTY_SIZE(ALMOST_EMPTY_SIZE), + .ALMOST_FULL_SIZE(ALMOST_FULL_SIZE) + ) dut ( + .clk(clk), + .dataIn(dataIn), + .rd(rd), + .wr(wr), + .dataOut(dataOut), + .rst(rst), + .empty(empty), + .full(full), + .almost_full(almost_full), + .almost_empty(almost_empty) +); + + +initial begin + + // Reset + clk = 0; + dataIn = 0; + rd = 0; + wr = 0; + rst = 1'b1; + + #2; + // Load from 1 to 10 + #1; + rst = 0; + wr = 1'b1; + dataIn = 32'h1; + #1; + dataIn = 32'h2; + #1; + dataIn = 32'h3; + #1; + dataIn = 32'h4; + #1; + dataIn = 32'h5; + #1; + dataIn = 32'h6; + #1; + dataIn = 32'h7; + #1; + dataIn = 32'h8; + #1; + dataIn = 32'h9; + #1; + dataIn = 32'hA; // Shouldn't add this + #1; + dataIn = 32'hB; // Shouldn't add this + #1; + wr = 0; + rd = 1'b1; + #10; + rd = 1'b1; //Read and write at the same time + wr = 1'b1; + dataIn = 32'h1; + #1; + dataIn = 32'h2; + #1; + dataIn = 32'h3; + #1; + dataIn = 32'h4; + #1; + dataIn = 32'h5; + #1; + dataIn = 32'h6; + #1; + dataIn = 32'h7; + #1; + dataIn = 32'h8; + #1; + dataIn = 32'h9; + #1; + dataIn = 32'hA; // Shouldn't add this + #1; + dataIn = 32'hB; // Shouldn't add this + #1; + wr = 0; + rd = 1'b1; + #13 $finish; +end + + + +always #0.5 clk = ~clk; + +endmodule \ No newline at end of file diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedAdd.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedAdd.sv new file mode 100644 index 000000000..d50034ec5 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedAdd.sv @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/16/2020 02:36:20 PM +// Design Name: Fixed Point Add +// Module Name: FixedAdd +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: +// +// Revision: 0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FixedAdd #( + DATA_WIDTH = 32, + RADIX =15 // Not relevant for add +)( + input [DATA_WIDTH-1:0] x, + input [DATA_WIDTH-1:0] y, + output [DATA_WIDTH-1:0] z, + output overflow +); + +wire [DATA_WIDTH-1:0] result; + +assign overflow = result[DATA_WIDTH-1]; +assign z = $signed(x) + $signed(y); + +generate + if (DATA_WIDTH < 1) + begin: INVALID_DATA_WIDTH_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. DATA_BIT_WIDTH must be > 0.", DATA_WIDTH); + end +endgenerate + +assign result = (x[DATA_WIDTH-1]==0 && y[DATA_WIDTH-1]==0)? + x[DATA_WIDTH-2:0] + y[DATA_WIDTH-2:0]: + (x[DATA_WIDTH-1]==1 && y[DATA_WIDTH-1]==1)? + (-x[DATA_WIDTH-2:0]) + (-y[DATA_WIDTH-2:0]):0; + + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedDiv.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedDiv.sv new file mode 100644 index 000000000..246294e65 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedDiv.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/18/2020 06:45:41 PM +// Design Name: +// Module Name: FixedDiv +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FixedDiv( + + ); +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv new file mode 100644 index 000000000..9214bdc16 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedMult.sv @@ -0,0 +1,50 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/16/2020 02:36:20 PM +// Design Name: Fixed Point Multiplier +// Module Name: FixedMult +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: +// +// Revision: 0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FixedMult #( + DATA_WIDTH = 32, + RADIX =15 +)( + input [DATA_WIDTH-1:0] x, + input [DATA_WIDTH-1:0] y, + output [DATA_WIDTH-1:0] z, + output overflow +); + +wire [2*DATA_WIDTH-1:0] result; + +generate + if (DATA_WIDTH < 1) + begin: INVALID_DATA_WIDTH_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. DATA_BIT_WIDTH must be > 0.", DATA_WIDTH); + end +endgenerate + + +assign overflow = (result >> (DATA_WIDTH-1) != 0); +assign result = (((x[DATA_WIDTH-1]==1)?$unsigned(-x):$unsigned(x)) + *((y[DATA_WIDTH-1]==1)?$unsigned(-y):$unsigned(y)))>>>RADIX; + +assign z = result[DATA_WIDTH-1:0]; + + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedSub.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedSub.sv new file mode 100644 index 000000000..e4c03798f --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedSub.sv @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/16/2020 02:36:20 PM +// Design Name: Fixed Point Subtract +// Module Name: FixedSub +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: +// +// Revision: 0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FixedSub #( + DATA_WIDTH = 32, + RADIX =15 // Not relevant for add +)( + input [DATA_WIDTH-1:0] x, + input [DATA_WIDTH-1:0] y, + output [DATA_WIDTH-1:0] z, + output logic overflow +); + +FixedAdd #( + .DATA_WIDTH(DATA_WIDTH), + .RADIX(RADIX) +) dutAdd ( + .x(x), + .y(-y), + .z(z), + .overflow(overflow) +); + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiMaster.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiMaster.sv new file mode 100644 index 000000000..cc6525be2 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiMaster.sv @@ -0,0 +1,126 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: RoboJackets +// Engineer: Arthur Siqueira +// +// Create Date: 02/02/2020 12:08:15 AM +// Design Name: SPI Master +// Module Name: SpiMaster +// Project Name: RoboCup +// Target Devices: Artix 7 +// Tool Versions: 2019.2 +// Description: +// +// Dependencies: +// +// Revision: 0.01 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SpiMaster #( + DATA_BIT_WIDTH = 8, + + localparam COUNTER_WIDTH = $clog2(DATA_BIT_WIDTH), + localparam RESET = 0, + localparam IDLE = 1, + localparam LOAD = 2, + localparam TRANSACT = 3, + localparam UNLOAD =4 +)( + input clk, + input rst, + input miso, + input start, + input [DATA_BIT_WIDTH-1:0] dataIn, + + output mosi, + output logic cs, + output valid, + output busy, + output logic [DATA_BIT_WIDTH-1:0] dataOut +); + + + +reg [COUNTER_WIDTH-1:0] count = 0; +reg [DATA_BIT_WIDTH-1:0] mosi_d; +reg [DATA_BIT_WIDTH-1:0] miso_d; +reg [2:0] state = 0; + +assign busy = (state == TRANSACT); +assign mosi = cs? 1'bz: mosi_d[DATA_BIT_WIDTH-1]; +assign valid = (state == UNLOAD); +assign cs = (state == IDLE || state == RESET); + +generate + if (DATA_BIT_WIDTH < 1) + begin: INVALID_DATA_BIT_WIDTH_ERROR + $fatal(1, "Fatal elaboration error. Invalid parameter value %b. DATA_BIT_WIDTH must be > 0.", DATA_BIT_WIDTH); + end +endgenerate + +always_ff @(posedge clk) begin + if (rst == 0) + state = RESET; + else + case (state) + RESET: + begin + state = IDLE; + end + IDLE: + begin + if (start) + state = LOAD; + end + LOAD: + begin + state = TRANSACT; + end + TRANSACT: + begin + if (count == 0) + state = UNLOAD; + end + UNLOAD: + begin + if (start) + state = LOAD; + else + state = IDLE; + end + endcase +end + +always_ff @(posedge clk) begin + if (state == TRANSACT) + miso_d = {miso_d[DATA_BIT_WIDTH-2:0], miso}; + else + miso_d <= 0; +end + +always_ff @(negedge clk) begin + if (state == TRANSACT) + mosi_d <= {mosi_d[DATA_BIT_WIDTH-2:0], 1'b0}; + else if (state == LOAD) + mosi_d <= dataIn; + else + mosi_d <= 0; + + if (state == UNLOAD) + dataOut <= miso_d; + else + dataOut <= 0; + + if (state == LOAD) + count <= DATA_BIT_WIDTH; + else if (state == TRANSACT) + count = count - 1; + else + count <= 0; +end + +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiSlave.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiSlave.sv new file mode 100644 index 000000000..7e6b54986 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/SpiSlave.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/02/2020 12:08:15 AM +// Design Name: +// Module Name: SpiSlave +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SpiSlave( + + ); +endmodule diff --git a/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/addFixed.sv b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/addFixed.sv new file mode 100644 index 000000000..1fc941ede --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/addFixed.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/16/2020 02:34:28 PM +// Design Name: +// Module Name: addFixed +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module addFixed( + + ); +endmodule diff --git a/fpga_new/rc_ports/rc_ports.xpr b/fpga_new/rc_ports/rc_ports.xpr new file mode 100644 index 000000000..7e7f48a29 --- /dev/null +++ b/fpga_new/rc_ports/rc_ports.xpr @@ -0,0 +1,271 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/fpga_new/rc_ports/vivado.jou b/fpga_new/rc_ports/vivado.jou new file mode 100644 index 000000000..7e2c390d1 --- /dev/null +++ b/fpga_new/rc_ports/vivado.jou @@ -0,0 +1,38 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Feb 17 19:23:43 2020 +# Process ID: 4684 +# Current directory: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent784 C:\Users\arthu\Desktop\robocup-firmware\fpga_new\rc_ports\rc_ports.xpr +# Log file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/vivado.log +# Journal file: C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.xpr +update_compile_order -fileset sources_1 +launch_simulation +source FixedMult_tb.tcl +close_sim +launch_simulation +source FixedMult_tb.tcl +reset_run synth_1 +launch_runs synth_1 -jobs 4 +wait_on_run synth_1 +launch_runs impl_1 -jobs 4 +wait_on_run impl_1 +open_run impl_1 +reset_run impl_1 +launch_runs impl_1 -jobs 4 +wait_on_run impl_1 +refresh_design +close_design +reset_run impl_1 +launch_runs impl_1 -jobs 4 +wait_on_run impl_1 +open_run impl_1 +close [ open C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedDiv.sv w ] +add_files C:/Users/arthu/Desktop/robocup-firmware/fpga_new/rc_ports/rc_ports.srcs/sources_1/new/FixedDiv.sv +update_compile_order -fileset sources_1 +close_sim