riscv: backport mainline SG2042 and SG2044 platform support - #383
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RevySR wants to merge 218 commits into
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riscv: backport mainline SG2042 and SG2044 platform support#383RevySR wants to merge 218 commits into
RevySR wants to merge 218 commits into
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mainline inclusion commit a630427 category: cleanup bugzilla: RVCK-Project#63 -------------------------------- Patch series "kdump: use generic functions to simplify crashkernel reservation in arch", v3. In the current arm64, crashkernel=,high support has been finished after several rounds of posting and careful reviewing. The code in arm64 which parses crashkernel kernel parameters firstly, then reserve memory can be a good example for other ARCH to refer to. Whereas in x86_64, the code mixing crashkernel parameter parsing and memory reserving is twisted, and looks messy. Refactoring the code to make it more readable maintainable is necessary. Here, firstly abstract the crashkernel parameter parsing code into parse_crashkernel() to make it be able to parse crashkernel=,high|low. Then abstract the crashkernel memory reserving code into a generic function reserve_crashkernel_generic(). Finally, in ARCH which crashkernel=,high support is needed, a simple arch_reserve_crashkernel() can be added to call above two functions. This can remove the duplicated implmentation code in each ARCH, like arm64, x86_64 and riscv. crashkernel=512M,high crashkernel=512M,high crashkernel=256M,low crashkernel=512M,high crashkernel=0M,low crashkernel=0M,high crashkernel=256M,low crashkernel=512M crashkernel=512M@0x4f000000 crashkernel=1G-4G:256M,4G-64G:320M,64G-:576M crashkernel=0M This patch (of 9): In all call sites of __parse_crashkernel(), the parameter 'name' is hardcoded as "crashkernel=". So remove the unnecessary parameter 'name', add local varibale 'name' inside __parse_crashkernel() instead. Link: https://lkml.kernel.org/r/20230914033142.676708-1-bhe@redhat.com Link: https://lkml.kernel.org/r/20230914033142.676708-2-bhe@redhat.com Signed-off-by: Baoquan He <bhe@redhat.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen Jiahao <chenjiahao16@huawei.com> Cc: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> (cherry picked from commit a630427) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit a9e1a3d category: cleanup bugzilla: RVCK-Project#63 -------------------------------- Add two parameters 'low_size' and 'high' to function parse_crashkernel(), later crashkernel=,high|low parsing will be added. Make adjustments in all call sites of parse_crashkernel() in arch. Link: https://lkml.kernel.org/r/20230914033142.676708-3-bhe@redhat.com Signed-off-by: Baoquan He <bhe@redhat.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen Jiahao <chenjiahao16@huawei.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> (cherry picked from commit a9e1a3d) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
…ow parsing mainline inclusion commit 70916e9 category: feature bugzilla: RVCK-Project#63 -------------------------------- Now parse_crashkernel() is a real entry point for all kinds of crahskernel parsing on any architecture. And wrap the crahskernel=,high|low handling inside CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION ifdeffery scope. Link: https://lkml.kernel.org/r/20230914033142.676708-4-bhe@redhat.com Signed-off-by: Baoquan He <bhe@redhat.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen Jiahao <chenjiahao16@huawei.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> (cherry picked from commit 70916e9) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 0ab9716 category: feature bugzilla: RVCK-Project#63 -------------------------------- In architecture like x86_64, arm64 and riscv, they have vast virtual address space and usually have huge physical memory RAM. Their crashkernel reservation doesn't have to be limited under 4G RAM, but can be extended to the whole physical memory via crashkernel=,high support. Now add function reserve_crashkernel_generic() to reserve crashkernel memory if users specify any case of kernel pamameters, like crashkernel=xM[@offset] or crashkernel=,high|low. This is preparation to simplify code of crashkernel=,high support in architecutures. Link: https://lkml.kernel.org/r/20230914033142.676708-5-bhe@redhat.com Signed-off-by: Baoquan He <bhe@redhat.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen Jiahao <chenjiahao16@huawei.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> (cherry picked from commit 0ab9716) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit b631b95 category: feature bugzilla: RVCK-Project#63 -------------------------------- Both crashk_res and crashk_low_res are used to mark the reserved crashkernel regions in iomem_resource tree. And later the generic crashkernel resrvation will be added into crash_core.c. So move crashk_res and crashk_low_res definition into crash_core.c to avoid compiling error if CONFIG_CRASH_CORE=on while CONFIG_KEXEC_CORE is unset. Meanwhile include <asm/crash_core.h> in <linux/crash_core.h> if generic reservation is needed. In that case, <asm/crash_core.h> need be added by ARCH. In asm/crash_core.h, ARCH can provide its own macro definitions to override macros in <linux/crash_core.h> if needed. Wrap the including into CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION ifdeffery scope to avoid compiling error in other ARCH-es which don't take the generic reservation way yet. Link: https://lkml.kernel.org/r/20230914033142.676708-6-bhe@redhat.com Signed-off-by: Baoquan He <bhe@redhat.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen Jiahao <chenjiahao16@huawei.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> (cherry picked from commit b631b95) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 0e3f364 category: feature bugzilla: RVCK-Project#63 -------------------------------- Currently x86, ARM and ARM64 support generic CPU vulnerabilites, but RISC-V not, such as: # cd /sys/devices/system/cpu/vulnerabilities/ x86: # cat spec_store_bypass Mitigation: Speculative Store Bypass disabled via prctl and seccomp # cat meltdown Not affected ARM64: # cat spec_store_bypass Mitigation: Speculative Store Bypass disabled via prctl and seccomp # cat meltdown Mitigation: PTI RISC-V: # cat /sys/devices/system/cpu/vulnerabilities # ... No such file or directory As SiFive RISC-V Core IP offerings are not affected by Meltdown and Spectre, it can use the default weak function as below: # cat spec_store_bypass Not affected # cat meltdown Not affected Link: https://www.sifive.cn/blog/sifive-statement-on-meltdown-and-spectre Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://lore.kernel.org/r/20240703022732.2068316-1-ruanjinjie@huawei.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> (cherry picked from commit 0e3f364) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 4bf9706 category: bugfix bugzilla: RVCK-Project#63 -------------------------------- Follow the patterns of the other architectures that use GENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwrite vulnerability and mitigation. The mitigation is to disable all vector which is accomplished by clearing the bit from the cpufeature field. Ghostwrite only affects thead c9xx CPUs that impelment xtheadvector, so the vulerability will only be mitigated on these CPUs. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-14-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> (cherry picked from commit 4bf9706) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit b67a1ee category: bugfix bugzilla: RVCK-Project#63 -------------------------------- When kexec_file_load places segments with buf_max=ULONG_MAX and top_down=true, they land at the highest available physical addresses. On RISC-V the size of the linear mapping is determined by the active VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 extend the range substantially further. When the installed physical memory exceeds the direct map size of the active mode, top-down placement puts DTB/initrd at physical addresses outside the linearly mapped region. The kexec'd kernel cannot reach them during early boot, triggering a page fault at memcmp in start_kernel. Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects the runtime direct map boundary for the active VM mode (SV39/SV48/ SV57). This keeps all kexec segments within the linearly mapped region while preserving the upstream top_down allocation strategy. Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Link: https://patch.msgid.link/20260519170641.123517-1-gaohan@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit b67a1ee) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit bce3513 category: bugfix bugzilla: RVCK-Project#63 -------------------------------- On RISC-V, also select ARCH_KEEP_MEMBLOCK if kexec is selected, not only if ACPI is selected. This is because kexec requires the memblock areas to be kept after boot to initialize the secondary kernel. This is needed for both Device Tree and ACPI platforms. Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Link: https://patch.msgid.link/20260519165546.123105-1-gaohan@iscas.ac.cn [pjw@kernel.org: change to add the dependency on kexec, rather than making it unconditional; rewrite the patch description accordingly] Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit bce3513) [ Han Gao: resolve conflit ] Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 16d18e3 category: cleanup bugzilla: RVCK-Project#63 -------------------------------- Move vendor errata definitions into errata_list_vendors.h. Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Tested-by: Han Gao <rabenda.cn@gmail.com> Link: https://lore.kernel.org/r/20250713155321.2064856-2-guoren@kernel.org [pjw@kernel.org: updated to apply and to make the whitespace consistent] Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit 16d18e3) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- The early version of XuanTie C910 core has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the store queue for a long time. That would cause significant problems for communication between multi-cores. This problem was found on sg2042 & th1520 platforms with the qspinlock lock torture test. So appending a fence w.o could immediately flush the store merge buffer and let other cores see the write result. This will apply the WRITE_ONCE errata to handle the non-standard behavior via appending a fence w.o instruction for WRITE_ONCE(). This problem is only observed on the sg2042 hardware platform by running the lock_torture test program for half an hour. The problem was not found in the user space application, because interrupt can break the livelock. Reviewed-by: Leonardo Bras <leobras@redhat.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Tested-by: Han Gao <gaohan@iscas.ac.cn> Tested-by: Yao Zi <me@ziyao.cc> Cc: Chen Wang <unicorn_wang@outlook.com> Cc: Inochi Amaoto <inochiama@gmail.com> Cc: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Cc: Paul Walmsley <pjw@kernel.org> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20260412143116.1445893-1-guoren@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn> (cherry picked from commit 20df941cb435dc1aec3e2027e13254780219d4df)
mainline inclusion commit 299d623 category: feature bugzilla: RVCK-Project#63 -------------------------------- The existing irq_domain_add_*() functions used to instantiate an IRQ domain are wrappers built on top of __irq_domain_add() and describe the domain properties using a bunch of parameters. Adding more parameters and wrappers to hide new parameters in the existing code lead to more and more code without any relevant value and without any flexibility. Introduce irq_domain_instantiate() where the interrupt domain properties are given using a irq_domain_info structure instead of the bunch of parameters to allow flexibility and easy evolution. irq_domain_instantiate() performs the same operation as the one done by __irq_domain_add(). For compatibility reason with existing code, keep __irq_domain_add() but convert it to irq_domain_instantiate(). [ tglx: Fixed up struct initializer coding style ] Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-3-herve.codina@bootlin.com (cherry picked from commit 299d623) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 7573985 category: feature bugzilla: RVCK-Project#63 -------------------------------- In order to use irq_domain_instantiate() from several places such as irq_domain_create_hierarchy(), irq_domain_instantiate() needs to handle additional domain flags. Add the required infrastructure. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-8-herve.codina@bootlin.com (cherry picked from commit 7573985) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 419e377 category: feature bugzilla: RVCK-Project#63 -------------------------------- To use irq_domain_instantiate() from irq_domain_create_hierarchy(), irq_domain_instantiate() needs to handle the domain hierarchy parent. Add the required functionality. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-9-herve.codina@bootlin.com (cherry picked from commit 419e377) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit dbd56ab category: feature bugzilla: RVCK-Project#63 -------------------------------- The interrupt domain name computation and setting is directly done in __irq_domain_create(). This leads to a quite long __irq_domain_create() function. In order to simplify __irq_domain_create() and isolate the domain name computation and setting, move the related operations to a dedicated function. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-6-herve.codina@bootlin.com (cherry picked from commit dbd56ab) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 24a4f4e category: cleanup bugzilla: RVCK-Project#63 -------------------------------- The existing __irq_domain_create() use a bunch of parameters to create an irq domain. With the introduction of irq_domain_info structure, these parameters are available in the information structure itself. Using directly this information structure allows future flexibility to add other parameters in a simple way without the need to change the __irq_domain_create() prototype. Convert __irq_domain_create() to use the information structure. [ tglx: Fixup struct initializer ] Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-7-herve.codina@bootlin.com (cherry picked from commit 24a4f4e) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 0b21add category: feature bugzilla: RVCK-Project#63 -------------------------------- irq_domain_update_bus_token() is the only way to set the domain bus token. This is sub-optimal as irq_domain_update_bus_token() can be called only once the domain is created and needs to revert some operations, change the domain name and redo the operations. In order to avoid this revert/change/redo sequence, take the domain bus into account token during the domain creation. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240614173232.1184015-12-herve.codina@bootlin.com (cherry picked from commit 0b21add) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit e4d001b category: feature bugzilla: RVCK-Project#63 -------------------------------- Creating an irq domain that serves as an MSI parent requires a substantial amount of esoteric boiler-plate code, some of which is often provided twice (such as the bus token). To make things a bit simpler for the unsuspecting MSI tinkerer, provide a helper that does it for them, and serves as documentation of what needs to be provided. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250513172819.2216709-3-maz@kernel.org (cherry picked from commit e4d001b) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 7d189c7 category: feature bugzilla: RVCK-Project#63 -------------------------------- Most ARM(64) PCI/MSI domains mask and unmask in the parent domain after or before the PCI mask/unmask operation takes place. So there are more than a dozen of the same wrapper implementation all over the place. Don't make the same mistake with the new per device PCI/MSI domains and provide a new MSI feature flag, which lets the domain implementation enable this sequence in the PCI/MSI code. Signed-off-by: Shivamurthy Shastri <shivamurthy.shastri@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/87ed8j34pj.ffs@tglx (cherry picked from commit 7d189c7) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 7a721a2 category: feature bugzilla: RVCK-Project#63 -------------------------------- As the MSI controller on SG2044 uses PLIC as the underlying interrupt controller, it needs to call irq_enable() and irq_disable() to startup/shutdown interrupts. Otherwise, the MSI interrupt can not be startup correctly and will not respond any incoming interrupt. Introduce irq_chip_startup_parent() and irq_chip_shutdown_parent() to allow the interrupt controller to call the irq_startup()/irq_shutdown() callbacks of the parent interrupt chip. In case the irq_startup()/irq_shutdown() callbacks are not implemented for the parent interrupt chip, this will fallback to irq_chip_enable_parent() or irq_chip_disable_parent(). Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/all/20250813232835.43458-2-inochiama@gmail.com Link: https://lore.kernel.org/lkml/20250722224513.22125-1-inochiama@gmail.com/ (cherry picked from commit 7a721a2) Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 54f45a3 category: feature bugzilla: RVCK-Project#63 -------------------------------- As the RISC-V PLIC cannot apply affinity settings without invoking irq_enable(), it will make the interrupt unavailble when used as an underlying interrupt chip for the MSI controller. Implement the irq_startup() and irq_shutdown() callbacks for the PCI MSI and MSI-X templates. For chips that specify MSI_FLAG_PCI_MSI_STARTUP_PARENT, the parent startup and shutdown functions are invoked. That allows the interrupt on the parent chip to be enabled if the interrupt has not been enabled during allocation. This is necessary for MSI controllers which use PLIC as underlying parent interrupt chip. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/all/20250813232835.43458-3-inochiama@gmail.com (cherry picked from commit 54f45a3) Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
…]_parent() mainline inclusion commit 727e914 category: feature bugzilla: RVCK-Project#63 -------------------------------- For MSI controllers which only support MSI_FLAG_PCI_MSI_MASK_PARENT, the newly added callback irq_startup() and irq_shutdown() for pci_msi[x]_template will not unmask or mask the interrupt when startup() resp. shutdown() is invoked. This prevents the interrupt from being enabled resp. disabled. Invoke irq_[un]mask_parent() in cond_[startup|shutdown]_parent(), when the interrupt has the MSI_FLAG_PCI_MSI_MASK_PARENT flag set. Fixes: 54f45a3 ("PCI/MSI: Add startup/shutdown for per device domains") Reported-by: Linux Kernel Functional Testing <lkft@linaro.org> Reported-by: Nathan Chancellor <nathan@kernel.org> Reported-by: Wei Fang <wei.fang@nxp.com> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Wei Fang <wei.fang@nxp.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox/SG2042 Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/all/20250827230943.17829-1-inochiama@gmail.com Closes: https://lore.kernel.org/regressions/aK4O7Hl8NCVEMznB@monster/ Closes: https://lore.kernel.org/regressions/20250826220959.GA4119563@ax162/ Closes: https://lore.kernel.org/all/20250827093911.1218640-1-wei.fang@nxp.com/ (cherry picked from commit 727e914) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 72e257c category: feature bugzilla: RVCK-Project#63 -------------------------------- All irqdomains which provide MSI parent domain functionality for per device MSI domains need to provide a select() callback for the irqdomain and a function to initialize the child domain. Most of these functions would just be copy&paste with minimal modifications, so provide a library function which implements the required functionality and is customizable via parent_domain::msi_parent_ops. The check for the supported bus tokens in msi_lib_init_dev_msi_info() is expanded step by step within the next patches. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anna-Maria Behnsen <anna-maria@linutronix.de> Signed-off-by: Shivamurthy Shastri <shivamurthy.shastri@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240623142234.840975799@linutronix.de (cherry picked from commit 72e257c) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 8c41cce category: feature bugzilla: RVCK-Project#63 -------------------------------- Add the bus tokens for DOMAIN_BUS_PCI_DEVICE_MSI and DOMAIN_BUS_PCI_DEVICE_MSIX to the common child init function. Provide the match mask which can be used by parent domain implementation so the bitmask based child bus token match works. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anna-Maria Behnsen <anna-maria@linutronix.de> Signed-off-by: Shivamurthy Shastri <shivamurthy.shastri@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240623142234.964056815@linutronix.de (cherry picked from commit 8c41cce) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 1c000dc category: feature bugzilla: RVCK-Project#63 -------------------------------- msi_lib_init_dev_msi_info() sets the default irq_eoi()/irq_ack() callbacks unconditionally. This is correct for all existing users, but prevents the IMSIC driver to be moved to the MSI library implementation. Introduce chip_flags in struct msi_parent_ops, which instruct the library to selectively set the callbacks depending on the flags, and update all current users to set them. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250217085657.789309-3-apatel@ventanamicro.com (cherry picked from commit 1c000dc) Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 7170d3b category: feature bugzilla: RVCK-Project#63 -------------------------------- Some PWM devices require sleeping, for example if the pwm device is connected over I2C. However, many PWM devices could be used from atomic context, e.g. memory mapped PWM. This is useful for, for example, the pwm-ir-tx driver which requires precise timing. Sleeping causes havoc with the generated IR signal. Since not all PWM devices can support atomic context, we also add a pwm_might_sleep() function to check if is not supported. Signed-off-by: Sean Young <sean@mess.org> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> (cherry picked from commit 7170d3b) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 4e59267 category: feature bugzilla: RVCK-Project#63 -------------------------------- Currently a pwm_chip stores in its struct device *dev member a pointer to the parent device. Preparing a change that embeds a full struct device in struct pwm_chip, this accessor function should be used in all drivers directly accessing chip->dev now. This way struct pwm_chip and this new function can be changed without having to touch all drivers in the same change set. Make use of this function in the framework's core sources. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/cc30090d2f9762bed9854a55612144bccc910781.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> (cherry picked from commit 4e59267) [ Han Gao: drivers/pwm/core.c: 's/chip->dev/pwmchip_parent(chip)/g' ] Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 24003d5 category: feature bugzilla: RVCK-Project#63 -------------------------------- These functions are useful to store and query driver private data depending on the pwm_chip. After struct pwm_chip got its own struct device, this can make use of dev_get_drvdata() and dev_set_drvdata() on that device. These functions are required already now to convert drivers to pwmchip_alloc() which must happen before changing pwm_chip::dev. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/67514cdf29d29bd8b4ad8d44fac87f6ae6dca1e5.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> (cherry picked from commit 24003d5) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 024913d category: feature bugzilla: RVCK-Project#63 -------------------------------- This function allocates a struct pwm_chip and driver data. Compared to the status quo the split into pwm_chip and driver data is new, otherwise it doesn't change anything relevant (yet). The intention is that after all drivers are switched to use this allocation function, its possible to add a struct device to struct pwm_chip to properly track the latter's lifetime without touching all drivers again. Proper lifetime tracking is a necessary precondition to introduce character device support for PWMs (that implements atomic setting and doesn't suffer from the sysfs overhead of the /sys/class/pwm userspace support). The new function pwmchip_priv() (obviously?) only works for chips allocated with pwmchip_alloc(). Link: https://lore.kernel.org/r/9577d6053a5a52536057dc8654ff567181c2da82.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> (cherry picked from commit 024913d) [ Han Gao: manual add patch content because reorder cannot apply patches ] Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit b0cde62 category: feature bugzilla: RVCK-Project#63 -------------------------------- This allows to simplify drivers that use clk_rate_exclusive_get() in their probe routine as calling clk_rate_exclusive_put() is cared for automatically. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20240104225512.1124519-2-u.kleine-koenig@pengutronix.de Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Stephen Boyd <sboyd@kernel.org> (cherry picked from commit b0cde62) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 6b1aa3c category: feature bugzilla: RVCK-Project#63 -------------------------------- As the ethernet controller of SG2044 and SG2042 only supports RGMII phy. Add phy-mode property to restrict the value. Also, since SG2042 has internal rx delay in its mac, make only "rgmii-txid" and "rgmii-id" valid for phy-mode. Fixes: e281c48 ("dt-bindings: net: sophgo,sg2044-dwmac: Add support for Sophgo SG2042 dwmac") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251114003805.494387-2-inochiama@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> (cherry picked from commit 6b1aa3c) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit db37c6e category: feature bugzilla: RVCK-Project#63 -------------------------------- As the SG2042 has an internal rx delay, the delay should be removed when initializing the mac, otherwise the phy will be misconfigurated. Fixes: 543009e ("net: stmmac: dwmac-sophgo: Add support for Sophgo SG2042 SoC") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Tested-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/20251114003805.494387-4-inochiama@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> (cherry picked from commit db37c6e) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 613f325 category: bugfix bugzilla: RVCK-Project#63 -------------------------------- Sophgo 2044 Root Ports advertise L0 and L1 capabilities without supporting them. Since commit f3ac2ff ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") force enabled ASPM on all device tree platforms, the issue became evident and the SG2044 Root Port started breaking. Hence, disable the L0s and L1 capabilities in the LINKCAP register for the SG2044 Root Ports, so that these states won't get enabled. Fixes: 467d9c0 ("PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> [mani: reworded description and corrected fixes tag] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Tested-by: Han Gao <gaohan@iscas.ac.cn> Link: https://patch.msgid.link/20260109040756.731169-1-inochiama@gmail.com (cherry picked from commit 613f325) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 9e81c52 category: feature bugzilla: RVCK-Project#63 -------------------------------- These boards have a working hardware clock if you put a CR-1220 battery in them. We enable it using information from a 6.1.x vendor kernel. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Michael Orlitzky <michael@orlitzky.com> Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> (cherry picked from commit 9e81c52) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 5e6836e category: cleanup bugzilla: RVCK-Project#63 -------------------------------- As we have a separate CPU dtsi file, move the PLIC and CLINT node to the CPU dtsi file. This will make the sg2042.dtsi focus on peripheral devices, and make the CPU dtsi force CPU related devices. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> (cherry picked from commit 5e6836e) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit ebb87dd category: bugfix bugzilla: RVCK-Project#63 -------------------------------- In sg2042.dtsi, some peripheral device node does not follow the address order. Reorder them in ascending order by address. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> (cherry picked from commit ebb87dd) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 932ec9d category: bugfix bugzilla: RVCK-Project#63 -------------------------------- devm_pm_runtime_enable() is used in the probe, so pm_runtime_disable() should not be called explicitly in the remove function. Fixes: 1c72774 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Tested-by: Chen Wang <unicorn_wang@outlook.com> # on Pioneerbox. Acked-by: Chen Wang <unicorn_wang@outlook.com> Link: https://patch.msgid.link/242eca0ff6601de7966a53706e9950fbcb10aac8.1759169586.git.christophe.jaillet@wanadoo.fr (cherry picked from commit 932ec9d) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 988ef70 category: bugfix bugzilla: RVCK-Project#63 -------------------------------- Since commit f3ac2ff ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") force enables ASPM on all device tree platforms, the SG2042 Root Ports are breaking as they advertise L0s and L1 capabilities without supporting them. Set ASPM quirks to disable the L0s and L1 capabilities for the Root Ports so that these broken link states won't be enabled. Fixes: 4e27aca ("riscv: sophgo: dts: add PCIe controllers for SG2042") Co-developed-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Yao Zi <me@ziyao.cc> [mani: commit log] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Han Gao <gaohan@iscas.ac.cn> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://patch.msgid.link/20260405154154.46829-3-me@ziyao.cc (cherry picked from commit 988ef70) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit c6d5151 category: feature bugzilla: RVCK-Project#63 -------------------------------- Add dma-coherent as an allowed property in the SG2042 PCIe host controller binding. SG2042's PCIe Root Complexes are cache-coherent with the CPU. Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260331171248.973014-2-gaohan@iscas.ac.cn (cherry picked from commit c6d5151) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 2647eab category: feature bugzilla: RVCK-Project#63 -------------------------------- SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent so the kernel uses coherent DMA mappings instead of non-coherent bounce buffering. Cc: stable@vger.kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Link: https://patch.msgid.link/20260331171248.973014-3-gaohan@iscas.ac.cn Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> (cherry picked from commit 2647eab) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 207cbc4 category: feature bugzilla: RVCK-Project#63 -------------------------------- Previous the CPU unit address cpu of sg2044 use decimal, it is not following the general convention for unit addresses of the OF. Convent the unit address to hex to resolve this problem. The introduces a small change for the CPU node name, but it should nothing since there is no direct full-path reference to these CPU nodes. Fixes: 967a94a ("riscv: dts: add initial Sophgo SG2042 SoC device tree") Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Guo Ren <guoren@kernel.org> Link: https://patch.msgid.link/20260426013449.694435-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> (cherry picked from commit 207cbc4) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit a7e6589 category: feature bugzilla: RVCK-Project#63 -------------------------------- Previous the CPU unit address cpu of sg2042 use decimal, it is not following the general convention for unit addresses of the OF. Convent the unit address to hex to resolve this problem. The introduces a small change for the CPU node name, but it should affect nothing since there is no direct full-path reference to these CPU nodes. Fixes: ae5bac3 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox. Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox. Link: https://patch.msgid.link/20260426013449.694435-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> (cherry picked from commit a7e6589) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
mainline inclusion commit 903a936 category: bugfix bugzilla: RVCK-Project#63 -------------------------------- The SG2042 MSI controller has one 32-bit doorbell register, and each bit corresponds to an interrupt. At a glance, it seems that the MSI controller can support 32 interrupts; however the PCI MSI capability only supports 16-bit messages, which makes the high 16 interrupts unusable in such way. Reduce the MSI count to 16 to prevent producing MSI message values that cannot fit 16-bit integers. Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox. Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> (cherry picked from commit 903a936) Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: bugfix bugzilla: RVCK-Project#63 -------------------------------- SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to downstream devices when native port services are enabled. Devices under an affected root port receive zero interrupts despite successful vector allocation, causing driver timeouts (e.g. amdgpu fence fallback timer expired on all rings). Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the port service driver from probing, restoring correct MSI delivery. Fixes: 1c72774 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20260331175658.1015829-3-gaohan@iscas.ac.cn Signed-off-by: Han Gao <gaohan@iscas.ac.cn> (cherry picked from commit c0b2eb44d583088521153282ec7203ba56b889be)
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- The SRD3-10 board has two spiflash. Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn> Link: https://lore.kernel.org/r/20260902-sg2044-dts-v1-1-aa1fd1a4ec0d@iscas.ac.cn Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- Sophgo SG2044 uses eFuses used to store factory-programmed data such as ROM patch, public keys and other factory information. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- Sophgo SoCs such as SG2044 contain eFuses used to store factory-programmed data. As for SG2044, HW automatically loads the eFuse content into shadow registers which are organized as 32bit values exposed as MMIO. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- Add eFUSE controller node for SG2044. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- The SRD3-10-LB variant disables C2C0 Wrapper1 and assigns the full 128 GiB C2C0 window to Wrapper0 for large prefetchable BARs. Add its board compatible with SRD3-10 and SG2044 fallbacks. Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- EDK2 exposes only IO, 32-bit non-prefetchable memory and 64-bit prefetchable memory for each root complex. The existing DTS still describes five older windows with different bases and sizes. Match the current EDK2 windows. Keep Linux PCI domains packed and document their divide-by-two mapping from the sparse EDK2 segments. This also makes 64-bit non-prefetchable BARs fall back below 4 GiB, where standard Type 1 PCIe bridges can forward them. Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
dist inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- Some GPGPU cards require a prefetchable BAR larger than the stock C2C0 layout can provide. Add an SRD3-10-LB variant that disables C2C0 Wrapper1 and assigns the full 128 GiB C2C0 window to Wrapper0. Move its config, IO and Mem32 windows below 4 GiB, matching the corresponding EDK2 platform. Keep the packed Linux PCI domain numbering inherited from SRD3-10. Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
community inclusion category: feature bugzilla: RVCK-Project#63 -------------------------------- Enable the upstream-oriented SG2042 and SG2044 clock, pinctrl, PWM, MSI, PCIe, Ethernet, SPI NOR, hardware monitor, top syscon and eFuse drivers used by the new Sophgo device trees. Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/33628753284 参数解析结果
测试完成 详细结果:
Kunit Test Result[12:18:25] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)
result: Lava check done!
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Contributor
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@RevySR 我尝试做了一个版本，但是替换原先内核后系统启动异常，附件是串口 log，看上去似乎 usb host 工作不太正常，导致了 openEuler 走不下去了。 |
Contributor
Author
旧的启动流是不兼容主线启动的 |
Contributor
请问你说的旧的启动流程具体指的是哪个阶段，是引导阶段还是文件系统（openEuler）？我需要做什么改动才能正常启动？我希望在 review 之前先确保能测试一下。 |
Contributor
Author
请问你说的是什么启动流程? https://github.com/revyos/firmware-sg204x/releases/tag/20260830 |
Contributor
@RevySR：我这里的 Pioneerbox 上安装的 openEuler 是一个 embeded 版本，即采用 linuxboot，然后启动过程中会读取 附件是上电后串口的日志： 1：启动多次，停在 2：出现 “[ 32.218337] watchdog: BUG: soft lockup - CPU#1 stuck for 27s! [swapper/0:1]” |
Contributor
Author
这里请仔细阅读材料 我说的是edk2+dt的形式 然后你选择了非这个信息的镜像
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Summary
Backport the mainline Sophgo SG2042 and SG2044 platform support to RVCK 6.6.
This series replaces the legacy Mango-specific implementation with the
mainline SG2042/SG2044 drivers and device trees. Shared kernel infrastructure
is placed before its platform consumers to keep the patch stack dependency
ordered and bisectable.
Closes #63
Major changes
stmmac, and PHY infrastructure before the corresponding platform drivers.
crashkernel=,high/lowparsingARCH_KEEP_MEMBLOCKsupport when KEXEC is enabledXTheadVector implementations already present in RVCK.
errata_list_vendors.h:ERRATA_THEAD_GHOSTWRITE = 3ERRATA_THEAD_WRITE_ONCE = 4rvck_defconfig.GPIO_DWAPBinto the kernel so the built-in SG2042 GPIO power-keydevice does not remain in deferred probe.
Patch organization
The series is organized in dependency order:
networking prerequisites
All commits use the RVCK inclusion/category/bugzilla commit log format.
Validation
The following builds passed using 24 threads:
A separate configuration with
KEXEC_FILE=yandCRASH_DUMP=yalsosuccessfully built the kernel Image.
The following Sophgo DTBs were generated successfully:
All 27 modified device tree schemas passed
yamllintanddt-doc-validate.The targeted
dt_binding_checkreaches schema generation but is blocked bypre-existing unrelated TH1520, UltraRISC, LRW, and
pincfg-node.yamlschemaerrors in the RVCK tree.
Hardware testing
Basic SG2042 boot testing has been performed. Full hardware validation of
kexec/kdump, GhostWrite reporting, PCIe, and SG2044 peripherals remains to be
completed on Milk-V Pioneer and Sophgo SRD3-10 systems.