From 22f2ac378013592d667f173d3121cb3a5386e12c Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Wed, 30 Sep 2026 12:25:21 +0000 Subject: [PATCH 01/15] fix(registry): dispatch rms_norm to the CUDA backend on CUDA `test_registry_dispatches_rms_norm` asserts that the registry resolves `rms_norm` to `RMSNormCudaOp` whenever CUDA and the compiled kernels are both present, but `OpBackend` had no CUDA member for this operator and the CUDA priority list contained only `PYTORCH_NATIVE_RMS_NORM`, so the assert could never hold. The test therefore fails on any CUDA machine that builds the native extension, and only passes when `_HAS_CUDA_RMSNORM` is false -- which is why an unbuilt CI has not caught it. `RMSNormCudaOp` is already a first-class backend elsewhere: it is the `"cuda"` candidate in `gtest/operator_specs.py` and is used directly by `attention_preprocess.py`. Only the registry was missing it. Add `OpBackend.CUDA_RMS_NORM` and put it ahead of the PyTorch reference in the CUDA priority list. Because `_load_backend` only catches import errors and this module imports cleanly without `_C`, a CUDA-first list would otherwise hand out an op that raises at call time on an unbuilt install; so `RMSNormCudaOp.__init__` now validates the extension and its three symbols, matching `_require_cuda_activation` in the activation ops. The registry already treats a backend whose construction raises as unavailable, so the list degrades to `NativeRMSNormOp` as before. Only the `cuda` priority map changes; rocm/musa/cpu/npu are untouched. Verified on 2x B200 (sm_100, driver 580.126.20, torch 2.13.0+cu130) with the extension rebuilt from source: pytest tests/test_rms_norm.py -q pytest tests/ rl_engine/tests/ -q -p no:randomly \ --ignore=tests/test_rocm_aiter_api_contract.py tests/test_rms_norm.py passes, including test_registry_dispatches_rms_norm, which fails on the merge-base. The full suite gains no failure. The ignored file fails to import on the merge-base as well. Absolute suite counts are reported in the PR description against a named base commit, not here: they shift whenever a sibling test is added, so a count frozen in a commit message goes stale the moment the branch is rebased. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- rl_engine/kernels/ops/cuda/norm/rmsnorm.py | 27 +++++++++++++++++ rl_engine/kernels/registry.py | 6 +++- tests/test_rms_norm.py | 35 ++++++++++++++++++++++ 3 files changed, 67 insertions(+), 1 deletion(-) diff --git a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py index 773325c5d..f7af2a8bc 100644 --- a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py +++ b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py @@ -5,6 +5,25 @@ from rl_engine.kernels.ops.vjp_fp32 import reduce_rows_fp32, rmsnorm_dweight_rows_fp32 +def _require_cuda_symbols(what: str, *names: str) -> None: + """Raise when the compiled kernels backing ``what`` are missing. + + The registry treats a backend whose construction raises as unavailable and + falls through to the next candidate, so calling this from ``__init__`` is + what lets a CUDA-first priority list degrade to the PyTorch reference on a + build without the extension. Mirrors ``_require_cuda_activation`` in the + activation ops. + """ + if not _EXT_AVAILABLE or _C is None: + raise RuntimeError(f"{what} requires the compiled rl_engine._C extension.") + missing = [name for name in names if not hasattr(_C, name)] + if missing: + raise RuntimeError( + f"{what} symbols ({', '.join(missing)}) are not compiled into _C. " + "Rebuild the extension with csrc/cuda/rmsnorm.cu." + ) + + class RMSNormCuda(torch.autograd.Function): """ PyTorch autograd wrapper for CUDA RMSNorm. @@ -99,6 +118,14 @@ class RMSNormCudaOp: backward_impl = "cuda_rmsnorm_dx_declared_fp32_rowfold_dw" + def __init__(self) -> None: + _require_cuda_symbols( + "CUDA RMSNorm", + "rmsnorm_forward", + "rmsnorm_backward_dx", + "rmsnorm_backward_dw", + ) + def __call__(self, x, weight, *, eps=1e-6): return self.forward(x, weight, eps=eps) diff --git a/rl_engine/kernels/registry.py b/rl_engine/kernels/registry.py index 9eeb1c42b..3b935499a 100644 --- a/rl_engine/kernels/registry.py +++ b/rl_engine/kernels/registry.py @@ -154,6 +154,7 @@ class OpBackend(Enum, metaclass=_KernelEnumMeta): ) # RMSNorm(pre-norm / QK-Norm) - pure Pytorch reference(ws1 ground-truth) + CUDA_RMS_NORM = "rl_engine.kernels.ops.cuda.norm.rmsnorm.RMSNormCudaOp" TRITON_RMS_NORM = "rl_engine.kernels.ops.triton.rmsnorm_triton.RMSNormTritonOp" PYTORCH_NATIVE_RMS_NORM = "rl_engine.kernels.ops.pytorch.norm.rms_norm.NativeRMSNormOp" @@ -589,7 +590,10 @@ def __init__(self): OpBackend.TRITON_BATCH_INVARIANT_LOGP, OpBackend.PYTORCH_BATCH_INVARIANT_LOGP, ], - "rms_norm": [OpBackend.PYTORCH_NATIVE_RMS_NORM], + "rms_norm": [ + OpBackend.CUDA_RMS_NORM, + OpBackend.PYTORCH_NATIVE_RMS_NORM, + ], "lm_head": [OpBackend.PYTORCH_NATIVE_LM_HEAD], "embedding": [OpBackend.PYTORCH_NATIVE_EMBEDDING], "silu": [ diff --git a/tests/test_rms_norm.py b/tests/test_rms_norm.py index e8dcaa0a2..cfc12ab68 100644 --- a/tests/test_rms_norm.py +++ b/tests/test_rms_norm.py @@ -247,6 +247,41 @@ def test_backward_batch_invariance_slice(): assert torch.equal(x_slice.grad, grad_x_full_sliced) +# 9b. The CUDA backend must report itself unavailable by failing construction, +# which is the seam the registry uses to fall back (see _get_or_create_backend). +def test_cuda_op_construction_fails_without_extension(monkeypatch): + from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm + + monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", False) + monkeypatch.setattr(cuda_rmsnorm, "_C", None) + with pytest.raises(RuntimeError, match="requires the compiled rl_engine._C extension"): + cuda_rmsnorm.RMSNormCudaOp() + + +def test_cuda_op_construction_fails_when_symbols_missing(monkeypatch): + from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm + + class _WithoutRMSNorm: # a built extension that lacks the rmsnorm symbols + pass + + monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", True) + monkeypatch.setattr(cuda_rmsnorm, "_C", _WithoutRMSNorm()) + with pytest.raises(RuntimeError, match="are not compiled into _C"): + cuda_rmsnorm.RMSNormCudaOp() + + +@requires_cuda +def test_registry_falls_back_to_native_without_extension(monkeypatch): + """A CUDA-first priority list must still resolve on a build without _C.""" + from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm + from rl_engine.kernels.registry import KernelRegistry + + monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", False) + monkeypatch.setattr(cuda_rmsnorm, "_C", None) + # A fresh registry, so the cached instance from other tests is not reused. + assert isinstance(KernelRegistry().get_op("rms_norm"), NativeRMSNormOp) + + # 10. Registry dispatch resolves to the hardware op when available def test_registry_dispatches_rms_norm(): from rl_engine.kernels.registry import kernel_registry From ba9b89e34408671b66a4e10a9e9ced570373358e Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Wed, 30 Sep 2026 18:06:44 +0000 Subject: [PATCH 02/15] fix(norm): validate only used CUDA symbols and exercise explicit fallback Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- rl_engine/kernels/ops/cuda/norm/rmsnorm.py | 1 - tests/test_rms_norm.py | 34 ++++++++++++++++++++-- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py index f7af2a8bc..21be8dfb8 100644 --- a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py +++ b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py @@ -123,7 +123,6 @@ def __init__(self) -> None: "CUDA RMSNorm", "rmsnorm_forward", "rmsnorm_backward_dx", - "rmsnorm_backward_dw", ) def __call__(self, x, weight, *, eps=1e-6): diff --git a/tests/test_rms_norm.py b/tests/test_rms_norm.py index cfc12ab68..0b2a6178f 100644 --- a/tests/test_rms_norm.py +++ b/tests/test_rms_norm.py @@ -270,7 +270,6 @@ class _WithoutRMSNorm: # a built extension that lacks the rmsnorm symbols cuda_rmsnorm.RMSNormCudaOp() -@requires_cuda def test_registry_falls_back_to_native_without_extension(monkeypatch): """A CUDA-first priority list must still resolve on a build without _C.""" from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm @@ -279,7 +278,38 @@ def test_registry_falls_back_to_native_without_extension(monkeypatch): monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", False) monkeypatch.setattr(cuda_rmsnorm, "_C", None) # A fresh registry, so the cached instance from other tests is not reused. - assert isinstance(KernelRegistry().get_op("rms_norm"), NativeRMSNormOp) + assert isinstance(KernelRegistry().get_op("rms_norm", device="cuda"), NativeRMSNormOp) + + +@pytest.mark.parametrize("missing", ["rmsnorm_forward", "rmsnorm_backward_dx"]) +def test_registry_falls_back_when_required_symbol_is_missing(monkeypatch, missing): + from types import SimpleNamespace + + from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm + from rl_engine.kernels.registry import KernelRegistry + + symbols = {name: object() for name in ("rmsnorm_forward", "rmsnorm_backward_dx")} + del symbols[missing] + monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", True) + monkeypatch.setattr(cuda_rmsnorm, "_C", SimpleNamespace(**symbols)) + assert isinstance(KernelRegistry().get_op("rms_norm", device="cuda"), NativeRMSNormOp) + + +def test_registry_cuda_requires_only_used_symbols_and_cpu_stays_native(monkeypatch): + from types import SimpleNamespace + + from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm + from rl_engine.kernels.registry import KernelRegistry + + monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", True) + monkeypatch.setattr( + cuda_rmsnorm, + "_C", + SimpleNamespace(rmsnorm_forward=object(), rmsnorm_backward_dx=object()), + ) + registry = KernelRegistry() + assert isinstance(registry.get_op("rms_norm", device="cuda"), RMSNormCudaOp) + assert isinstance(registry.get_op("rms_norm", device="cpu"), NativeRMSNormOp) # 10. Registry dispatch resolves to the hardware op when available From 1dd6dbb698c35b7e666cda77a8df5b32fb46ca80 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Sun, 4 Oct 2026 01:48:41 +0000 Subject: [PATCH 03/15] test(rmsnorm): gate the dispatch test on the symbols the CUDA op requires Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- tests/test_rms_norm.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/test_rms_norm.py b/tests/test_rms_norm.py index 0b2a6178f..2785ec678 100644 --- a/tests/test_rms_norm.py +++ b/tests/test_rms_norm.py @@ -17,9 +17,10 @@ try: from rl_engine.kernels.ops.base import _C, _EXT_AVAILABLE + # The same two symbols RMSNormCudaOp.__init__ requires; a build that has them + # dispatches to the CUDA op, so the dispatch test must agree with that guard. _HAS_CUDA_RMSNORM = _EXT_AVAILABLE and all( - hasattr(_C, name) - for name in ("rmsnorm_forward", "rmsnorm_backward_dx", "rmsnorm_backward_dw") + hasattr(_C, name) for name in ("rmsnorm_forward", "rmsnorm_backward_dx") ) except ImportError: # pragma: no cover - import can fail when the extension is not built. _HAS_CUDA_RMSNORM = False From 6a4f07818c75b14af84c7a8b7ed45aaa99a69659 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Sun, 4 Oct 2026 12:51:23 +0000 Subject: [PATCH 04/15] fix(rmsnorm): guard the CUDA launchers on the input's device The forward, backward-dx and both backward-dw launchers took the current CUDA stream without switching to the input's device, so a tensor on cuda:1 while cuda:0 is current launched on the wrong GPU. Add a device guard on the input's device in each launcher. Use at::cuda::OptionalCUDAGuard with the headers included unconditionally, as activation.cu does: those launchers compile in the ROCm build too, where the file's existing c10::cuda::CUDAGuard stays inside the !USE_ROCM block. A two-device test checks that the op runs on the input's device and matches the single-device result. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- csrc/cuda/rmsnorm.cu | 8 ++++++-- tests/test_rms_norm.py | 27 +++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/csrc/cuda/rmsnorm.cu b/csrc/cuda/rmsnorm.cu index 1adaca5bd..b32bc5af4 100644 --- a/csrc/cuda/rmsnorm.cu +++ b/csrc/cuda/rmsnorm.cu @@ -1,9 +1,7 @@ #include #include -#if !defined(USE_ROCM) #include #include -#endif #include #include #include @@ -251,6 +249,9 @@ void rmsnorm_forward_cuda( torch::Tensor rstd, double eps ) { + // Launch on x's device: the current CUDA stream belongs to the current + // device, which need not be x's. + const at::cuda::OptionalCUDAGuard device_guard(device_of(x)); int T = x.size(0); int H = x.size(1); int threads = choose_threads(H); @@ -283,6 +284,7 @@ void rmsnorm_backward_dx_cuda( torch::Tensor rstd, torch::Tensor dx ) { + const at::cuda::OptionalCUDAGuard device_guard(device_of(x)); int T = x.size(0); int H = x.size(1); int threads = choose_threads(H); @@ -315,6 +317,7 @@ void rmsnorm_backward_partial_dw_cuda( torch::Tensor mask, torch::Tensor partial_dw ) { + const at::cuda::OptionalCUDAGuard device_guard(device_of(x)); int T = x.size(0); int H = x.size(1); @@ -342,6 +345,7 @@ void rmsnorm_backward_reduce_dw_cuda( torch::Tensor partial_dw, torch::Tensor dw ) { + const at::cuda::OptionalCUDAGuard device_guard(device_of(partial_dw)); int chunks = partial_dw.size(0); int H = partial_dw.size(1); diff --git a/tests/test_rms_norm.py b/tests/test_rms_norm.py index 2785ec678..b17a3f302 100644 --- a/tests/test_rms_norm.py +++ b/tests/test_rms_norm.py @@ -379,6 +379,33 @@ def test_cuda_triton_rms_norm_matches_native_forward_and_backward(impl, dtype, r ) +@requires_cuda_rmsnorm +@pytest.mark.skipif(torch.cuda.device_count() < 2, reason="requires at least two CUDA devices") +def test_cuda_rms_norm_runs_on_the_input_device_not_the_current_one(): + # The launchers take the current CUDA stream, which belongs to the current + # device; they must switch to x's device first or a cuda:1 input while + # cuda:0 is current launches on the wrong GPU. + torch.manual_seed(0) + x_cpu = torch.randn(8, 768, dtype=torch.float32) + w_cpu = torch.randn(768, dtype=torch.float32) + dy_cpu = torch.randn(8, 768, dtype=torch.float32) + + def run(device): + x = x_cpu.to(device=device, dtype=torch.bfloat16).requires_grad_(True) + w = w_cpu.to(device=device, dtype=torch.bfloat16).requires_grad_(True) + y = rmsnorm_cuda(x, w, eps=_EPS) + y.backward(dy_cpu.to(device=device, dtype=torch.bfloat16)) + torch.cuda.synchronize(device) + return y.detach(), x.grad.detach(), w.grad.detach() + + with torch.cuda.device(0): + expected = run("cuda:0") + actual = run("cuda:1") + for got, want in zip(actual, expected, strict=True): + assert got.device == torch.device("cuda:1") + assert torch.equal(got.cpu(), want.cpu()) + + @requires_cuda @pytest.mark.parametrize("impl", ["triton", "cuda"]) def test_cuda_triton_rms_norm_deterministic_repeat(impl): From 6741d16505b6c40c8abab3c91d887af8d3f76baf Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Wed, 30 Sep 2026 14:03:12 +0000 Subject: [PATCH 05/15] feat(ws1): Qwen3-Next RMSNorm references and zero-centred CUDA offset Advances RFC #428 C1 on the CUDA track. Claim level: L0 repeatable and L1 batch-invariant. L2 is NOT claimed -- see "On exactness against vLLM" below. Qwen3-Next's decoder and final norms store a zero-centred weight and compute `x * rstd * (1 + w)`, with the `1 +` applied in fp32 after the upcast. Folding it into a bf16 weight beforehand rounds the offset away, so it has to reach the kernel as a parameter rather than being pre-applied by the caller. NativeRMSNormOp gains `weight_offset` (default 0.0) Qwen3NextRMSNormOp subclasses it, overriding only weight_offset = 1.0 Qwen3NextRMSNormGatedOp GDN gated norm: plain w, weight multiply in fp32 Qwen3NextRMSNormGatedHFOp the transformers convention, kept as a witness The offset is applied under `if cls.weight_offset:` rather than unconditionally, because `0.0 + w` rewrites -0.0 to +0.0. torch.equal does not notice that, but a bitwise comparison does, and the plain path must stay bit-for-bit what it was. A test pins it at the bit level. The gated pair exists because transformers and vLLM disagree on where the gated norm's weight multiply happens, and the gap is not a ULP: on bf16 / head_v_dim=128 they differ in 35% of elements with max|diff| = 6.25e-2. Isolating the cast order alone reproduces the gap (5.3e-2), so the cast order dominates rather than the reduction order. The two conventions share their validation and normalization and differ only in a `_scale_by_weight` hook. CUDA: `weight_offset` added to the forward and dx kernels, defaulting to 0.0 so every existing caller and binding is unaffected. The dw kernel is untouched: d/dw (offset + w) == d/dw w. weight_offset=1.0 vs an explicit fp32 (1 + w) weight bitwise equal weight_offset=1.0 vs a bf16-folded (1 + w) weight differs, as required default offset vs the previous kernel bitwise equal The first line is the correctness argument: the in-kernel offset is the same arithmetic as the fp32 reference, not an approximation. The second is a regression guard -- if it ever passes, the offset has stopped being fp32. On exactness against vLLM ------------------------- Measured over 40 seeds (bf16, head_v_dim=128, 512 rows): ours vs forward_native 6/40 seeds differ, worst 1.56e-2 ours vs forward_cuda 18/40 seeds differ, worst 3.91e-3 forward_native vs forward_cuda 21/40 seeds differ, worst 1.56e-2 vLLM's own two paths are not bitwise equal to each other, so "bitwise equal to vLLM" is undefined until a single provider is named. In fp32 the two paths differ on ~36% of elements, every one by an fp32 ULP -- the tree shapes differ, the semantics do not. What this reproduces is the convention (fp32 weight multiply, single trailing cast); the residual is the reduction tree. The reduction stays the repo's fixed 32-wide chunked sum, which is what buys L1. It was introduced for NPU but is needed on CUDA too: over 20 seeds at H=2048 in bf16 -- Qwen3-Next's own hidden_size and dtype -- a plain mean(-1) broke slice invariance on 1 of 20 while the chunked reduction broke on 0 of 20. Matching stock vLLM bitwise would mean adopting a reduction that is not itself batch-invariant, i.e. trading L1 for L2. tests/check_qwen3_next_norm_providers.py pins the dispatch facts and bounds the gap, asserting magnitudes rather than equality so a vLLM bump that changes the provider fails loudly. It is named `check_` rather than `test_`, following tests/distributed/check_*.py: it imports real vLLM, and tests/test_framework_operator_integrations.py asserts vllm is absent from sys.modules, an invariant any collected test importing vLLM would break for the whole session. Also: `rl_engine/_C.pyi` updated for the new `weight_offset` argument (CI runs mypy against it), `tests/test_qwen3_next_norm.py` added to the CI test list in .github/workflows/ci.yml, and an operator page added per docs/operators/README.md ("the documentation page is part of the operator contract"). Verified on 2x B200 (sm_100, driver 580.126.20, torch 2.13.0+cu130, triton 3.7.1, vllm 0.30.0, transformers 5.17.0): pytest tests/test_qwen3_next_norm.py -q pytest tests/check_qwen3_next_norm_providers.py -q pytest tests/ rl_engine/tests/ -q -p no:randomly \ --ignore=tests/test_rocm_aiter_api_contract.py Both new files pass and the full suite gains no failure. The ignored file fails to import on the merge-base as well. Absolute suite counts are reported in the PR description against a named base commit, not here: they shift whenever a sibling test is added, so a count frozen in a commit message goes stale the moment the branch is rebased. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- .github/workflows/ci.yml | 2 +- csrc/cuda/rmsnorm.cu | 29 +- csrc/ops.cpp | 24 +- docs/.nav.yml | 1 + docs/operators/README.md | 1 + docs/operators/qwen3-next-rms-norm.md | 103 ++++ rl_engine/_C.pyi | 2 + rl_engine/kernels/ops/cuda/norm/rmsnorm.py | 37 +- .../ops/pytorch/norm/qwen3_next_rms_norm.py | 198 +++++++ .../kernels/ops/pytorch/norm/rms_norm.py | 30 +- tests/check_qwen3_next_norm_providers.py | 232 ++++++++ tests/test_qwen3_next_norm.py | 502 ++++++++++++++++++ 12 files changed, 1127 insertions(+), 34 deletions(-) create mode 100644 docs/operators/qwen3-next-rms-norm.md create mode 100644 rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py create mode 100644 tests/check_qwen3_next_norm_providers.py create mode 100644 tests/test_qwen3_next_norm.py diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 75627621e..5f8c900b3 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -67,7 +67,7 @@ jobs: run: | python -m pytest rl_engine/tests/test_dispatch.py -v PYTEST_DISABLE_PLUGIN_AUTOLOAD=1 python -m pytest tests/test_attention_correctness.py -q -rs - python -m pytest tests/test_forward_invariance.py tests/test_tolerance_contract.py tests/test_ws1_workload.py tests/test_gradient_invariance.py tests/test_elementwise_inventory.py tests/test_four_judgment_matrix.py tests/test_op_checks.py tests/test_operator_inputs.py tests/test_profiler.py tests/test_kv_consistency.py tests/test_ws1_qwen3_dense.py tests/test_ws1_chain_integration.py -q + python -m pytest tests/test_forward_invariance.py tests/test_tolerance_contract.py tests/test_ws1_workload.py tests/test_gradient_invariance.py tests/test_elementwise_inventory.py tests/test_four_judgment_matrix.py tests/test_op_checks.py tests/test_operator_inputs.py tests/test_profiler.py tests/test_kv_consistency.py tests/test_ws1_qwen3_dense.py tests/test_ws1_chain_integration.py tests/test_qwen3_next_norm.py -q - name: Run Cross-Configuration Contract Tests (CPU-safe) run: | diff --git a/csrc/cuda/rmsnorm.cu b/csrc/cuda/rmsnorm.cu index b32bc5af4..fc6c425d6 100644 --- a/csrc/cuda/rmsnorm.cu +++ b/csrc/cuda/rmsnorm.cu @@ -108,7 +108,8 @@ __global__ void rmsnorm_fwd_kernel( float* __restrict__ rstd, int T, int H, - float eps + float eps, + float weight_offset ) { int row = blockIdx.x; int tid = threadIdx.x; @@ -135,10 +136,13 @@ __global__ void rmsnorm_fwd_kernel( __syncthreads(); - // Write y = x * rstd * weight. + // Write y = x * rstd * (weight_offset + weight). The offset is added in + // fp32 after the upcast: a zero-centred weight (Qwen3-Next, Gemma) must not + // have its "+1" folded into the low-precision weight beforehand, which would + // round the offset and break the bitwise contract. for (int col = tid; col < H; col += blockDim.x) { float xv = load_as_float(x_row + col); - float wv = load_as_float(weight + col); + float wv = load_as_float(weight + col) + weight_offset; float out = xv * row_rstd * wv; store_from_float(y_row + col, out); } @@ -153,7 +157,8 @@ __global__ void rmsnorm_bwd_dx_kernel( const float* __restrict__ rstd, scalar_t* __restrict__ dx, int T, - int H + int H, + float weight_offset ) { int row = blockIdx.x; int tid = threadIdx.x; @@ -167,7 +172,7 @@ __global__ void rmsnorm_bwd_dx_kernel( for (int col = tid; col < H; col += blockDim.x) { float dyv = load_as_float(dy_row + col); float xv = load_as_float(x_row + col); - float wv = load_as_float(weight + col); + float wv = load_as_float(weight + col) + weight_offset; local_dot += dyv * wv * xv; } @@ -179,7 +184,7 @@ __global__ void rmsnorm_bwd_dx_kernel( for (int col = tid; col < H; col += blockDim.x) { float dyv = load_as_float(dy_row + col); float xv = load_as_float(x_row + col); - float wv = load_as_float(weight + col); + float wv = load_as_float(weight + col) + weight_offset; float out = r * dyv * wv - xv * coeff; store_from_float(dx_row + col, out); @@ -247,7 +252,8 @@ void rmsnorm_forward_cuda( torch::Tensor weight, torch::Tensor y, torch::Tensor rstd, - double eps + double eps, + double weight_offset ) { // Launch on x's device: the current CUDA stream belongs to the current // device, which need not be x's. @@ -270,7 +276,8 @@ void rmsnorm_forward_cuda( rstd.data_ptr(), T, H, - static_cast(eps) + static_cast(eps), + static_cast(weight_offset) ); }); }); @@ -282,7 +289,8 @@ void rmsnorm_backward_dx_cuda( torch::Tensor x, torch::Tensor weight, torch::Tensor rstd, - torch::Tensor dx + torch::Tensor dx, + double weight_offset ) { const at::cuda::OptionalCUDAGuard device_guard(device_of(x)); int T = x.size(0); @@ -303,7 +311,8 @@ void rmsnorm_backward_dx_cuda( rstd.data_ptr(), dx.data_ptr(), T, - H + H, + static_cast(weight_offset) ); }); }); diff --git a/csrc/ops.cpp b/csrc/ops.cpp index 11fda1159..4e786e5b3 100644 --- a/csrc/ops.cpp +++ b/csrc/ops.cpp @@ -260,14 +260,16 @@ void rmsnorm_forward_cuda( torch::Tensor weight, torch::Tensor y, torch::Tensor rstd, - double eps); + double eps, + double weight_offset); void rmsnorm_backward_dx_cuda( torch::Tensor dy, torch::Tensor x, torch::Tensor weight, torch::Tensor rstd, - torch::Tensor dx); + torch::Tensor dx, + double weight_offset); void rmsnorm_backward_partial_dw_cuda( torch::Tensor dy, @@ -296,7 +298,8 @@ static void rmsnorm_check_input(const torch::Tensor& x, const char* name) { std::vector rmsnorm_forward( torch::Tensor x, torch::Tensor weight, - double eps) + double eps, + double weight_offset) { rmsnorm_check_input(x, "x"); rmsnorm_check_input(weight, "weight"); @@ -309,7 +312,7 @@ std::vector rmsnorm_forward( auto y = torch::empty_like(x); auto rstd = torch::empty({T}, x.options().dtype(torch::kFloat32)); - rmsnorm_forward_cuda(x, weight, y, rstd, eps); + rmsnorm_forward_cuda(x, weight, y, rstd, eps, weight_offset); return {y, rstd}; } @@ -318,7 +321,8 @@ torch::Tensor rmsnorm_backward_dx( torch::Tensor dy, torch::Tensor x, torch::Tensor weight, - torch::Tensor rstd) + torch::Tensor rstd, + double weight_offset) { rmsnorm_check_input(dy, "dy"); rmsnorm_check_input(x, "x"); @@ -333,7 +337,7 @@ torch::Tensor rmsnorm_backward_dx( auto dx = torch::empty_like(x); - rmsnorm_backward_dx_cuda(dy, x, weight, rstd, dx); + rmsnorm_backward_dx_cuda(dy, x, weight, rstd, dx, weight_offset); return dx; } @@ -712,8 +716,12 @@ PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) { &det_gemm_db_transposed, "Batch-invariant deterministic GEMM backward in canonical [N,K] layout"); // registry RMSNorm - m.def("rmsnorm_forward", &rmsnorm_forward, "Batch-invariant RMSNorm forward CUDA"); - m.def("rmsnorm_backward_dx", &rmsnorm_backward_dx, "Batch-invariant RMSNorm backward dx CUDA"); + m.def("rmsnorm_forward", &rmsnorm_forward, "Batch-invariant RMSNorm forward CUDA", + py::arg("x"), py::arg("weight"), py::arg("eps"), + py::arg("weight_offset") = 0.0); + m.def("rmsnorm_backward_dx", &rmsnorm_backward_dx, "Batch-invariant RMSNorm backward dx CUDA", + py::arg("dy"), py::arg("x"), py::arg("weight"), py::arg("rstd"), + py::arg("weight_offset") = 0.0); m.def("rmsnorm_backward_dw", &rmsnorm_backward_dw, "Deterministic RMSNorm backward dweight CUDA"); #if !defined(USE_ROCM) m.def( diff --git a/docs/.nav.yml b/docs/.nav.yml index 7d71230a3..9133710de 100644 --- a/docs/.nav.yml +++ b/docs/.nav.yml @@ -29,6 +29,7 @@ nav: - operators/sampling.md - operators/det-gemm.md - operators/embedding.md + - operators/qwen3-next-rms-norm.md - Developer Guide: - contributing/README.md - General: diff --git a/docs/operators/README.md b/docs/operators/README.md index 00f4cbb45..0d955ed18 100644 --- a/docs/operators/README.md +++ b/docs/operators/README.md @@ -32,4 +32,5 @@ Every operator page should include: - [Matmul](matmul.md) - [Sampling](sampling.md) - [Token Embedding](embedding.md) +- [Qwen3-Next RMSNorm (zero-centred)](qwen3-next-rms-norm.md) - [Operator Doc Template](../contributing/operator-doc-template.md) diff --git a/docs/operators/qwen3-next-rms-norm.md b/docs/operators/qwen3-next-rms-norm.md new file mode 100644 index 000000000..292139bea --- /dev/null +++ b/docs/operators/qwen3-next-rms-norm.md @@ -0,0 +1,103 @@ +# Qwen3-Next RMSNorm (zero-centred) + +## Summary + +Qwen3-Next's decoder and final norms store a **zero-centred** weight and compute +`x * rstd * (1 + w)` rather than `x * rstd * w`. The `1 +` is applied in fp32, +after the upcast — folding it into a low-precision weight beforehand rounds the +offset away and silently breaks any bitwise claim. + +This operator exists for RFC #428 C1 (Embedding / RMSNorm / residual / final norm +exactness) on the Qwen3-Next rollout-vs-replay path. The Gated DeltaNet block uses +a *different* weight convention and a different cast order; it is a separate +operator. + +Upstream references: `transformers` `Qwen3NextRMSNorm`, and vLLM's `GemmaRMSNorm`, +which `vllm/model_executor/models/qwen3_next.py` aliases as `Qwen3NextRMSNorm`. + +## Entry Point + +```python +from rl_engine.kernels.ops.pytorch.norm.qwen3_next_rms_norm import Qwen3NextRMSNormOp +from rl_engine.kernels.ops.cuda.norm.rmsnorm import Qwen3NextRMSNormCudaOp, rmsnorm_cuda + +y = Qwen3NextRMSNormOp().forward(x, weight, eps=1e-6) # reference +y = Qwen3NextRMSNormCudaOp().forward(x, weight, eps=1e-6) # CUDA + +# The offset is a kernel parameter, not a pre-pass: +y = rmsnorm_cuda(x, weight, eps=1e-6, weight_offset=1.0) +``` + +## Backends + +| Backend | Wrapper | Native symbol | Status | +| --- | --- | --- | --- | +| CUDA | `Qwen3NextRMSNormCudaOp` | `rl_engine._C.rmsnorm_forward` (`weight_offset=1.0`) | Supported | +| ROCm | — | — | Not implemented | +| PyTorch fallback | `Qwen3NextRMSNormOp` | — | Supported (WS1 gold) | + +`Qwen3NextRMSNormOp` subclasses `NativeRMSNormOp` and overrides only +`weight_offset`; the base applies it in fp32. + +## Tensor Contract + +| Argument | Shape | Dtype | Requirements | +| --- | --- | --- | --- | +| `x` | `[..., H]` | fp32 / bf16 / fp16 | CUDA path requires contiguous | +| `weight` | `[H]` | matches `x` | zero-centred (upstream inits to zeros) | +| `eps` | scalar | float | inside the sqrt; `1e-6` for Qwen3-Next | + +## Dispatch Behavior + +Registered as the `qwen3_next_rms_norm` gtest operator. On CUDA the registry +prefers `Qwen3NextRMSNormCudaOp`; every other platform resolves to the PyTorch +reference. The CUDA op validates the compiled symbols in `__init__`, so on a build +without the extension construction raises and the registry falls through to the +reference rather than handing out an op that fails at call time. + +## Accuracy + +Claim level: **L0 repeatable, L1 batch-invariant**. L2 is not claimed. + +The reduction is the repo's fixed 32-wide chunked sum +(`shape_invariant_rstd`), which is what makes a row's result independent of the +batch layout. It deliberately differs from upstream's `mean(-1)`: measured on B200, +over 20 seeds at `H=2048` in bf16, a plain `mean(-1)` broke slice invariance on 1 +of 20 while the chunked reduction broke on 0 of 20. + +The cost is that the decoder norm is **not** bitwise equal to stock vLLM — 7 +elements of 1048576 differ, `max|diff| = 1.56e-2` in bf16 at `H=2048`. That gap is +inherent: matching stock vLLM bitwise would mean adopting a reduction that is not +itself batch-invariant, i.e. trading L1 for L2. + +The in-kernel offset is exact, not an approximation: `weight_offset=1.0` is bitwise +equal to passing an explicit fp32 `1 + w` weight, and differs from a bf16-folded +`1 + w`, both asserted. + +Tolerances come from `tolerance_contract.json` (`reduction` × dtype); no private +thresholds. + +## Performance Notes + +The CUDA path reuses the existing `rmsnorm_fwd_kernel` reduction +(`block_reduce_sum` over `choose_threads(H)`), so the offset costs one fp32 add per +element and no extra memory traffic. + +```bash +python scripts/check_operator.py --op qwen3_next_rms_norm --candidate cuda \ + --device cuda --dtype bf16 --check-grad +``` + +## Tests + +```bash +python -m pytest tests/test_qwen3_next_norm.py -v +``` + +## Known Limitations + +- CUDA only; no ROCm, Ascend or Triton backend. +- Not bitwise against stock vLLM (see Accuracy); an L2 claim needs the strict + provider on both sides, per RFC #428 §1 item 1. +- Measured on sm_100 (B200). Per RFC #428 §2.2 no claim carries across + H100/H200/B100/B200. diff --git a/rl_engine/_C.pyi b/rl_engine/_C.pyi index fb3c4379c..b911feaf7 100644 --- a/rl_engine/_C.pyi +++ b/rl_engine/_C.pyi @@ -260,12 +260,14 @@ def rmsnorm_forward( x: torch.Tensor, weight: torch.Tensor, eps: float, + weight_offset: float = ..., ) -> list[torch.Tensor]: ... def rmsnorm_backward_dx( dy: torch.Tensor, x: torch.Tensor, weight: torch.Tensor, rstd: torch.Tensor, + weight_offset: float = ..., ) -> torch.Tensor: ... def rmsnorm_backward_dw( dy: torch.Tensor, diff --git a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py index 21be8dfb8..3b72e497d 100644 --- a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py +++ b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py @@ -30,16 +30,18 @@ class RMSNormCuda(torch.autograd.Function): """ @staticmethod - def forward(ctx, x, weight, mask=None, eps=1e-6): + def forward(ctx, x, weight, mask=None, eps=1e-6, weight_offset=0.0): """ Forward: - y = x * rsqrt(mean(x^2) + eps) * weight + y = x * rsqrt(mean(x^2) + eps) * (weight_offset + weight) Input: x: [T, H], fp16/bf16/fp32 CUDA tensor weight: [H], fp16/bf16/fp32 CUDA tensor mask: [T], bool CUDA tensor eps: float + weight_offset: float, added to weight in fp32 inside the kernel. + 1.0 selects the zero-centred (1 + w) convention. Output: y: [T, H] @@ -64,10 +66,11 @@ def forward(ctx, x, weight, mask=None, eps=1e-6): assert mask.dim() == 1, "mask must be [T]" assert mask.shape[0] == x.shape[0], "mask length mismatch" - y, rstd = _C.rmsnorm_forward(x, weight, float(eps)) + y, rstd = _C.rmsnorm_forward(x, weight, float(eps), float(weight_offset)) ctx.save_for_backward(x, weight, rstd, mask) ctx.eps = eps + ctx.weight_offset = float(weight_offset) return y @@ -81,7 +84,7 @@ def backward(ctx, grad_out): x, weight, rstd, mask = ctx.saved_tensors dy = grad_out.contiguous() - dx = _C.rmsnorm_backward_dx(dy, x, weight, rstd) + dx = _C.rmsnorm_backward_dx(dy, x, weight, rstd, ctx.weight_offset) # The shape-independent FP32 left fold preserves the C2 Batch/Chunk # reduction order while the CUDA reducer executes it in one launch. @@ -101,16 +104,18 @@ def backward(ctx, grad_out): family="cuda", ) - return dx, dw, None, None + # dw is unchanged by the offset: d/dw (offset + w) == d/dw w. + return dx, dw, None, None, None -def rmsnorm_cuda(x, weight, eps=1e-6, mask=None): +def rmsnorm_cuda(x, weight, eps=1e-6, mask=None, weight_offset=0.0): """ use: y = rmsnorm_cuda(x, weight) y = rmsnorm_cuda(x, weight, mask=mask) + y = rmsnorm_cuda(x, weight, weight_offset=1.0) # zero-centred weight """ - return RMSNormCuda.apply(x, weight, mask, eps) + return RMSNormCuda.apply(x, weight, mask, eps, weight_offset) class RMSNormCudaOp: @@ -124,6 +129,9 @@ def __init__(self) -> None: "rmsnorm_forward", "rmsnorm_backward_dx", ) + #: Added to the weight in fp32 inside the kernel. Subclasses override it; + #: 0.0 is the plain convention. + weight_offset = 0.0 def __call__(self, x, weight, *, eps=1e-6): return self.forward(x, weight, eps=eps) @@ -131,7 +139,9 @@ def __call__(self, x, weight, *, eps=1e-6): def forward(self, x, weight, *, eps=1e-6): hidden = x.shape[-1] x_2d = x.contiguous().view(-1, hidden) - y_2d = rmsnorm_cuda(x_2d, weight.contiguous(), eps=eps) + y_2d = rmsnorm_cuda( + x_2d, weight.contiguous(), eps=eps, weight_offset=self.weight_offset + ) return y_2d.view_as(x) def parameter_vjp_contributions_fp32(self, *, x, weight, grad_output, eps=1e-6): @@ -140,3 +150,14 @@ def parameter_vjp_contributions_fp32(self, *, x, weight, grad_output, eps=1e-6): rstd = torch.rsqrt(x32.square().mean(dim=-1) + float(eps)) rows = grad_output.float() * x32 * rstd.unsqueeze(-1) return {"weight": rows} + + +class Qwen3NextRMSNormCudaOp(RMSNormCudaOp): + """Zero-centred CUDA RMSNorm: ``y = x * rstd * (1 + weight)``. + + The decoder and final norms of Qwen3-Next (and Gemma) store a zero-centred + weight. The ``+1`` is applied inside the kernel after the fp32 upcast, so it + is never rounded through the low-precision weight dtype. + """ + + weight_offset = 1.0 diff --git a/rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py b/rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py new file mode 100644 index 000000000..5261245d0 --- /dev/null +++ b/rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2026 RL-Kernel Contributors + +"""Qwen3-Next RMSNorm references (WS1 ground truth for RFC #428 C1). + +Qwen3-Next ships two RMSNorm conventions that differ both in how the weight is +applied and in where the dtype casts sit. They are kept as separate operators +because the cast order is part of the contract, not a flag: + +``Qwen3NextRMSNorm`` (decoder / final norm) + normalize in fp32, scale by ``(1 + weight)`` in fp32, cast once at the end. + The stored weight is zero-centred, so the ``1 +`` offset MUST be applied + after the fp32 upcast -- folding it into a bf16 weight first rounds the + offset and silently breaks the bitwise claim. + +``Qwen3NextRMSNormGated`` (inside the Gated DeltaNet block) + normalize in fp32, scale by a plain (non zero-centred) weight, then gate by + ``silu(gate)``. Where the weight multiply happens is NOT agreed upstream -- + see below -- so it is an explicit part of the operator identity here. + +Divergence at the gated-norm boundary (measured) +------------------------------------------------- +``transformers`` and vLLM do not agree on the gated variant: + +* vLLM (``RMSNormGated``, both ``forward_native`` and the FLA Triton + ``forward_cuda``) keeps the normalized value in fp32 for the weight multiply. +* ``transformers`` (``Qwen3NextRMSNormGated``) casts the normalized value back + to the input dtype *before* the weight multiply. + +On B200 / bf16 / ``head_v_dim=128`` these differ in 35% of elements with +``max|diff| = 6.25e-2``; swapping only the cast order reproduces the gap +(``5.3e-2``), so the cast order -- not the reduction order -- dominates. Because +RFC #428 claims L2 exactness against **vLLM rollout**, the fp32 multiply is the +strict default; the transformers convention is kept as a named witness so the +divergence stays testable instead of being silently picked. + +What "agrees with vLLM" means here, precisely +---------------------------------------------- +Only the *convention* is reproduced, not the bits. vLLM's own two paths are not +bitwise equal to each other: over 40 seeds (bf16, ``head_v_dim=128``, 512 rows), +``forward_native`` and ``forward_cuda`` disagreed on 21, worst +``max|diff| = 1.56e-2``. Against this operator the figures were 6/40 and 18/40. +So "bitwise equal to vLLM" is undefined until a single provider is named, and +this operator does not claim it -- see the reduction-order note below. + +Both reuse :func:`shape_invariant_rstd` so the reduction order -- and hence the +result -- never depends on the batch layout (RFC #428 section 6, item 2). The +reduction order therefore deliberately differs from upstream's ``mean(-1)``; +what is reproduced exactly is the weight convention and the cast order. + +Why the chunked reduction is kept on CUDA too +--------------------------------------------- +:func:`shape_invariant_rstd` was introduced for NPU, where ``mean``/``sum`` pick +shape-dependent kernels. Measured on B200 (sm_100) it is needed on CUDA as well: +over 20 seeds at ``H=2048`` in bf16 -- Qwen3-Next's own ``hidden_size`` and dtype +-- a plain ``mean(-1)`` broke slice invariance (``rstd(x[3:5]) != rstd(x)[3:5]``) +on 1 of 20, while the chunked reduction broke on 0 of 20. Failures were also seen +at ``H=5120`` in fp32. + +The cost is that the decoder norm is NOT bitwise equal to stock vLLM: 7 elements +of 1048576 differ (``max|diff| = 1.56e-2``, bf16, H=2048). That gap is inherent -- +matching stock vLLM bitwise would mean adopting a reduction that is itself not +batch-invariant, i.e. trading L1 for L2. These operators therefore claim L0 and L1 +only; an L2 claim needs the strict provider on both sides, per RFC #428 section 1, +item 1. +""" + +from __future__ import annotations + +import torch +import torch.nn.functional as F + +from rl_engine.kernels.ops.pytorch.norm.rms_norm import ( + NativeRMSNormOp, + check_norm_weight, + shape_invariant_rstd, +) + +__all__ = [ + "Qwen3NextRMSNormOp", + "Qwen3NextRMSNormGatedOp", + "Qwen3NextRMSNormGatedHFOp", +] + + +class Qwen3NextRMSNormOp(NativeRMSNormOp): + """Zero-centred RMSNorm: ``out = x * rstd * (1 + weight)``. + + Only the weight convention differs from :class:`NativeRMSNormOp`, so that is + all this overrides. The base applies the offset in fp32, after the upcast, + which is what ``transformers`` and vLLM both do -- folding ``1 +`` into a + bf16 weight beforehand would round the offset away. + """ + + weight_offset = 1.0 + + +class Qwen3NextRMSNormGatedOp: + """Gated RMSNorm used by the Gated DeltaNet block (vLLM/strict convention). + + ``out = (x * rstd * weight) * silu(gate)``, with every multiply in fp32 and + a single cast on the way out. This is the convention vLLM's ``RMSNormGated`` + uses with ``norm_before_gate=True``, which is what the RFC #428 L2 claim is + measured against. + + Not a subclass of the plain op: it takes an extra tensor and its epilogue + differs, so it is not a drop-in substitute for one. + + The weight is plain, NOT zero-centred -- upstream initializes it to ones. + """ + + def __call__( + self, + x: torch.Tensor, + weight: torch.Tensor, + gate: torch.Tensor, + *, + eps: float = 1e-6, + ) -> torch.Tensor: + return self.forward(x, weight, gate, eps=eps) + + def forward( + self, + x: torch.Tensor, + weight: torch.Tensor, + gate: torch.Tensor, + *, + eps: float = 1e-6, + ) -> torch.Tensor: + return self._rms_norm_gated(x, weight, gate, eps=eps, output_dtype=x.dtype) + + def forward_fp32( + self, + x: torch.Tensor, + weight: torch.Tensor, + gate: torch.Tensor, + *, + eps: float = 1e-6, + ) -> torch.Tensor: + """Ground-truth: fp32 in, fp32 out.""" + return self._rms_norm_gated(x, weight, gate, eps=eps, output_dtype=torch.float32) + + # ------------------------------------------------------------------ # + # Shared by both conventions; only `_scale_by_weight` differs. + # ------------------------------------------------------------------ # + @staticmethod + def _normalized( + x: torch.Tensor, weight: torch.Tensor, gate: torch.Tensor, *, eps: float + ) -> torch.Tensor: + check_norm_weight(x, weight) + if gate.shape != x.shape: + raise ValueError( + f"gate must match x, got tuple(gate.shape)={tuple(gate.shape)} " + f"vs tuple(x.shape)={tuple(x.shape)}" + ) + x_f = x.float() + rstd = shape_invariant_rstd(x_f, float(eps)).unsqueeze(-1) + return x_f * rstd + + @staticmethod + def _scale_by_weight( + normed: torch.Tensor, weight: torch.Tensor, input_dtype: torch.dtype + ) -> torch.Tensor: + """vLLM: the weight multiply stays in fp32.""" + del input_dtype + return normed * weight.float() + + @classmethod + def _rms_norm_gated( + cls, + x: torch.Tensor, + weight: torch.Tensor, + gate: torch.Tensor, + *, + eps: float, + output_dtype: torch.dtype, + ) -> torch.Tensor: + normed = cls._normalized(x, weight, gate, eps=eps) + scaled = cls._scale_by_weight(normed, weight, x.dtype) + # The gate activation is evaluated in fp32 and promotes the product. + gated = scaled * F.silu(gate.float()) + return gated.to(output_dtype) + + +class Qwen3NextRMSNormGatedHFOp(Qwen3NextRMSNormGatedOp): + """``transformers`` gated convention: weight multiply in the input dtype. + + Kept so the HF-vs-vLLM divergence documented in the module docstring stays + covered by a test rather than discovered in a drift report. Do NOT use this + for an L2 claim against vLLM rollout. + """ + + @staticmethod + def _scale_by_weight( + normed: torch.Tensor, weight: torch.Tensor, input_dtype: torch.dtype + ) -> torch.Tensor: + """transformers: round-trip through the input dtype first.""" + return weight * normed.to(input_dtype) diff --git a/rl_engine/kernels/ops/pytorch/norm/rms_norm.py b/rl_engine/kernels/ops/pytorch/norm/rms_norm.py index 135556c3c..66d4723fa 100644 --- a/rl_engine/kernels/ops/pytorch/norm/rms_norm.py +++ b/rl_engine/kernels/ops/pytorch/norm/rms_norm.py @@ -86,6 +86,15 @@ def strict_add_rms_norm( return _strict_add_rms_norm(x, residual, weight, eps) +def check_norm_weight(x: torch.Tensor, weight: torch.Tensor) -> None: + """Shared shape guard for the RMSNorm family (plain, zero-centred, gated).""" + if weight.dim() != 1 or weight.shape[0] != x.shape[-1]: + raise ValueError( + f"weight must be 1-D of size x.shape[-1]={x.shape[-1]}, " + f"got tuple(weight.shape)={tuple(weight.shape)}" + ) + + def shape_invariant_rstd(x_f: torch.Tensor, eps: float) -> torch.Tensor: """Shape-invariant per-row rstd (the shared RMSNorm statistic). @@ -113,6 +122,10 @@ class NativeRMSNormOp: out = x * rsqrt(mean(x^2, dim=-1) + eps) * weight """ + #: Added to the weight in fp32 before it scales the normalized value. + #: Subclasses set 1.0 for the zero-centred ``(1 + w)`` convention. + weight_offset = 0.0 + def __init__(self) -> None: pass @@ -151,21 +164,24 @@ def forward_fp32( # ------------------------------------------------------------------ # # Helpers # ------------------------------------------------------------------ # - @staticmethod + @classmethod def _rms_norm( + cls, x: torch.Tensor, weight: torch.Tensor, *, eps: float, output_dtype: torch.dtype, ) -> torch.Tensor: - if weight.dim() != 1 or weight.shape[0] != x.shape[-1]: - raise ValueError( - f"weight must be 1-D of size x.shape[-1]={x.shape[-1]}, " - f"got tuple(weight.shape)={tuple(weight.shape)}" - ) + check_norm_weight(x, weight) x_f = x.float() rstd = shape_invariant_rstd(x_f, float(eps)).unsqueeze(-1) normed = x_f * rstd - out = normed * weight.float() + scale = weight.float() + # Guarded rather than unconditional: `0.0 + w` rewrites -0.0 to +0.0, + # which torch.equal does not notice but a bitwise comparison does. The + # plain path must stay bit-for-bit what it was. + if cls.weight_offset: + scale = cls.weight_offset + scale + out = normed * scale return out.to(output_dtype) diff --git a/tests/check_qwen3_next_norm_providers.py b/tests/check_qwen3_next_norm_providers.py new file mode 100644 index 000000000..062052cfa --- /dev/null +++ b/tests/check_qwen3_next_norm_providers.py @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2026 RL-Kernel Contributors + +"""Which vLLM gated-RMSNorm path is the strict provider, and how far apart are they. + +Named ``check_`` rather than ``test_`` on purpose, following +``tests/distributed/check_*.py``: this module imports real vLLM, and +``tests/test_framework_operator_integrations.py`` asserts that ``vllm`` is absent +from ``sys.modules`` -- an invariant any collected test importing vLLM would break +for the whole session. Run it explicitly: + + pytest tests/check_qwen3_next_norm_providers.py -v + +RFC #428 section 2.1 defines L2 as "bitwise identical to vLLM rollout". For +Qwen3-Next's GDN gated norm that phrase is not well defined until a single +provider is named, because vLLM ships several and they do not agree bitwise with +each other. + +This module pins two things so a vLLM upgrade cannot move them silently: + +1. **Dispatch facts** -- which provider actually runs, asserted on the env + defaults and the registered ops rather than inferred from reading one branch. +2. **The size of the gap** -- a seed sweep that asserts an upper bound on the + disagreement and on the mismatch rate. It deliberately does NOT assert + equality; the point is to keep the number honest, not to pretend it is zero. + +Measured on 2x B200 (sm_100, torch 2.13.0+cu130, vllm 0.30.0), bf16, +``head_v_dim=128``, 512 rows, 40 seeds: + +=============================== ================== ================ +comparison seeds not bitwise worst max|diff| +=============================== ================== ================ +ours vs ``forward_native`` 6 / 40 1.56e-2 +ours vs ``forward_cuda`` 18 / 40 3.91e-3 +``forward_native`` vs ``cuda`` 21 / 40 1.56e-2 +=============================== ================== ================ +""" + +from __future__ import annotations + +import pytest +import torch + +from rl_engine.kernels.ops.pytorch.norm.qwen3_next_rms_norm import Qwen3NextRMSNormGatedOp + +# vLLM is imported inside the checks, never at module scope, so that merely +# collecting this file does not pull it into sys.modules. + +pytestmark = pytest.mark.skipif(not torch.cuda.is_available(), reason="CUDA is required") + +# Qwen3-Next-80B-A3B-Instruct: linear_value_head_dim / rms_norm_eps. +_HEAD_V_DIM = 128 +_EPS = 1e-6 +_ROWS = 512 +_SEEDS = 40 + +# The gated norm is constructed by vLLM's GDN block with exactly these settings; +# see vllm/model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py. +_NORM_BEFORE_GATE = True +_GROUP_SIZE = None +_ACTIVATION = "silu" + + +@pytest.fixture(scope="module") +def vllm_config_ctx(): + """`RMSNormGated` is a CustomOp and refuses to build outside a config context.""" + pytest.importorskip("vllm", reason="vLLM is required to identify the provider") + from vllm.config import VllmConfig, set_current_vllm_config + + with set_current_vllm_config(VllmConfig()): + yield + + +def _make_norm(): + from vllm.model_executor.layers.layernorm import RMSNormGated + + return RMSNormGated( + _HEAD_V_DIM, + eps=_EPS, + group_size=_GROUP_SIZE, + norm_before_gate=_NORM_BEFORE_GATE, + activation=_ACTIVATION, + ) + + +def _inputs(seed: int, dtype: torch.dtype, rows: int = _ROWS): + g = torch.Generator(device="cuda").manual_seed(seed) + x = torch.randn(rows, _HEAD_V_DIM, device="cuda", dtype=dtype, generator=g) + gate = torch.randn(rows, _HEAD_V_DIM, device="cuda", dtype=dtype, generator=g) + weight = torch.randn(_HEAD_V_DIM, device="cuda", dtype=dtype, generator=g) + return x, gate, weight + + +def _disagreement(a: torch.Tensor, b: torch.Tensor) -> tuple[float, float]: + """(worst absolute difference, fraction of elements that differ bitwise).""" + bits_a = a.float().view(torch.int32) + bits_b = b.float().view(torch.int32) + mismatch = int((bits_a != bits_b).sum()) + worst = (a.float() - b.float()).abs().max().item() + return worst, mismatch / a.numel() + + +# --------------------------------------------------------------------------- # +# 1. Dispatch facts -- which provider actually runs +# --------------------------------------------------------------------------- # +def test_custom_op_has_distinct_native_and_cuda_paths(vllm_config_ctx): + """`forward_native` is a reference; `forward_cuda` is what CustomOp dispatches.""" + norm = _make_norm() + assert type(norm).forward_cuda is not type(norm).forward_native + + +def test_gdn_decode_provider_env_defaults_are_recorded(): + """Pin the env defaults that decide which GDN decode kernel runs. + + These are what make ``fused_recurrent_gated_delta_rule_packed_decode`` (not + ``fused_sigmoid_gating_delta_rule_update``) the rollout decode path. If a + vLLM bump flips either default, the provider identity behind any L2 claim + changes, so this must fail loudly rather than drift. + """ + pytest.importorskip("vllm", reason="vLLM is required to identify the provider") + import vllm.envs as envs + + observed = { + "VLLM_GDN_DECODE_KERNEL": envs.VLLM_GDN_DECODE_KERNEL.strip().lower(), + "VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE": bool( + envs.VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE + ), + } + assert observed == { + "VLLM_GDN_DECODE_KERNEL": "cuda", + "VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE": True, + }, ( + f"GDN decode provider defaults changed: {observed}. Re-derive which kernel " + "the rollout decode path takes before relying on any exactness claim." + ) + + +# --------------------------------------------------------------------------- # +# 2. The gap, bounded -- never asserted to be zero +# --------------------------------------------------------------------------- # +@pytest.mark.parametrize( + "dtype, max_abs, max_mismatch_rate", + [ + # bf16 rounding absorbs most of the reduction-tree difference, so few + # elements move -- but each that does moves by a whole bf16 ULP. + (torch.bfloat16, 2e-2, 0.05), + # fp32 has nothing to absorb it: ~36% of elements differ, every one of + # them by an fp32 ULP. Bounding the rate here would be measuring the + # wrong thing; the magnitude is what says the two agree semantically. + (torch.float32, 1e-5, 1.0), + ], +) +def test_vllm_paths_disagree_only_within_bounds(vllm_config_ctx, dtype, max_abs, max_mismatch_rate): + """vLLM's own two paths differ; bound how much. + + A growing magnitude means the reduction trees have diverged semantically, + which would invalidate treating either as the reference. A high mismatch + *rate* at ULP magnitude does not -- it just means the tree shapes differ. + """ + norm = _make_norm().to("cuda", dtype) + worst_abs, worst_rate, differing = 0.0, 0.0, 0 + for seed in range(_SEEDS): + x, gate, weight = _inputs(seed, dtype) + norm.weight.data = weight.clone() + native = norm.forward_native(x, gate) + cuda = norm.forward_cuda(x, gate) + abs_d, rate = _disagreement(native, cuda) + worst_abs, worst_rate = max(worst_abs, abs_d), max(worst_rate, rate) + differing += int(rate > 0.0) + + assert worst_abs <= max_abs, ( + f"vLLM forward_native vs forward_cuda worst |diff| {worst_abs:.3e} exceeds " + f"{max_abs:.3e} over {_SEEDS} seeds ({differing} seeds differ)" + ) + assert worst_rate <= max_mismatch_rate + + +@pytest.mark.parametrize("path", ["forward_native", "forward_cuda"]) +def test_ours_tracks_each_vllm_path_within_bounds(vllm_config_ctx, path): + """Our strict op follows vLLM's convention; bound the residual. + + Not an equality assertion. We reproduce the fp32 weight multiply and the + single trailing cast, but our reduction is the repo's fixed 32-wide chunked + sum rather than whatever tree the provider uses, so a few elements straddle + a rounding boundary. + """ + dtype = torch.bfloat16 + ours = Qwen3NextRMSNormGatedOp() + norm = _make_norm().to("cuda", dtype) + + worst_abs, worst_rate = 0.0, 0.0 + for seed in range(_SEEDS): + x, gate, weight = _inputs(seed, dtype) + norm.weight.data = weight.clone() + reference = getattr(norm, path)(x, gate) + abs_d, rate = _disagreement(ours.forward(x, weight, gate), reference) + worst_abs, worst_rate = max(worst_abs, abs_d), max(worst_rate, rate) + + assert worst_abs <= 2e-2, f"worst |diff| vs {path} was {worst_abs:.3e}" + assert worst_rate <= 0.05, f"mismatch rate vs {path} was {worst_rate:.3%}" + + +# --------------------------------------------------------------------------- # +# 3. Batch invariance -- the property we DO claim +# --------------------------------------------------------------------------- # +@pytest.mark.parametrize("path", ["forward_native", "forward_cuda"]) +def test_vllm_gated_norm_is_batch_invariant(vllm_config_ctx, path): + """If this ever fails, vLLM stops being a coherent L2 target. + + Kept as a guard rather than a claim about our code: a provider whose output + depends on unrelated rows cannot anchor a bitwise contract. + """ + dtype = torch.bfloat16 + norm = _make_norm().to("cuda", dtype) + for seed in range(8): + x, gate, weight = _inputs(seed, dtype) + norm.weight.data = weight.clone() + full = getattr(norm, path)(x, gate) + for n in (1, 2, 8, 16, 32, 48, 64, 256): + sliced = getattr(norm, path)(x[:n], gate[:n]) + assert torch.equal(sliced, full[:n]), f"{path} seed={seed} n={n}" + + +def test_our_gated_op_is_batch_invariant(): + """The L1 claim for this operator, bitwise.""" + dtype = torch.bfloat16 + ours = Qwen3NextRMSNormGatedOp() + for seed in range(8): + x, gate, weight = _inputs(seed, dtype) + full = ours.forward(x, weight, gate) + for n in (1, 2, 8, 16, 32, 48, 64, 256): + assert torch.equal(ours.forward(x[:n], weight, gate[:n]), full[:n]) diff --git a/tests/test_qwen3_next_norm.py b/tests/test_qwen3_next_norm.py new file mode 100644 index 000000000..c66bf2ba7 --- /dev/null +++ b/tests/test_qwen3_next_norm.py @@ -0,0 +1,502 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2026 RL-Kernel Contributors + +"""WS1 C1 (RFC #428): Qwen3-Next RMSNorm conventions and batch invariance. + +Claim levels exercised here (RFC #428 section 2.1): + * L0 repeatable -- identical inputs reproduce bitwise identical outputs. + * L1 batch-invariant -- a row is unaffected by unrelated rows, padding or order. + +L2 (train-rollout exact against vLLM) is NOT claimed by this file; it needs the +rollout engine on the other side. + +The reduction order here is the repo's fixed 32-wide chunked reduction, which +differs from upstream's ``mean(-1)``. What is reproduced exactly is the weight +convention and the cast order, so comparisons against the upstream formula are +tolerance based while the invariance assertions are bitwise. +""" + +from __future__ import annotations + +import pytest +import torch +import torch.nn.functional as F + +from rl_engine.kernels.ops.pytorch.norm.qwen3_next_rms_norm import ( + Qwen3NextRMSNormGatedHFOp, + Qwen3NextRMSNormGatedOp, + Qwen3NextRMSNormOp, +) + +# Qwen3-Next-80B-A3B-Instruct config.json +_HIDDEN = 2048 # hidden_size +_HEAD_V_DIM = 128 # linear_value_head_dim -- the gated norm width +_EPS = 1e-6 # rms_norm_eps + + +def _rand(shape, seed): + g = torch.Generator().manual_seed(seed) + return torch.randn(*shape, generator=g, dtype=torch.float32) + + +# --------------------------------------------------------------------------- # +# Upstream formulas, transcribed from transformers/models/qwen3_next. +# These pin the exact semantics; they are deliberately verbatim. +# --------------------------------------------------------------------------- # +def _hf_rms_norm(x, weight, eps=_EPS): + output = x.float() * torch.rsqrt(x.float().pow(2).mean(-1, keepdim=True) + eps) + output = output * (1.0 + weight.float()) + return output.type_as(x) + + +def _vllm_rms_norm_gated(x, weight, gate, eps=_EPS): + """vLLM ``RMSNormGated.forward_static`` with ``norm_before_gate=True``.""" + orig_dtype = x.dtype + x, weight, z = x.float(), weight.float(), gate.float() + variance = x.pow(2).mean(dim=-1, keepdim=True) + out = (x * torch.rsqrt(variance + eps)) * weight + out = out * F.silu(z) + return out.to(orig_dtype) + + +def _hf_rms_norm_gated(x, weight, gate, eps=_EPS): + input_dtype = x.dtype + h = x.to(torch.float32) + variance = h.pow(2).mean(-1, keepdim=True) + h = h * torch.rsqrt(variance + eps) + h = weight * h.to(input_dtype) + h = h * F.silu(gate.to(torch.float32)) + return h.to(input_dtype) + + +# --------------------------------------------------------------------------- # +# 1. The zero-centred (1 + w) convention +# --------------------------------------------------------------------------- # +def test_zero_weight_is_identity_scaling(): + """weight == 0 must leave the normalized value untouched, bitwise. + + This is what separates the zero-centred convention from the plain one: a + plain RMSNorm returns all zeros for a zero weight, this one returns the + bare normalized value. + """ + from rl_engine.kernels.ops.pytorch.norm.rms_norm import ( + NativeRMSNormOp, + shape_invariant_rstd, + ) + + x = _rand((4, _HIDDEN), seed=0) + zeros = torch.zeros(_HIDDEN) + + x_f = x.float() + bare = x_f * shape_invariant_rstd(x_f, _EPS).unsqueeze(-1) + assert torch.equal(Qwen3NextRMSNormOp().forward_fp32(x, zeros, eps=_EPS), bare) + + # ... and the plain convention really does differ here. + assert torch.equal( + NativeRMSNormOp().forward_fp32(x, zeros, eps=_EPS), torch.zeros_like(bare) + ) + + +def test_weight_offset_is_one(): + """w and w+1 scaling relationship: out(w) == norm * (1 + w).""" + op = Qwen3NextRMSNormOp() + x = _rand((2, _HEAD_V_DIM), seed=1) + unit = op.forward_fp32(x, torch.zeros(_HEAD_V_DIM)) # scale = 1 + doubled = op.forward_fp32(x, torch.ones(_HEAD_V_DIM)) # scale = 2 + torch.testing.assert_close(doubled, 2.0 * unit, atol=1e-6, rtol=1e-6) + + +def test_offset_applied_in_fp32_not_folded_into_bf16(): + """The 1 + w offset must not be pre-rounded through bf16. + + A weight one bf16 ULP below zero stays distinguishable from exactly zero + once the offset is added in fp32; folding (1 + w) into bf16 first would + collapse both to 1.0 and lose the difference. + """ + op = Qwen3NextRMSNormOp() + x = _rand((2, _HEAD_V_DIM), seed=2) + tiny = torch.full((_HEAD_V_DIM,), -(2**-9), dtype=torch.bfloat16) + folded = (1.0 + tiny.float()).bfloat16() # the wrong way + assert not torch.equal( + op.forward_fp32(x, tiny), + op.forward_fp32(x, folded - 1.0), + ) + + +# --------------------------------------------------------------------------- # +# 2. L1 -- batch invariance, bitwise +# --------------------------------------------------------------------------- # +@pytest.mark.parametrize("hidden", [_HIDDEN, _HEAD_V_DIM]) +def test_batch_invariance_slice(hidden): + op = Qwen3NextRMSNormOp() + w, x = _rand((hidden,), seed=3), _rand((8, 32, hidden), seed=4) + full = op.forward_fp32(x, w) + assert torch.equal(op.forward_fp32(x[:1], w), full[:1]) + assert torch.equal(op.forward_fp32(x[3:5], w), full[3:5]) + + +@pytest.mark.parametrize("batch", [1, 2, 8, 16, 32, 48, 64]) +def test_batch_invariance_across_concurrency(batch): + """RFC #428 section 10: batch size / concurrency axis 1..64.""" + op = Qwen3NextRMSNormOp() + w = _rand((_HIDDEN,), seed=5) + target = _rand((1, _HIDDEN), seed=6) + others = _rand((batch - 1, _HIDDEN), seed=7) if batch > 1 else None + alone = op.forward_fp32(target, w) + for position in ("first", "last"): + if others is None: + batched, index = target, 0 + elif position == "first": + batched, index = torch.cat([target, others]), 0 + else: + batched, index = torch.cat([others, target]), batch - 1 + assert torch.equal(op.forward_fp32(batched, w)[index : index + 1], alone) + + +def test_batch_invariance_with_padding(): + op = Qwen3NextRMSNormOp() + w = _rand((_HIDDEN,), seed=8) + x = _rand((4, _HIDDEN), seed=9) + padded = torch.cat([x, _rand((6, _HIDDEN), seed=10)], dim=0) + assert torch.equal(op.forward_fp32(padded, w)[:4], op.forward_fp32(x, w)) + + +def test_gated_batch_invariance_slice(): + op = Qwen3NextRMSNormGatedOp() + w = _rand((_HEAD_V_DIM,), seed=11) + x = _rand((8, 32, _HEAD_V_DIM), seed=12) + gate = _rand((8, 32, _HEAD_V_DIM), seed=13) + full = op.forward_fp32(x, w, gate) + assert torch.equal(op.forward_fp32(x[:1], w, gate[:1]), full[:1]) + assert torch.equal(op.forward_fp32(x[3:5], w, gate[3:5]), full[3:5]) + + +# --------------------------------------------------------------------------- # +# 2b. The fixed-order reduction is what buys invariance -- on CUDA too +# --------------------------------------------------------------------------- # +@pytest.mark.skipif(not torch.cuda.is_available(), reason="CUDA is required") +@pytest.mark.parametrize("hidden", [_HIDDEN, _HEAD_V_DIM]) +def test_chunked_reduction_is_slice_invariant_on_device(hidden): + """The rstd statistic must be slice-invariant on the accelerator, every seed. + + Measured counterpoint on B200/bf16/H=2048: a plain ``mean(-1)`` broke this on + 1 of 20 seeds. We assert only the property we rely on -- asserting that torch's + ``mean`` is broken would be a brittle test of someone else's kernel. + """ + from rl_engine.kernels.ops.pytorch.norm.rms_norm import shape_invariant_rstd + + for seed in range(20): + g = torch.Generator(device="cuda").manual_seed(seed) + x = torch.randn(64, hidden, device="cuda", dtype=torch.bfloat16, generator=g) + full = shape_invariant_rstd(x.float(), _EPS) + assert torch.equal(shape_invariant_rstd(x[3:5].float(), _EPS), full[3:5]), seed + assert torch.equal(shape_invariant_rstd(x[:1].float(), _EPS), full[:1]), seed + + +@pytest.mark.skipif(not torch.cuda.is_available(), reason="CUDA is required") +def test_op_batch_invariance_on_device(): + """L1 for the op itself, on the accelerator, in the model's dtype.""" + op = Qwen3NextRMSNormOp() + g = torch.Generator(device="cuda").manual_seed(0) + x = torch.randn(64, _HIDDEN, device="cuda", dtype=torch.bfloat16, generator=g) + w = torch.randn(_HIDDEN, device="cuda", dtype=torch.bfloat16, generator=g) + full = op.forward(x, w) + for n in (1, 2, 8, 16, 32, 48, 64): + assert torch.equal(op.forward(x[:n], w), full[:n]), n + + +# --------------------------------------------------------------------------- # +# 3. L0 -- repeatable +# --------------------------------------------------------------------------- # +def test_deterministic_repeat(): + op = Qwen3NextRMSNormOp() + x, w = _rand((64, _HIDDEN), seed=14), _rand((_HIDDEN,), seed=15) + first = op.forward_fp32(x, w) + for _ in range(10): + assert torch.equal(op.forward_fp32(x, w), first) + + +# --------------------------------------------------------------------------- # +# 4. Agreement with the upstream formula (tolerance, not bitwise: the reduction +# order differs by design) +# --------------------------------------------------------------------------- # +@pytest.mark.parametrize("hidden", [_HIDDEN, _HEAD_V_DIM]) +def test_matches_upstream_formula_fp32(hidden): + op = Qwen3NextRMSNormOp() + x, w = _rand((4, 16, hidden), seed=16), _rand((hidden,), seed=17) + torch.testing.assert_close(op.forward_fp32(x, w), _hf_rms_norm(x, w), atol=1e-6, rtol=1e-6) + + +def test_gated_strict_matches_vllm_formula_fp32(): + """The strict gated op follows vLLM, which is what the L2 claim targets.""" + op = Qwen3NextRMSNormGatedOp() + x = _rand((4, 16, _HEAD_V_DIM), seed=18) + w = _rand((_HEAD_V_DIM,), seed=19) + gate = _rand((4, 16, _HEAD_V_DIM), seed=20) + torch.testing.assert_close( + op.forward_fp32(x, w, gate), + _vllm_rms_norm_gated(x, w, gate), + atol=1e-6, + rtol=1e-6, + ) + + +def test_gated_hf_witness_matches_hf_formula_fp32(): + op = Qwen3NextRMSNormGatedHFOp() + x = _rand((4, 16, _HEAD_V_DIM), seed=18) + w = _rand((_HEAD_V_DIM,), seed=19) + gate = _rand((4, 16, _HEAD_V_DIM), seed=20) + torch.testing.assert_close( + op.forward_fp32(x, w, gate), + _hf_rms_norm_gated(x, w, gate), + atol=1e-6, + rtol=1e-6, + ) + + +def test_gated_conventions_diverge_in_low_precision(): + """Pin the HF-vs-vLLM gated divergence (RFC #428 first-divergence boundary). + + With fp32 inputs the two conventions coincide, because the HF round-trip is + an identity. In bf16 they do not, and the gap is far larger than a ULP: this + is why the convention is part of the operator identity and not a detail. + """ + strict, witness = Qwen3NextRMSNormGatedOp(), Qwen3NextRMSNormGatedHFOp() + x = _rand((64, _HEAD_V_DIM), seed=33).bfloat16() + w = _rand((_HEAD_V_DIM,), seed=34).bfloat16() + gate = _rand((64, _HEAD_V_DIM), seed=35).bfloat16() + + a, b = strict.forward(x, w, gate), witness.forward(x, w, gate) + assert not torch.equal(a, b), "the two gated conventions must be distinguishable" + assert (a.float() - b.float()).abs().max() > 1e-3 + + # ... and in fp32 the round-trip vanishes, so they agree bitwise. + xf, wf, gf = x.float(), w.float(), gate.float() + assert torch.equal(strict.forward(xf, wf, gf), witness.forward(xf, wf, gf)) + + +@pytest.mark.parametrize("dtype", [torch.bfloat16, torch.float16]) +def test_matches_upstream_formula_low_precision(dtype): + op = Qwen3NextRMSNormOp() + x = _rand((4, 16, _HIDDEN), seed=21).to(dtype) + w = _rand((_HIDDEN,), seed=22).to(dtype) + got, ref = op.forward(x, w), _hf_rms_norm(x, w) + assert got.dtype == ref.dtype == dtype + torch.testing.assert_close(got.float(), ref.float(), atol=2e-2, rtol=1.6e-2) + + +@pytest.mark.parametrize("dtype", [torch.bfloat16, torch.float16]) +def test_gated_hf_witness_low_precision(dtype): + """Covers the mid-computation cast back to the input dtype.""" + op = Qwen3NextRMSNormGatedHFOp() + x = _rand((4, 16, _HEAD_V_DIM), seed=23).to(dtype) + w = _rand((_HEAD_V_DIM,), seed=24).to(dtype) + gate = _rand((4, 16, _HEAD_V_DIM), seed=25).to(dtype) + got, ref = op.forward(x, w, gate), _hf_rms_norm_gated(x, w, gate) + assert got.dtype == ref.dtype == dtype + torch.testing.assert_close(got.float(), ref.float(), atol=2e-2, rtol=1.6e-2) + + +@pytest.mark.parametrize("dtype", [torch.bfloat16, torch.float16]) +def test_gated_strict_low_precision(dtype): + op = Qwen3NextRMSNormGatedOp() + x = _rand((4, 16, _HEAD_V_DIM), seed=23).to(dtype) + w = _rand((_HEAD_V_DIM,), seed=24).to(dtype) + gate = _rand((4, 16, _HEAD_V_DIM), seed=25).to(dtype) + got, ref = op.forward(x, w, gate), _vllm_rms_norm_gated(x, w, gate) + assert got.dtype == ref.dtype == dtype + torch.testing.assert_close(got.float(), ref.float(), atol=2e-2, rtol=1.6e-2) + + +# --------------------------------------------------------------------------- # +# 5. dtype paths and guards +# --------------------------------------------------------------------------- # +@pytest.mark.parametrize("dtype", [torch.float32, torch.bfloat16, torch.float16]) +def test_dtype_paths(dtype): + op = Qwen3NextRMSNormOp() + x = _rand((2, 16, _HIDDEN), seed=26).to(dtype) + w = _rand((_HIDDEN,), seed=27).to(dtype) + assert op.forward(x, w).dtype == dtype + assert op.forward_fp32(x, w).dtype == torch.float32 + + +def test_eps_inside_sqrt(): + op = Qwen3NextRMSNormOp() + out = op.forward_fp32(torch.zeros(1, _HIDDEN), torch.zeros(_HIDDEN)) + assert torch.isfinite(out).all() + assert torch.equal(out, torch.zeros(1, _HIDDEN)) + + +def test_bad_weight_shape_raises(): + op = Qwen3NextRMSNormOp() + with pytest.raises(ValueError, match="weight must be 1-D"): + op.forward_fp32(_rand((2, _HIDDEN), seed=28), _rand((_HIDDEN - 1,), seed=29)) + + +def test_gated_shape_mismatch_raises(): + op = Qwen3NextRMSNormGatedOp() + x, w = _rand((2, _HEAD_V_DIM), seed=30), _rand((_HEAD_V_DIM,), seed=31) + with pytest.raises(ValueError, match="gate must match x"): + op.forward_fp32(x, w, _rand((3, _HEAD_V_DIM), seed=32)) + + +# --------------------------------------------------------------------------- # +# 6. CUDA kernel: the offset is applied in fp32 inside the kernel +# --------------------------------------------------------------------------- # +_CUDA_RMSNORM = False +if torch.cuda.is_available(): # pragma: no branch - probe only + try: + from rl_engine.kernels.ops.base import _C, _EXT_AVAILABLE + + _CUDA_RMSNORM = _EXT_AVAILABLE and hasattr(_C, "rmsnorm_forward") + except ImportError: # pragma: no cover + _CUDA_RMSNORM = False + +requires_cuda_rmsnorm = pytest.mark.skipif( + not _CUDA_RMSNORM, reason="CUDA RMSNorm extension is not available" +) + + +@requires_cuda_rmsnorm +def test_cuda_offset_equals_explicit_fp32_weight(): + """``weight_offset=1.0`` must equal passing an fp32 ``1 + w``, bitwise. + + This is the correctness proof for doing the offset inside the kernel: it is + the same arithmetic as the fp32 reference, not an approximation of it. + """ + from rl_engine.kernels.ops.cuda.norm.rmsnorm import rmsnorm_cuda + + torch.manual_seed(0) + x = torch.randn(512, _HIDDEN, device="cuda", dtype=torch.bfloat16) + w = torch.randn(_HIDDEN, device="cuda", dtype=torch.bfloat16) + + offset = rmsnorm_cuda(x, w, eps=_EPS, weight_offset=1.0) + explicit = rmsnorm_cuda(x, (1.0 + w.float()), eps=_EPS) + assert torch.equal(offset, explicit) + + +@requires_cuda_rmsnorm +def test_cuda_offset_is_not_folded_through_bfloat16(): + """Pre-rounding ``1 + w`` to bf16 must give a different answer. + + If this ever becomes equal, the offset has stopped being applied in fp32 and + the zero-centred contract is silently broken. + """ + from rl_engine.kernels.ops.cuda.norm.rmsnorm import rmsnorm_cuda + + torch.manual_seed(0) + x = torch.randn(512, _HIDDEN, device="cuda", dtype=torch.bfloat16) + w = torch.randn(_HIDDEN, device="cuda", dtype=torch.bfloat16) + + offset = rmsnorm_cuda(x, w, eps=_EPS, weight_offset=1.0) + folded = rmsnorm_cuda(x, (1.0 + w.float()).bfloat16(), eps=_EPS) + assert not torch.equal(offset, folded) + + +@requires_cuda_rmsnorm +def test_cuda_default_offset_preserves_plain_convention(): + """An unset offset must leave the existing kernel behaviour untouched.""" + from rl_engine.kernels.ops.cuda.norm.rmsnorm import RMSNormCudaOp, rmsnorm_cuda + + torch.manual_seed(0) + x = torch.randn(256, _HEAD_V_DIM, device="cuda", dtype=torch.bfloat16) + w = torch.randn(_HEAD_V_DIM, device="cuda", dtype=torch.bfloat16) + assert torch.equal(RMSNormCudaOp().forward(x, w, eps=_EPS), rmsnorm_cuda(x, w, eps=_EPS)) + + +@requires_cuda_rmsnorm +@pytest.mark.parametrize("batch", [1, 2, 8, 16, 32, 48, 64, 512]) +def test_cuda_zero_centred_batch_invariance(batch): + """L1 for the zero-centred CUDA op across the RFC #428 concurrency axis.""" + from rl_engine.kernels.ops.cuda.norm.rmsnorm import Qwen3NextRMSNormCudaOp + + op = Qwen3NextRMSNormCudaOp() + torch.manual_seed(0) + x = torch.randn(512, _HIDDEN, device="cuda", dtype=torch.bfloat16) + w = torch.randn(_HIDDEN, device="cuda", dtype=torch.bfloat16) + assert torch.equal(op.forward(x[:batch], w, eps=_EPS), op.forward(x, w, eps=_EPS)[:batch]) + + +@requires_cuda_rmsnorm +def test_cuda_zero_centred_within_tolerance_of_golden(): + from rl_engine.kernels.ops.cuda.norm.rmsnorm import Qwen3NextRMSNormCudaOp + + torch.manual_seed(0) + x = torch.randn(256, _HIDDEN, device="cuda", dtype=torch.bfloat16) + w = torch.randn(_HIDDEN, device="cuda", dtype=torch.bfloat16) + got = Qwen3NextRMSNormCudaOp().forward(x, w, eps=_EPS) + ref = Qwen3NextRMSNormOp().forward_fp32(x, w, eps=_EPS) + torch.testing.assert_close(got.float(), ref, atol=2e-2, rtol=1.6e-2) + + +@requires_cuda_rmsnorm +def test_cuda_zero_centred_backward_is_offset_aware(): + """dx must see (1 + w); dw is offset-independent since d/dw (1+w) == d/dw w.""" + from rl_engine.kernels.ops.cuda.norm.rmsnorm import rmsnorm_cuda + + torch.manual_seed(0) + x = torch.randn(128, _HEAD_V_DIM, device="cuda", dtype=torch.float32) + w = torch.randn(_HEAD_V_DIM, device="cuda", dtype=torch.float32) + dy = torch.randn(128, _HEAD_V_DIM, device="cuda", dtype=torch.float32) + + grads = {} + for name, off in (("plain", 0.0), ("zero_centred", 1.0)): + xg = x.clone().requires_grad_(True) + wg = w.clone().requires_grad_(True) + rmsnorm_cuda(xg, wg, eps=_EPS, weight_offset=off).backward(dy.clone()) + grads[name] = (xg.grad.clone(), wg.grad.clone()) + + assert torch.isfinite(grads["zero_centred"][0]).all() + assert not torch.equal(grads["plain"][0], grads["zero_centred"][0]) # dx differs + assert torch.equal(grads["plain"][1], grads["zero_centred"][1]) # dw does not + + +# --------------------------------------------------------------------------- # +# 8. `__call__` is the documented entry point and must agree with `forward` +# --------------------------------------------------------------------------- # +def test_call_matches_forward(): + x, w = _rand((4, _HIDDEN), seed=40), _rand((_HIDDEN,), seed=41) + op = Qwen3NextRMSNormOp() + assert torch.equal(op(x, w, eps=_EPS), op.forward(x, w, eps=_EPS)) + + +@pytest.mark.parametrize("cls", [Qwen3NextRMSNormGatedOp, Qwen3NextRMSNormGatedHFOp]) +def test_gated_call_matches_forward(cls): + x = _rand((4, _HEAD_V_DIM), seed=42) + w = _rand((_HEAD_V_DIM,), seed=43) + gate = _rand((4, _HEAD_V_DIM), seed=44) + op = cls() + assert torch.equal(op(x, w, gate, eps=_EPS), op.forward(x, w, gate, eps=_EPS)) + + +def test_zero_centred_op_inherits_the_plain_reference(): + """The only difference from the plain op is the weight convention. + + Pins the inheritance: if the subclass ever grows its own `_rms_norm`, this + stops being true and the two references can drift apart silently. + """ + from rl_engine.kernels.ops.pytorch.norm.rms_norm import NativeRMSNormOp + + assert issubclass(Qwen3NextRMSNormOp, NativeRMSNormOp) + assert Qwen3NextRMSNormOp.weight_offset == 1.0 + assert NativeRMSNormOp.weight_offset == 0.0 + assert Qwen3NextRMSNormOp._rms_norm.__func__ is NativeRMSNormOp._rms_norm.__func__ + + +def test_plain_reference_is_unchanged_by_the_offset_plumbing(): + """Adding `weight_offset` to the base must not perturb the plain path. + + `0.0 + w` rewrites -0.0 to +0.0, which torch.equal does not notice, so this + compares the raw bits. + """ + from rl_engine.kernels.ops.pytorch.norm.rms_norm import NativeRMSNormOp + + x = _rand((2, _HEAD_V_DIM), seed=45) + w = torch.zeros(_HEAD_V_DIM) + w[0] = -0.0 + got = NativeRMSNormOp().forward_fp32(x, w, eps=_EPS) + x_f = x.float() + from rl_engine.kernels.ops.pytorch.norm.rms_norm import shape_invariant_rstd + + expected = (x_f * shape_invariant_rstd(x_f, _EPS).unsqueeze(-1)) * w.float() + assert torch.equal(got.view(torch.int32), expected.view(torch.int32)) From 5f5654a99268ba7e7bfc0aef646bf46e1c7d379d Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Wed, 30 Sep 2026 18:15:09 +0000 Subject: [PATCH 06/15] fix(norm): preserve signed zero and use CUDA statistics for parameter VJPs Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- csrc/cuda/rmsnorm.cu | 9 ++-- rl_engine/kernels/ops/cuda/norm/rmsnorm.py | 17 +++++--- tests/test_qwen3_next_norm.py | 51 +++++++++++++++++++--- 3 files changed, 60 insertions(+), 17 deletions(-) diff --git a/csrc/cuda/rmsnorm.cu b/csrc/cuda/rmsnorm.cu index fc6c425d6..5b570c557 100644 --- a/csrc/cuda/rmsnorm.cu +++ b/csrc/cuda/rmsnorm.cu @@ -142,7 +142,8 @@ __global__ void rmsnorm_fwd_kernel( // round the offset and break the bitwise contract. for (int col = tid; col < H; col += blockDim.x) { float xv = load_as_float(x_row + col); - float wv = load_as_float(weight + col) + weight_offset; + float wv = load_as_float(weight + col); + if (weight_offset != 0.0f) wv += weight_offset; float out = xv * row_rstd * wv; store_from_float(y_row + col, out); } @@ -172,7 +173,8 @@ __global__ void rmsnorm_bwd_dx_kernel( for (int col = tid; col < H; col += blockDim.x) { float dyv = load_as_float(dy_row + col); float xv = load_as_float(x_row + col); - float wv = load_as_float(weight + col) + weight_offset; + float wv = load_as_float(weight + col); + if (weight_offset != 0.0f) wv += weight_offset; local_dot += dyv * wv * xv; } @@ -184,7 +186,8 @@ __global__ void rmsnorm_bwd_dx_kernel( for (int col = tid; col < H; col += blockDim.x) { float dyv = load_as_float(dy_row + col); float xv = load_as_float(x_row + col); - float wv = load_as_float(weight + col) + weight_offset; + float wv = load_as_float(weight + col); + if (weight_offset != 0.0f) wv += weight_offset; float out = r * dyv * wv - xv * coeff; store_from_float(dx_row + col, out); diff --git a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py index 3b72e497d..7d5a7a754 100644 --- a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py +++ b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py @@ -129,6 +129,7 @@ def __init__(self) -> None: "rmsnorm_forward", "rmsnorm_backward_dx", ) + #: Added to the weight in fp32 inside the kernel. Subclasses override it; #: 0.0 is the plain convention. weight_offset = 0.0 @@ -139,16 +140,18 @@ def __call__(self, x, weight, *, eps=1e-6): def forward(self, x, weight, *, eps=1e-6): hidden = x.shape[-1] x_2d = x.contiguous().view(-1, hidden) - y_2d = rmsnorm_cuda( - x_2d, weight.contiguous(), eps=eps, weight_offset=self.weight_offset - ) + y_2d = rmsnorm_cuda(x_2d, weight.contiguous(), eps=eps, weight_offset=self.weight_offset) return y_2d.view_as(x) def parameter_vjp_contributions_fp32(self, *, x, weight, grad_output, eps=1e-6): - del weight - x32 = x.float() - rstd = torch.rsqrt(x32.square().mean(dim=-1) + float(eps)) - rows = grad_output.float() * x32 * rstd.unsqueeze(-1) + hidden = x.shape[-1] + _, rstd = _C.rmsnorm_forward( + x.contiguous().reshape(-1, hidden), + weight.contiguous(), + float(eps), + float(self.weight_offset), + ) + rows = rmsnorm_dweight_rows_fp32(x, grad_output, rstd=rstd.reshape(x.shape[:-1])) return {"weight": rows} diff --git a/tests/test_qwen3_next_norm.py b/tests/test_qwen3_next_norm.py index c66bf2ba7..9fdf02e73 100644 --- a/tests/test_qwen3_next_norm.py +++ b/tests/test_qwen3_next_norm.py @@ -79,10 +79,7 @@ def test_zero_weight_is_identity_scaling(): plain RMSNorm returns all zeros for a zero weight, this one returns the bare normalized value. """ - from rl_engine.kernels.ops.pytorch.norm.rms_norm import ( - NativeRMSNormOp, - shape_invariant_rstd, - ) + from rl_engine.kernels.ops.pytorch.norm.rms_norm import NativeRMSNormOp, shape_invariant_rstd x = _rand((4, _HIDDEN), seed=0) zeros = torch.zeros(_HIDDEN) @@ -92,9 +89,7 @@ def test_zero_weight_is_identity_scaling(): assert torch.equal(Qwen3NextRMSNormOp().forward_fp32(x, zeros, eps=_EPS), bare) # ... and the plain convention really does differ here. - assert torch.equal( - NativeRMSNormOp().forward_fp32(x, zeros, eps=_EPS), torch.zeros_like(bare) - ) + assert torch.equal(NativeRMSNormOp().forward_fp32(x, zeros, eps=_EPS), torch.zeros_like(bare)) def test_weight_offset_is_one(): @@ -500,3 +495,45 @@ def test_plain_reference_is_unchanged_by_the_offset_plumbing(): expected = (x_f * shape_invariant_rstd(x_f, _EPS).unsqueeze(-1)) * w.float() assert torch.equal(got.view(torch.int32), expected.view(torch.int32)) + + +@requires_cuda_rmsnorm +@pytest.mark.parametrize("dtype", [torch.float32, torch.float16, torch.bfloat16]) +def test_cuda_plain_signed_zero_is_preserved(dtype): + from rl_engine.kernels.ops.cuda.norm.rmsnorm import rmsnorm_cuda + + x = torch.ones(2, 128, device="cuda", dtype=dtype) + x[1].neg_() + weight = torch.full((128,), -0.0, device="cuda", dtype=dtype) + actual = rmsnorm_cuda(x, weight) + expected = x * weight + bits = torch.int32 if dtype == torch.float32 else torch.int16 + assert torch.equal(actual.view(bits), expected.view(bits)) + + +@requires_cuda_rmsnorm +@pytest.mark.parametrize("offset", [0.0, 1.0]) +@pytest.mark.parametrize("shape", [(512, 128), (2, 3, 2048)]) +@pytest.mark.parametrize("dtype", [torch.float32, torch.bfloat16]) +def test_cuda_parameter_contributions_reproduce_backward(offset, shape, dtype): + from rl_engine.kernels.ops.cuda.norm.rmsnorm import Qwen3NextRMSNormCudaOp, RMSNormCudaOp + from rl_engine.kernels.ops.vjp_fp32 import reduce_rows_fp32 + + torch.manual_seed(128) + x = torch.randn(shape, device="cuda", dtype=dtype) + weight = torch.randn(shape[-1], device="cuda", dtype=dtype, requires_grad=True) + upstream = torch.randn_like(x) + op = RMSNormCudaOp() if offset == 0.0 else Qwen3NextRMSNormCudaOp() + op(x, weight).backward(upstream) + rows = op.parameter_vjp_contributions_fp32(x=x, weight=weight, grad_output=upstream)["weight"] + folded = reduce_rows_fp32(rows.reshape(-1, shape[-1])).to(dtype) + assert torch.equal(weight.grad, folded) + + +def test_zero_centred_cuda_constructor_rejects_missing_extension(monkeypatch): + from rl_engine.kernels.ops.cuda.norm import rmsnorm + + monkeypatch.setattr(rmsnorm, "_EXT_AVAILABLE", False) + monkeypatch.setattr(rmsnorm, "_C", None) + with pytest.raises(RuntimeError, match="requires the compiled"): + rmsnorm.Qwen3NextRMSNormCudaOp() From d03c8523a6e39bb616deead401d13ff9b53b4740 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Thu, 1 Oct 2026 21:36:52 +0000 Subject: [PATCH 07/15] fix(norm): contract tolerances and corrected claims for the Qwen3-Next norms Tests: the low-precision and CUDA-vs-golden comparisons hard-coded atol=2e-2/rtol=1.6e-2, which is the contract's elementwise bf16 row. They now resolve forward_accuracy for op_class="reduction" from tolerance_contract.json. That loosens bf16 (5e-2/2e-2) and tightens fp16 (1e-3/1e-3, previously 2e-2); the fp16 cases still pass. The vLLM provider-gap bounds in tests/check_qwen3_next_norm_providers.py are labelled as gap bounds, not contract thresholds. Docs and docstrings: correct statements this branch had committed. - The operator page no longer says the op is registered or prints a check_operator command; the gtest spec and registry entry arrive with the gated-norm PR. - Withdrawn: "7 of 1048576 differ" (single seed, no script), the 35% / 5.3e-2 cast-order isolation (an fp32 round-trip is a no-op), "needed on CUDA as well", and "matching vLLM means trading L1 for L2" (one unreproduced observation). Replaced with the scoped claim levels and the probe results. - The provider check no longer claims to establish which path vLLM dispatches, or a per-element fp32 ULP bound. - The module docstring is cut to the contract and links to the operator page. Comments: why the kernel's offset add is guarded (signed zero, with the pinning test), and why parameter_vjp_contributions_fp32 passes the offset. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- csrc/cuda/rmsnorm.cu | 3 + docs/operators/qwen3-next-rms-norm.md | 60 +++++++++------ rl_engine/kernels/ops/cuda/norm/rmsnorm.py | 2 + .../ops/pytorch/norm/qwen3_next_rms_norm.py | 76 +++++-------------- tests/check_qwen3_next_norm_providers.py | 43 ++++++----- tests/test_qwen3_next_norm.py | 22 ++++-- 6 files changed, 102 insertions(+), 104 deletions(-) diff --git a/csrc/cuda/rmsnorm.cu b/csrc/cuda/rmsnorm.cu index 5b570c557..0c09b3a4a 100644 --- a/csrc/cuda/rmsnorm.cu +++ b/csrc/cuda/rmsnorm.cu @@ -143,6 +143,9 @@ __global__ void rmsnorm_fwd_kernel( for (int col = tid; col < H; col += blockDim.x) { float xv = load_as_float(x_row + col); float wv = load_as_float(weight + col); + // Guarded: `-0.0f + 0.0f` is +0.0f, so an unconditional add would flip the + // sign bit of -0.0 weights on the plain path. Pinned by + // tests/test_qwen3_next_norm.py::test_cuda_plain_signed_zero_is_preserved. if (weight_offset != 0.0f) wv += weight_offset; float out = xv * row_rstd * wv; store_from_float(y_row + col, out); diff --git a/docs/operators/qwen3-next-rms-norm.md b/docs/operators/qwen3-next-rms-norm.md index 292139bea..81fdde9b3 100644 --- a/docs/operators/qwen3-next-rms-norm.md +++ b/docs/operators/qwen3-next-rms-norm.md @@ -49,32 +49,47 @@ y = rmsnorm_cuda(x, weight, eps=1e-6, weight_offset=1.0) ## Dispatch Behavior -Registered as the `qwen3_next_rms_norm` gtest operator. On CUDA the registry -prefers `Qwen3NextRMSNormCudaOp`; every other platform resolves to the PyTorch -reference. The CUDA op validates the compiled symbols in `__init__`, so on a build -without the extension construction raises and the registry falls through to the -reference rather than handing out an op that fails at call time. +Not registered on this branch: there is no `qwen3_next_rms_norm` gtest spec and no +registry entry yet. Both arrive with the gated-norm PR. Until then, construct the +ops directly as in "Entry Point". The CUDA op validates the compiled symbols in +`__init__`, so on a build without the extension construction raises instead of +handing out an op that fails at call time. ## Accuracy -Claim level: **L0 repeatable, L1 batch-invariant**. L2 is not claimed. +Claim levels: -The reduction is the repo's fixed 32-wide chunked sum -(`shape_invariant_rstd`), which is what makes a row's result independent of the -batch layout. It deliberately differs from upstream's `mean(-1)`: measured on B200, -over 20 seeds at `H=2048` in bf16, a plain `mean(-1)` broke slice invariance on 1 -of 20 while the chunked reduction broke on 0 of 20. +- **L1** (prefix-slice and concurrency) for `Qwen3NextRMSNormCudaOp`; padding, + packing and order are not tested for the CUDA op. +- **L1** (slice, concurrency and padding) for `Qwen3NextRMSNormOp`. +- **L0** for `Qwen3NextRMSNormOp` only (CPU, fp32); no test repeats the CUDA op. +- L2 is not claimed. -The cost is that the decoder norm is **not** bitwise equal to stock vLLM — 7 -elements of 1048576 differ, `max|diff| = 1.56e-2` in bf16 at `H=2048`. That gap is -inherent: matching stock vLLM bitwise would mean adopting a reduction that is not -itself batch-invariant, i.e. trading L1 for L2. +The PyTorch reference uses the repo's fixed 32-wide chunked sum +(`shape_invariant_rstd`, introduced in `8ed1693` as a device-agnostic reference). +On B200, over 20 seeds at `H=2048` in bf16, a plain `mean(-1)` broke slice +invariance on 1 of 20 seeds (slices `x[3:5]` and `x[:1]` of 64 rows; which one +failed was not recorded), and the chunked reduction broke on none. That is a recorded +observation, not an assertion. + +The CUDA kernel has its own fixed-order reduction (per-thread strided partial sums, +then `block_reduce_sum`). It is not bitwise equal to the PyTorch reference. + +Neither is bitwise equal to vLLM. In one-off probes (not committed checks), the +reference differed from every vLLM path tried (eager, inductor-compiled, and eager +under `VLLM_BATCH_INVARIANT=1`) on 36–39 of 40 seeds, `max|diff| <= 1.56e-2` +(bf16, `H=2048`, 512 rows). The difference is attributed to reduction order, but that +has not been isolated. Only the no-residual call was compared; vLLM's +`fused_add_rms_norm` path (every decoder norm except layer 0's input norm) has no +reference here. The in-kernel offset is exact, not an approximation: `weight_offset=1.0` is bitwise equal to passing an explicit fp32 `1 + w` weight, and differs from a bf16-folded `1 + w`, both asserted. -Tolerances come from `tolerance_contract.json` (`reduction` × dtype); no private +Accuracy tests resolve their tolerances from `tolerance_contract.json` +(`forward_accuracy`, `reduction` × dtype). The bounds in +`tests/check_qwen3_next_norm_providers.py` are provider-gap bounds, not contract thresholds. ## Performance Notes @@ -83,11 +98,6 @@ The CUDA path reuses the existing `rmsnorm_fwd_kernel` reduction (`block_reduce_sum` over `choose_threads(H)`), so the offset costs one fp32 add per element and no extra memory traffic. -```bash -python scripts/check_operator.py --op qwen3_next_rms_norm --candidate cuda \ - --device cuda --dtype bf16 --check-grad -``` - ## Tests ```bash @@ -97,7 +107,11 @@ python -m pytest tests/test_qwen3_next_norm.py -v ## Known Limitations - CUDA only; no ROCm, Ascend or Triton backend. -- Not bitwise against stock vLLM (see Accuracy); an L2 claim needs the strict - provider on both sides, per RFC #428 §1 item 1. +- Not registered as a gtest operator or in the registry on this branch (see + "Dispatch Behavior"). +- Not bitwise against vLLM (see Accuracy). An L2 claim needs a single source of + truth for the forward on both sides, per RFC #428 §0 item 1. +- The gated pair (`Qwen3NextRMSNormGatedOp`, `Qwen3NextRMSNormGatedHFOp`) is + documented with its CUDA kernel in the gated-norm PR, not on this page. - Measured on sm_100 (B200). Per RFC #428 §2.2 no claim carries across H100/H200/B100/B200. diff --git a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py index 7d5a7a754..af9a31358 100644 --- a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py +++ b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py @@ -145,6 +145,8 @@ def forward(self, x, weight, *, eps=1e-6): def parameter_vjp_contributions_fp32(self, *, x, weight, grad_output, eps=1e-6): hidden = x.shape[-1] + # Only `rstd` is used, and it does not depend on the offset; the offset is + # passed so this is the same call the forward makes, not because it matters. _, rstd = _C.rmsnorm_forward( x.contiguous().reshape(-1, hidden), weight.contiguous(), diff --git a/rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py b/rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py index 5261245d0..2b3c410a9 100644 --- a/rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py +++ b/rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py @@ -3,66 +3,26 @@ """Qwen3-Next RMSNorm references (WS1 ground truth for RFC #428 C1). -Qwen3-Next ships two RMSNorm conventions that differ both in how the weight is -applied and in where the dtype casts sit. They are kept as separate operators -because the cast order is part of the contract, not a flag: +Qwen3-Next ships two RMSNorm conventions. They differ in how the weight is applied +and in where the dtype casts sit, so they are separate operators rather than a flag: ``Qwen3NextRMSNorm`` (decoder / final norm) - normalize in fp32, scale by ``(1 + weight)`` in fp32, cast once at the end. - The stored weight is zero-centred, so the ``1 +`` offset MUST be applied - after the fp32 upcast -- folding it into a bf16 weight first rounds the - offset and silently breaks the bitwise claim. + Normalize in fp32, scale by ``(1 + weight)`` in fp32, cast once at the end. The + stored weight is zero-centred, so the ``1 +`` must be applied after the fp32 + upcast; folding it into a bf16 weight first rounds the offset. ``Qwen3NextRMSNormGated`` (inside the Gated DeltaNet block) - normalize in fp32, scale by a plain (non zero-centred) weight, then gate by - ``silu(gate)``. Where the weight multiply happens is NOT agreed upstream -- - see below -- so it is an explicit part of the operator identity here. - -Divergence at the gated-norm boundary (measured) -------------------------------------------------- -``transformers`` and vLLM do not agree on the gated variant: - -* vLLM (``RMSNormGated``, both ``forward_native`` and the FLA Triton - ``forward_cuda``) keeps the normalized value in fp32 for the weight multiply. -* ``transformers`` (``Qwen3NextRMSNormGated``) casts the normalized value back - to the input dtype *before* the weight multiply. - -On B200 / bf16 / ``head_v_dim=128`` these differ in 35% of elements with -``max|diff| = 6.25e-2``; swapping only the cast order reproduces the gap -(``5.3e-2``), so the cast order -- not the reduction order -- dominates. Because -RFC #428 claims L2 exactness against **vLLM rollout**, the fp32 multiply is the -strict default; the transformers convention is kept as a named witness so the -divergence stays testable instead of being silently picked. - -What "agrees with vLLM" means here, precisely ----------------------------------------------- -Only the *convention* is reproduced, not the bits. vLLM's own two paths are not -bitwise equal to each other: over 40 seeds (bf16, ``head_v_dim=128``, 512 rows), -``forward_native`` and ``forward_cuda`` disagreed on 21, worst -``max|diff| = 1.56e-2``. Against this operator the figures were 6/40 and 18/40. -So "bitwise equal to vLLM" is undefined until a single provider is named, and -this operator does not claim it -- see the reduction-order note below. - -Both reuse :func:`shape_invariant_rstd` so the reduction order -- and hence the -result -- never depends on the batch layout (RFC #428 section 6, item 2). The -reduction order therefore deliberately differs from upstream's ``mean(-1)``; -what is reproduced exactly is the weight convention and the cast order. - -Why the chunked reduction is kept on CUDA too ---------------------------------------------- -:func:`shape_invariant_rstd` was introduced for NPU, where ``mean``/``sum`` pick -shape-dependent kernels. Measured on B200 (sm_100) it is needed on CUDA as well: -over 20 seeds at ``H=2048`` in bf16 -- Qwen3-Next's own ``hidden_size`` and dtype --- a plain ``mean(-1)`` broke slice invariance (``rstd(x[3:5]) != rstd(x)[3:5]``) -on 1 of 20, while the chunked reduction broke on 0 of 20. Failures were also seen -at ``H=5120`` in fp32. - -The cost is that the decoder norm is NOT bitwise equal to stock vLLM: 7 elements -of 1048576 differ (``max|diff| = 1.56e-2``, bf16, H=2048). That gap is inherent -- -matching stock vLLM bitwise would mean adopting a reduction that is itself not -batch-invariant, i.e. trading L1 for L2. These operators therefore claim L0 and L1 -only; an L2 claim needs the strict provider on both sides, per RFC #428 section 1, -item 1. + Normalize in fp32, scale by a plain weight, then gate by ``silu(gate)``. + vLLM's ``RMSNormGated`` multiplies the weight in fp32; transformers casts the + normalized value back to the input dtype first. ``Qwen3NextRMSNormGatedOp`` + follows vLLM; ``Qwen3NextRMSNormGatedHFOp`` keeps the transformers convention + as a witness, and ``test_gated_conventions_diverge_in_low_precision`` pins that + the two differ in bf16 and agree bitwise in fp32. + +All three reuse :func:`shape_invariant_rstd`, a fixed-order reduction. They +reproduce the weight convention and cast order, not vLLM's reduction tree, and are +not bitwise equal to any vLLM path probed so far. Claim levels, measurements and +limitations are in ``docs/operators/qwen3-next-rms-norm.md``. """ from __future__ import annotations @@ -100,8 +60,8 @@ class Qwen3NextRMSNormGatedOp: ``out = (x * rstd * weight) * silu(gate)``, with every multiply in fp32 and a single cast on the way out. This is the convention vLLM's ``RMSNormGated`` - uses with ``norm_before_gate=True``, which is what the RFC #428 L2 claim is - measured against. + uses with ``norm_before_gate=True``. Which gated convention is the strict + default is still open; see the operator page. Not a subclass of the plain op: it takes an extra tensor and its epilogue differs, so it is not a drop-in substitute for one. diff --git a/tests/check_qwen3_next_norm_providers.py b/tests/check_qwen3_next_norm_providers.py index 062052cfa..7086aa341 100644 --- a/tests/check_qwen3_next_norm_providers.py +++ b/tests/check_qwen3_next_norm_providers.py @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2026 RL-Kernel Contributors -"""Which vLLM gated-RMSNorm path is the strict provider, and how far apart are they. +"""How far apart vLLM's eager gated-RMSNorm paths are, and ours from each. Named ``check_`` rather than ``test_`` on purpose, following ``tests/distributed/check_*.py``: this module imports real vLLM, and @@ -16,13 +16,17 @@ provider is named, because vLLM ships several and they do not agree bitwise with each other. -This module pins two things so a vLLM upgrade cannot move them silently: +This module records two things so a vLLM upgrade cannot move them silently: -1. **Dispatch facts** -- which provider actually runs, asserted on the env - defaults and the registered ops rather than inferred from reading one branch. +1. **Provider facts** -- the GDN decode env defaults, and that ``RMSNormGated`` + has distinct ``forward_native`` and ``forward_cuda`` methods. It does NOT + determine which path vLLM dispatches at runtime: the checks below call each + method directly (eager), and vLLM's default compiled mode traces + ``forward_native`` into an inductor graph instead. 2. **The size of the gap** -- a seed sweep that asserts an upper bound on the - disagreement and on the mismatch rate. It deliberately does NOT assert - equality; the point is to keep the number honest, not to pretend it is zero. + disagreement and on the mismatch rate between the eager paths. The bounds are + provider-gap bounds, not ``tolerance_contract.json`` thresholds, and they + deliberately do NOT assert equality. Measured on 2x B200 (sm_100, torch 2.13.0+cu130, vllm 0.30.0), bf16, ``head_v_dim=128``, 512 rows, 40 seeds: @@ -101,21 +105,24 @@ def _disagreement(a: torch.Tensor, b: torch.Tensor) -> tuple[float, float]: # --------------------------------------------------------------------------- # -# 1. Dispatch facts -- which provider actually runs +# 1. Provider facts -- recorded, not a runtime dispatch check # --------------------------------------------------------------------------- # def test_custom_op_has_distinct_native_and_cuda_paths(vllm_config_ctx): - """`forward_native` is a reference; `forward_cuda` is what CustomOp dispatches.""" + """The two methods are distinct. Which one runs depends on the vLLM mode: eager + (``custom_ops="all"``) dispatches ``forward_cuda``; the default compiled mode + traces ``forward_native``. This test does not check that choice.""" norm = _make_norm() assert type(norm).forward_cuda is not type(norm).forward_native def test_gdn_decode_provider_env_defaults_are_recorded(): - """Pin the env defaults that decide which GDN decode kernel runs. + """Record the GDN decode env defaults. - These are what make ``fused_recurrent_gated_delta_rule_packed_decode`` (not - ``fused_sigmoid_gating_delta_rule_update``) the rollout decode path. If a - vLLM bump flips either default, the provider identity behind any L2 claim - changes, so this must fail loudly rather than drift. + This records the defaults only; it does not assert which kernel runs. For + Qwen3-Next the ``VLLM_GDN_DECODE_KERNEL="cuda"`` default does not take effect: + vLLM builds its GDN layers with ``gqa_interleaved_layout=True`` and falls back + to the Triton decode kernel. A change of either default still fails here, as a + prompt to re-derive the decode path. """ pytest.importorskip("vllm", reason="vLLM is required to identify the provider") import vllm.envs as envs @@ -141,12 +148,11 @@ def test_gdn_decode_provider_env_defaults_are_recorded(): @pytest.mark.parametrize( "dtype, max_abs, max_mismatch_rate", [ - # bf16 rounding absorbs most of the reduction-tree difference, so few - # elements move -- but each that does moves by a whole bf16 ULP. + # Provider-gap bounds, not contract thresholds. bf16 rounding absorbs most + # of the reduction-tree difference, so few elements move. (torch.bfloat16, 2e-2, 0.05), - # fp32 has nothing to absorb it: ~36% of elements differ, every one of - # them by an fp32 ULP. Bounding the rate here would be measuring the - # wrong thing; the magnitude is what says the two agree semantically. + # In fp32 about 36% of elements differ, so the rate is left unbounded and + # only the magnitude is bounded (no per-element ULP bound is asserted). (torch.float32, 1e-5, 1.0), ], ) @@ -196,6 +202,7 @@ def test_ours_tracks_each_vllm_path_within_bounds(vllm_config_ctx, path): abs_d, rate = _disagreement(ours.forward(x, weight, gate), reference) worst_abs, worst_rate = max(worst_abs, abs_d), max(worst_rate, rate) + # Provider-gap bounds, not contract thresholds. assert worst_abs <= 2e-2, f"worst |diff| vs {path} was {worst_abs:.3e}" assert worst_rate <= 0.05, f"mismatch rate vs {path} was {worst_rate:.3%}" diff --git a/tests/test_qwen3_next_norm.py b/tests/test_qwen3_next_norm.py index 9fdf02e73..a62d8410f 100644 --- a/tests/test_qwen3_next_norm.py +++ b/tests/test_qwen3_next_norm.py @@ -5,7 +5,8 @@ Claim levels exercised here (RFC #428 section 2.1): * L0 repeatable -- identical inputs reproduce bitwise identical outputs. - * L1 batch-invariant -- a row is unaffected by unrelated rows, padding or order. + * L1 batch-invariant -- a row is unaffected by slicing, concurrency and (for the + PyTorch reference) padding; packing and order are not exercised. L2 (train-rollout exact against vLLM) is NOT claimed by this file; it needs the rollout engine on the other side. @@ -22,6 +23,7 @@ import torch import torch.nn.functional as F +from rl_engine.kernels.gtest.tolerance import load_contract, resolve_tolerance from rl_engine.kernels.ops.pytorch.norm.qwen3_next_rms_norm import ( Qwen3NextRMSNormGatedHFOp, Qwen3NextRMSNormGatedOp, @@ -33,6 +35,16 @@ _HEAD_V_DIM = 128 # linear_value_head_dim -- the gated norm width _EPS = 1e-6 # rms_norm_eps +_CONTRACT = load_contract() + + +def _forward_tol(dtype: torch.dtype) -> dict[str, float]: + """C1 forward_accuracy row for the ``reduction`` op class -- no private thresholds.""" + spec = resolve_tolerance( + _CONTRACT, judgment="forward_accuracy", op_class="reduction", dtype=dtype + ) + return {"atol": spec.atol, "rtol": spec.rtol} + def _rand(shape, seed): g = torch.Generator().manual_seed(seed) @@ -277,7 +289,7 @@ def test_matches_upstream_formula_low_precision(dtype): w = _rand((_HIDDEN,), seed=22).to(dtype) got, ref = op.forward(x, w), _hf_rms_norm(x, w) assert got.dtype == ref.dtype == dtype - torch.testing.assert_close(got.float(), ref.float(), atol=2e-2, rtol=1.6e-2) + torch.testing.assert_close(got.float(), ref.float(), **_forward_tol(dtype)) @pytest.mark.parametrize("dtype", [torch.bfloat16, torch.float16]) @@ -289,7 +301,7 @@ def test_gated_hf_witness_low_precision(dtype): gate = _rand((4, 16, _HEAD_V_DIM), seed=25).to(dtype) got, ref = op.forward(x, w, gate), _hf_rms_norm_gated(x, w, gate) assert got.dtype == ref.dtype == dtype - torch.testing.assert_close(got.float(), ref.float(), atol=2e-2, rtol=1.6e-2) + torch.testing.assert_close(got.float(), ref.float(), **_forward_tol(dtype)) @pytest.mark.parametrize("dtype", [torch.bfloat16, torch.float16]) @@ -300,7 +312,7 @@ def test_gated_strict_low_precision(dtype): gate = _rand((4, 16, _HEAD_V_DIM), seed=25).to(dtype) got, ref = op.forward(x, w, gate), _vllm_rms_norm_gated(x, w, gate) assert got.dtype == ref.dtype == dtype - torch.testing.assert_close(got.float(), ref.float(), atol=2e-2, rtol=1.6e-2) + torch.testing.assert_close(got.float(), ref.float(), **_forward_tol(dtype)) # --------------------------------------------------------------------------- # @@ -421,7 +433,7 @@ def test_cuda_zero_centred_within_tolerance_of_golden(): w = torch.randn(_HIDDEN, device="cuda", dtype=torch.bfloat16) got = Qwen3NextRMSNormCudaOp().forward(x, w, eps=_EPS) ref = Qwen3NextRMSNormOp().forward_fp32(x, w, eps=_EPS) - torch.testing.assert_close(got.float(), ref, atol=2e-2, rtol=1.6e-2) + torch.testing.assert_close(got.float(), ref, **_forward_tol(torch.bfloat16)) @requires_cuda_rmsnorm From bec7e7adc01763c26dd7325689ed5f3b4ca06239 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Wed, 7 Oct 2026 16:35:28 +0000 Subject: [PATCH 08/15] fix(norm): reject stale RMSNorm bindings and enable GPU coverage Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- .github/workflows/ws1-gtest-gpu.yml | 6 +++ ci/run_ws1_gtest.sh | 1 + csrc/ops.cpp | 2 + rl_engine/_C.pyi | 3 ++ rl_engine/kernels/ops/cuda/norm/rmsnorm.py | 29 ++++++------ tests/test_qwen3_next_norm.py | 6 ++- tests/test_rms_norm.py | 51 +++++++++++++++++++--- 7 files changed, 77 insertions(+), 21 deletions(-) diff --git a/.github/workflows/ws1-gtest-gpu.yml b/.github/workflows/ws1-gtest-gpu.yml index 646d80bdf..f48d62382 100644 --- a/.github/workflows/ws1-gtest-gpu.yml +++ b/.github/workflows/ws1-gtest-gpu.yml @@ -12,6 +12,8 @@ on: pull_request: branches: [ main ] paths: + - "csrc/cuda/rmsnorm.cu" + - "csrc/ops.cpp" - "rl_engine/kernels/gtest/**" - "rl_engine/kernels/ops/**" - "rl_engine/testing/**" @@ -20,6 +22,7 @@ on: - "scripts/check_gradient_invariance.py" - "scripts/ws1_candidate_evidence.py" - "tests/test_ws1_*.py" + - "tests/test_qwen3_next_norm.py" - "tests/test_forward_invariance.py" - "tests/test_gradient_invariance.py" - "tests/test_four_judgment_matrix.py" @@ -30,6 +33,8 @@ on: push: branches: [ main ] paths: + - "csrc/cuda/rmsnorm.cu" + - "csrc/ops.cpp" - "rl_engine/kernels/gtest/**" - "rl_engine/kernels/ops/**" - "rl_engine/testing/**" @@ -38,6 +43,7 @@ on: - "scripts/check_gradient_invariance.py" - "scripts/ws1_candidate_evidence.py" - "tests/test_ws1_*.py" + - "tests/test_qwen3_next_norm.py" - "tests/test_forward_invariance.py" - "tests/test_gradient_invariance.py" - "tests/test_four_judgment_matrix.py" diff --git a/ci/run_ws1_gtest.sh b/ci/run_ws1_gtest.sh index 0e9b172cc..e4d8a36fa 100755 --- a/ci/run_ws1_gtest.sh +++ b/ci/run_ws1_gtest.sh @@ -19,6 +19,7 @@ echo "[ws1-gtest] interpreter=$PY out=$OUT" "$PY" -m pytest -q \ tests/test_ws1_gtest_gpu.py \ + tests/test_qwen3_next_norm.py \ tests/test_triton_batch_invariant_attention.py \ tests/test_four_judgment_matrix.py \ tests/test_ws1_candidate_evidence.py \ diff --git a/csrc/ops.cpp b/csrc/ops.cpp index 4e786e5b3..7ae1523f6 100644 --- a/csrc/ops.cpp +++ b/csrc/ops.cpp @@ -716,6 +716,8 @@ PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) { &det_gemm_db_transposed, "Batch-invariant deterministic GEMM backward in canonical [N,K] layout"); // registry RMSNorm + // API version 2 includes weight_offset in both entry points. + m.attr("rmsnorm_api_version") = 2; m.def("rmsnorm_forward", &rmsnorm_forward, "Batch-invariant RMSNorm forward CUDA", py::arg("x"), py::arg("weight"), py::arg("eps"), py::arg("weight_offset") = 0.0); diff --git a/rl_engine/_C.pyi b/rl_engine/_C.pyi index b911feaf7..225f997b6 100644 --- a/rl_engine/_C.pyi +++ b/rl_engine/_C.pyi @@ -256,6 +256,9 @@ def swiglu_backward( gate: torch.Tensor, up: torch.Tensor, ) -> list[torch.Tensor]: ... + +rmsnorm_api_version: int + def rmsnorm_forward( x: torch.Tensor, weight: torch.Tensor, diff --git a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py index af9a31358..a0da2ddd4 100644 --- a/rl_engine/kernels/ops/cuda/norm/rmsnorm.py +++ b/rl_engine/kernels/ops/cuda/norm/rmsnorm.py @@ -4,9 +4,11 @@ from rl_engine.kernels.ops.base import _C, _EXT_AVAILABLE from rl_engine.kernels.ops.vjp_fp32 import reduce_rows_fp32, rmsnorm_dweight_rows_fp32 +_RMSNORM_API_VERSION = 2 -def _require_cuda_symbols(what: str, *names: str) -> None: - """Raise when the compiled kernels backing ``what`` are missing. + +def _require_cuda_rmsnorm() -> None: + """Raise when the compiled RMSNorm bindings are missing or incompatible. The registry treats a backend whose construction raises as unavailable and falls through to the next candidate, so calling this from ``__init__`` is @@ -15,13 +17,21 @@ def _require_cuda_symbols(what: str, *names: str) -> None: activation ops. """ if not _EXT_AVAILABLE or _C is None: - raise RuntimeError(f"{what} requires the compiled rl_engine._C extension.") + raise RuntimeError("CUDA RMSNorm requires the compiled rl_engine._C extension.") + names = ("rmsnorm_forward", "rmsnorm_backward_dx") missing = [name for name in names if not hasattr(_C, name)] if missing: raise RuntimeError( - f"{what} symbols ({', '.join(missing)}) are not compiled into _C. " + f"CUDA RMSNorm symbols ({', '.join(missing)}) are not compiled into _C. " "Rebuild the extension with csrc/cuda/rmsnorm.cu." ) + api_version = getattr(_C, "rmsnorm_api_version", None) + if api_version != _RMSNORM_API_VERSION: + raise RuntimeError( + f"CUDA RMSNorm requires rl_engine._C RMSNorm API version {_RMSNORM_API_VERSION} " + f"(loaded {api_version!r}). Rebuild the extension with csrc/cuda/rmsnorm.cu " + "for weight_offset support." + ) class RMSNormCuda(torch.autograd.Function): @@ -46,6 +56,7 @@ def forward(ctx, x, weight, mask=None, eps=1e-6, weight_offset=0.0): Output: y: [T, H] """ + _require_cuda_rmsnorm() assert x.is_cuda, "x must be CUDA tensor" assert weight.is_cuda, "weight must be CUDA tensor" assert x.is_contiguous(), "x must be contiguous" @@ -53,10 +64,6 @@ def forward(ctx, x, weight, mask=None, eps=1e-6, weight_offset=0.0): assert x.dim() == 2, "x must be [T, H]" assert weight.dim() == 1, "weight must be [H]" assert x.shape[1] == weight.shape[0], "hidden size mismatch" - assert _EXT_AVAILABLE and hasattr( - _C, "rmsnorm_forward" - ), "RMSNorm CUDA extension is unavailable. Please rebuild with rmsnorm.cu." - if mask is None: mask = torch.ones((x.shape[0],), device=x.device, dtype=torch.bool) else: @@ -124,11 +131,7 @@ class RMSNormCudaOp: backward_impl = "cuda_rmsnorm_dx_declared_fp32_rowfold_dw" def __init__(self) -> None: - _require_cuda_symbols( - "CUDA RMSNorm", - "rmsnorm_forward", - "rmsnorm_backward_dx", - ) + _require_cuda_rmsnorm() #: Added to the weight in fp32 inside the kernel. Subclasses override it; #: 0.0 is the plain convention. diff --git a/tests/test_qwen3_next_norm.py b/tests/test_qwen3_next_norm.py index a62d8410f..d45670a7d 100644 --- a/tests/test_qwen3_next_norm.py +++ b/tests/test_qwen3_next_norm.py @@ -355,7 +355,11 @@ def test_gated_shape_mismatch_raises(): try: from rl_engine.kernels.ops.base import _C, _EXT_AVAILABLE - _CUDA_RMSNORM = _EXT_AVAILABLE and hasattr(_C, "rmsnorm_forward") + _CUDA_RMSNORM = ( + _EXT_AVAILABLE + and getattr(_C, "rmsnorm_api_version", None) == 2 + and all(hasattr(_C, name) for name in ("rmsnorm_forward", "rmsnorm_backward_dx")) + ) except ImportError: # pragma: no cover _CUDA_RMSNORM = False diff --git a/tests/test_rms_norm.py b/tests/test_rms_norm.py index b17a3f302..ec3046593 100644 --- a/tests/test_rms_norm.py +++ b/tests/test_rms_norm.py @@ -17,10 +17,11 @@ try: from rl_engine.kernels.ops.base import _C, _EXT_AVAILABLE - # The same two symbols RMSNormCudaOp.__init__ requires; a build that has them - # dispatches to the CUDA op, so the dispatch test must agree with that guard. - _HAS_CUDA_RMSNORM = _EXT_AVAILABLE and all( - hasattr(_C, name) for name in ("rmsnorm_forward", "rmsnorm_backward_dx") + # Keep dispatch expectations aligned with the constructor's capability guard. + _HAS_CUDA_RMSNORM = ( + _EXT_AVAILABLE + and getattr(_C, "rmsnorm_api_version", None) == 2 + and all(hasattr(_C, name) for name in ("rmsnorm_forward", "rmsnorm_backward_dx")) ) except ImportError: # pragma: no cover - import can fail when the extension is not built. _HAS_CUDA_RMSNORM = False @@ -263,7 +264,7 @@ def test_cuda_op_construction_fails_when_symbols_missing(monkeypatch): from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm class _WithoutRMSNorm: # a built extension that lacks the rmsnorm symbols - pass + rmsnorm_api_version = 2 monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", True) monkeypatch.setattr(cuda_rmsnorm, "_C", _WithoutRMSNorm()) @@ -291,12 +292,43 @@ def test_registry_falls_back_when_required_symbol_is_missing(monkeypatch, missin symbols = {name: object() for name in ("rmsnorm_forward", "rmsnorm_backward_dx")} del symbols[missing] + symbols["rmsnorm_api_version"] = 2 monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", True) monkeypatch.setattr(cuda_rmsnorm, "_C", SimpleNamespace(**symbols)) assert isinstance(KernelRegistry().get_op("rms_norm", device="cuda"), NativeRMSNormOp) -def test_registry_cuda_requires_only_used_symbols_and_cpu_stays_native(monkeypatch): +@pytest.mark.parametrize("api_version", [None, 1, 3]) +def test_cuda_rejects_incompatible_rmsnorm_api_before_dispatch(monkeypatch, api_version): + from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm + from rl_engine.kernels.registry import KernelRegistry + + class _LegacyRMSNorm: + def rmsnorm_forward(self, x, weight, eps): + pytest.fail("an incompatible extension must not be invoked") + + def rmsnorm_backward_dx(self, dy, x, weight, rstd): + pytest.fail("an incompatible extension must not be invoked") + + extension = _LegacyRMSNorm() + if api_version is not None: + extension.rmsnorm_api_version = api_version + monkeypatch.setattr(cuda_rmsnorm, "_EXT_AVAILABLE", True) + monkeypatch.setattr(cuda_rmsnorm, "_C", extension) + + for op_type in (cuda_rmsnorm.RMSNormCudaOp, cuda_rmsnorm.Qwen3NextRMSNormCudaOp): + with pytest.raises(RuntimeError, match="RMSNorm API version 2.*Rebuild"): + op_type() + + registry_op = KernelRegistry().get_op("rms_norm", device="cuda") + assert isinstance(registry_op, NativeRMSNormOp) + x, weight = torch.ones(2, 8), torch.ones(8) + assert torch.isfinite(registry_op(x, weight)).all() + with pytest.raises(RuntimeError, match="RMSNorm API version 2.*Rebuild"): + rmsnorm_cuda(x, weight, weight_offset=1.0) + + +def test_registry_cuda_requires_current_api_and_only_used_symbols(monkeypatch): from types import SimpleNamespace from rl_engine.kernels.ops.cuda.norm import rmsnorm as cuda_rmsnorm @@ -306,10 +338,15 @@ def test_registry_cuda_requires_only_used_symbols_and_cpu_stays_native(monkeypat monkeypatch.setattr( cuda_rmsnorm, "_C", - SimpleNamespace(rmsnorm_forward=object(), rmsnorm_backward_dx=object()), + SimpleNamespace( + rmsnorm_api_version=2, + rmsnorm_forward=object(), + rmsnorm_backward_dx=object(), + ), ) registry = KernelRegistry() assert isinstance(registry.get_op("rms_norm", device="cuda"), RMSNormCudaOp) + cuda_rmsnorm.Qwen3NextRMSNormCudaOp() assert isinstance(registry.get_op("rms_norm", device="cpu"), NativeRMSNormOp) From 53767ab89110fe53a70d4c6abcfff626b10f37b5 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Thu, 8 Oct 2026 17:27:59 +0000 Subject: [PATCH 09/15] feat(scripts): Qwen3-Next norm evidence runner vs existing implementations Compares the zero-centred RMSNorm CUDA op with the PyTorch reference, transformers, vLLM and FlashInfer (optional providers are skipped when absent): error vs an FP64 golden, row invariance (256 rows alone vs a 4096-row batch, three seeds, bitwise) and forward/backward latency. The plot script renders the report as one figure per op. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- scripts/plot_qwen3_next_norm_evidence.py | 117 ++++++++++ scripts/qwen3_next_norm_evidence.py | 276 +++++++++++++++++++++++ 2 files changed, 393 insertions(+) create mode 100644 scripts/plot_qwen3_next_norm_evidence.py create mode 100644 scripts/qwen3_next_norm_evidence.py diff --git a/scripts/plot_qwen3_next_norm_evidence.py b/scripts/plot_qwen3_next_norm_evidence.py new file mode 100644 index 000000000..54dab1a67 --- /dev/null +++ b/scripts/plot_qwen3_next_norm_evidence.py @@ -0,0 +1,117 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2026 RL-Kernel Contributors + +"""Plot a report from scripts/qwen3_next_norm_evidence.py: one 2x2 figure per op. + + python scripts/plot_qwen3_next_norm_evidence.py report.json # figure[-].png beside it +""" + +from __future__ import annotations + +import json +import sys +from pathlib import Path + +import matplotlib + +matplotlib.use("Agg") +import matplotlib.pyplot as plt # noqa: E402 + +COLORS = ["#2a6fdb", "#7a7a7a", "#e07b39", "#3aa676", "#9b59b6", "#c0392b"] + + +def _short(name: str) -> str: + return name.replace(" (forward only)", "*") + + +def plot_op(op: str, data: dict, title: str, out: Path) -> None: + names = list(data["row_invariance"]) + color = {n: COLORS[i % len(COLORS)] for i, n in enumerate(names)} + fig, axes = plt.subplots(2, 2, figsize=(13, 9)) + fig.suptitle(title, fontsize=13) + + for ax, key, label in ( + (axes[0, 0], "forward_us", "forward latency"), + (axes[0, 1], "backward_us", "backward latency (training-capable only)"), + ): + for name in names: + rows = sorted(int(r) for r in data["latency"][name]) + ys = [data["latency"][name][str(r)].get(key) for r in rows] + if all(y is None for y in ys): + continue + ax.plot(rows, ys, "o-", color=color[name], label=_short(name)) + ax.set_xscale("log", base=2) + ax.set_yscale("log") + ax.set_xlabel("rows") + ax.set_ylabel("µs (median)") + ax.set_title(label) + ax.grid(True, which="both", alpha=0.3) + ax.legend(fontsize=8) + + ax = axes[1, 0] + acc = data["accuracy"][max(data["accuracy"], key=int)] + metrics = [ + ("forward_max_abs", "forward max |err|"), + ("dx_max_abs_over_absmax", "dx max |err| / max|dx|"), + ("dweight_max_abs_over_absmax", "dweight max |err| / max|dw|"), + ] + width = 0.8 / len(names) + for i, name in enumerate(names): + vals = [acc[name].get(m) for m, _ in metrics] + xs = [j + (i - (len(names) - 1) / 2) * width for j in range(len(metrics))] + ax.bar( + [x for x, v in zip(xs, vals) if v is not None], + [v for v in vals if v is not None], + width, + color=color[name], + label=_short(name), + ) + ax.set_xticks(range(len(metrics)), [label for _, label in metrics], fontsize=9) + ax.set_yscale("log") + ax.set_title(f"error vs FP64 golden ({max(data['accuracy'], key=int)} rows, BF16)") + ax.grid(True, axis="y", alpha=0.3) + ax.legend(fontsize=8) + + ax = axes[1, 1] + bi = data["row_invariance"] + checked = next(iter(bi.values()))["rows_checked"] + ys = range(len(names)) + fwd = [bi[n]["forward_rows_differing"] for n in names] + dx = [ + bi[n]["dx_rows_differing"] if bi[n]["dx_rows_differing"] is not None else 0 for n in names + ] + ax.barh([y - 0.2 for y in ys], fwd, 0.4, color="#2a6fdb", label="forward") + ax.barh([y + 0.2 for y in ys], dx, 0.4, color="#e07b39", label="dx") + for y, n, f, d in zip(ys, names, fwd, dx): + no_bwd = bi[n]["dx_rows_differing"] is None + ax.text(max(f, d) + 0.2, y, f"{f} / {'n/a' if no_bwd else d}", va="center", fontsize=8) + ax.set_yticks(list(ys), [_short(n) for n in names], fontsize=8) + ax.invert_yaxis() + ax.set_xlabel(f"rows differing (of {checked}; row alone vs inside a batch, bitwise)") + ax.set_title("row invariance (0 = batch-invariant)") + ax.legend(fontsize=8) + ax.grid(True, axis="x", alpha=0.3) + + fig.text(0.01, 0.005, "* forward only (no backward)", fontsize=8) + fig.tight_layout(rect=(0, 0.02, 1, 0.96)) + fig.savefig(out, dpi=130) + print(f"wrote {out}") + + +def main() -> None: + path = Path(sys.argv[1]) + report = json.loads(path.read_text()) + env = report["environment"] + ops = report["ops"] + for op, data in ops.items(): + name = "figure.png" if len(ops) == 1 else f"figure-{op}.png" + title = ( + f"Qwen3-Next {op.replace('_', ' ')} — {env['gpu']}, hidden {report['hidden']}, " + f"BF16, commit {report['git_commit'][:7]}" + ) + plot_op(op, data, title, path.parent / name) + + +if __name__ == "__main__": + main() diff --git a/scripts/qwen3_next_norm_evidence.py b/scripts/qwen3_next_norm_evidence.py new file mode 100644 index 000000000..27a063df6 --- /dev/null +++ b/scripts/qwen3_next_norm_evidence.py @@ -0,0 +1,276 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2026 RL-Kernel Contributors + +"""Accuracy, row invariance and latency of the Qwen3-Next norms vs existing implementations. + +Writes one JSON report (RFC #428, reuse rule of #420): every candidate is compared with +an FP64 golden, checked for row invariance (a row computed alone vs inside a batch, +bitwise), and timed. Optional providers (transformers, vLLM, FlashInfer) are skipped +when they are not installed; the report says which ran. + + python scripts/qwen3_next_norm_evidence.py --out report.json + python scripts/plot_qwen3_next_norm_evidence.py report.json +""" + +from __future__ import annotations + +import argparse +import json +import platform +import statistics +import subprocess +import sys +from pathlib import Path +from typing import Any, Callable + +import torch + +REPO_ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(REPO_ROOT)) + +from rl_engine.kernels.ops.cuda.norm.rmsnorm import Qwen3NextRMSNormCudaOp # noqa: E402 +from rl_engine.kernels.ops.pytorch.norm.qwen3_next_rms_norm import Qwen3NextRMSNormOp # noqa: E402 + +EPS = 1e-6 +HIDDEN = 2048 # Qwen3-Next hidden size (decoder and final norms) +TIMED_ROWS = (1024, 4096, 16384, 65536) + + +# --------------------------------------------------------------------------- # +# Candidates: name -> (forward fn(x, w) -> y, has_backward) +# --------------------------------------------------------------------------- # + + +def zero_centred_candidates() -> dict[str, dict[str, Any]]: + cands: dict[str, dict[str, Any]] = { + "rl-kernel CUDA": {"fn": Qwen3NextRMSNormCudaOp(), "backward": True}, + "rl-kernel PyTorch reference": {"fn": Qwen3NextRMSNormOp(), "backward": True}, + } + try: + from transformers.models.qwen3_next.modeling_qwen3_next import Qwen3NextRMSNorm + + module = Qwen3NextRMSNorm(HIDDEN, eps=EPS).cuda() + + def hf(x, w, module=module): + return torch.func.functional_call(module, {"weight": w}, (x,)) + + cands["transformers Qwen3NextRMSNorm"] = {"fn": hf, "backward": True} + except ImportError: + pass + try: + from vllm.config import VllmConfig, set_current_vllm_config + + with set_current_vllm_config(VllmConfig()): + from vllm.model_executor.layers.layernorm import GemmaRMSNorm + + gemma = GemmaRMSNorm(HIDDEN, eps=EPS).cuda() + + def vllm_fwd(x, w, gemma=gemma): + gemma.weight.data = w.detach() + return gemma.forward_cuda(x) + + cands["vLLM GemmaRMSNorm (forward only)"] = {"fn": vllm_fwd, "backward": False} + except ImportError: + pass + try: + import flashinfer + + cands["FlashInfer gemma_rmsnorm (forward only)"] = { + "fn": lambda x, w: flashinfer.norm.gemma_rmsnorm(x, w, EPS), + "backward": False, + } + except ImportError: + pass + return cands + + +def zero_centred_golden(x: torch.Tensor, w: torch.Tensor) -> torch.Tensor: + x64 = x.double() + return x64 * torch.rsqrt(x64.square().mean(-1, keepdim=True) + EPS) * (1.0 + w.double()) + + +# --------------------------------------------------------------------------- # +# Measurements +# --------------------------------------------------------------------------- # + + +def _inputs(rows: int, seed: int, dtype=torch.bfloat16): + g = torch.Generator(device="cuda").manual_seed(seed) + x = (torch.randn(rows, HIDDEN, device="cuda", generator=g) * 2).to(dtype) + w = (torch.randn(HIDDEN, device="cuda", generator=g) * 0.1).to(dtype) + up = torch.randn(rows, HIDDEN, device="cuda", generator=g).to(dtype) + return x, w, up + + +def _grads(fn, x, w, up, dtype=None): + xl = (x if dtype is None else x.to(dtype)).detach().clone().requires_grad_(True) + wl = (w if dtype is None else w.to(dtype)).detach().clone().requires_grad_(True) + out = fn(xl, wl) + out.backward(up if dtype is None else up.to(dtype)) + return out.detach(), xl.grad, wl.grad + + +def accuracy(cands, golden, rows: int, seed: int) -> dict[str, Any]: + x, w, up = _inputs(rows, seed) + ref_out, ref_dx, ref_dw = _grads(golden, x, w, up, torch.float64) + result = {} + for name, c in cands.items(): + entry: dict[str, Any] = {} + if c["backward"]: + out, dx, dw = _grads(c["fn"], x, w, up) + for key, got, ref in (("dx", dx, ref_dx), ("dweight", dw, ref_dw)): + err = (got.double() - ref).abs().max().item() + entry[f"{key}_max_abs_over_absmax"] = err / ref.abs().max().item() + else: + with torch.no_grad(): + out = c["fn"](x, w) + err = (out.double() - ref_out).abs() + entry["forward_max_abs"] = err.max().item() + entry["forward_correctly_rounded_fraction"] = ( + (out == ref_out.to(out.dtype)).float().mean().item() + ) + result[name] = entry + return result + + +def row_invariance(cands, seeds=(3, 4, 5), rows: int = 4096, step: int = 16) -> dict[str, Any]: + """256 rows computed alone vs the same rows inside a batch, bitwise.""" + + result = {} + for name, c in cands.items(): + fwd_bad = dx_bad = checked = 0 + for seed in seeds: + x, w, up = _inputs(rows, seed) + if c["backward"]: + full_out, full_dx, _ = _grads(c["fn"], x, w, up) + else: + with torch.no_grad(): + full_out = c["fn"](x, w) + for i in range(0, rows, step): + sl = slice(i, i + 1) + if c["backward"]: + out, dx, _ = _grads(c["fn"], x[sl], w, up[sl]) + dx_bad += not torch.equal(dx[0], full_dx[i]) + else: + with torch.no_grad(): + out = c["fn"](x[sl], w) + fwd_bad += not torch.equal(out[0], full_out[i]) + checked += 1 + result[name] = { + "rows_checked": checked, + "forward_rows_differing": fwd_bad, + "dx_rows_differing": dx_bad if c["backward"] else None, + "batch_rows": rows, + "seeds": list(seeds), + } + return result + + +def _time_us(fn: Callable[[], Any], warmup: int = 10, iters: int = 50) -> float: + for _ in range(warmup): + fn() + torch.cuda.synchronize() + samples = [] + for _ in range(iters): + start, end = torch.cuda.Event(enable_timing=True), torch.cuda.Event(enable_timing=True) + start.record() + fn() + end.record() + end.synchronize() + samples.append(start.elapsed_time(end) * 1e3) + return statistics.median(samples) + + +def latency(cands, rows_list=TIMED_ROWS) -> dict[str, Any]: + result: dict[str, Any] = {name: {} for name in cands} + for rows in rows_list: + x, w, up = _inputs(rows, seed=11) + for name, c in cands.items(): + row: dict[str, float] = {} + with torch.no_grad(): + row["forward_us"] = _time_us(lambda f=c["fn"]: f(x, w)) + if c["backward"]: + xl = x.detach().clone().requires_grad_(True) + wl = w.detach().clone().requires_grad_(True) + out = c["fn"](xl, wl) + row["backward_us"] = _time_us( + lambda o=out: torch.autograd.grad(o, (xl, wl), up, retain_graph=True) + ) + result[name][str(rows)] = row + return result + + +# --------------------------------------------------------------------------- # + + +def _git(*args: str) -> str: + try: + return subprocess.check_output(["git", *args], cwd=REPO_ROOT, text=True).strip() + except (OSError, subprocess.CalledProcessError): + return "" + + +def environment() -> dict[str, Any]: + env = { + "gpu": torch.cuda.get_device_name(), + "capability": list(torch.cuda.get_device_capability()), + "torch": torch.__version__, + "cuda": torch.version.cuda, + "python": platform.python_version(), + } + for mod in ("transformers", "vllm", "flashinfer"): + try: + env[mod] = __import__(mod).__version__ + except ImportError: + env[mod] = None + return env + + +def run_op(name: str, cands, golden) -> dict[str, Any]: + print(f"[{name}] candidates: {', '.join(cands)}", flush=True) + report = { + "accuracy": {str(r): accuracy(cands, golden, r, seed=r) for r in (257, 4096)}, + "row_invariance": row_invariance(cands), + "latency": latency(cands), + } + for cand, entry in report["row_invariance"].items(): + print(f" BI {cand}: {entry}", flush=True) + return report + + +def build_report(ops: dict[str, tuple[Callable, Callable]]) -> dict[str, Any]: + torch.backends.cuda.matmul.allow_tf32 = False + report = { + "kind": "qwen3_next_norm_evidence", + "rfc": "RL-Align/RL-Kernel#428", + "git_commit": _git("rev-parse", "HEAD") or "unknown", + "git_dirty": bool(_git("status", "--porcelain", "--untracked-files=no")), + "environment": environment(), + "hidden": HIDDEN, + "eps": EPS, + "dtype": "bfloat16", + "ops": {}, + } + for name, (make_cands, golden) in ops.items(): + report["ops"][name] = run_op(name, make_cands(), golden) + return report + + +OPS = {"zero_centred_rmsnorm": (zero_centred_candidates, zero_centred_golden)} + + +def main() -> None: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--out", type=Path, required=True) + args = parser.parse_args() + if not torch.cuda.is_available(): + raise SystemExit("needs a CUDA device") + report = build_report(OPS) + args.out.parent.mkdir(parents=True, exist_ok=True) + args.out.write_text(json.dumps(report, indent=2) + "\n") + print(f"wrote {args.out} (commit {report['git_commit'][:7]}, dirty={report['git_dirty']})") + + +if __name__ == "__main__": + main() From 3d0bae7174c09a133ea1288d820b63e4a7db8f57 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Thu, 8 Oct 2026 18:11:14 +0000 Subject: [PATCH 10/15] fix(scripts): readable Qwen3-Next norm evidence figure layout Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- scripts/plot_qwen3_next_norm_evidence.py | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/scripts/plot_qwen3_next_norm_evidence.py b/scripts/plot_qwen3_next_norm_evidence.py index 54dab1a67..41c444100 100644 --- a/scripts/plot_qwen3_next_norm_evidence.py +++ b/scripts/plot_qwen3_next_norm_evidence.py @@ -22,13 +22,13 @@ def _short(name: str) -> str: - return name.replace(" (forward only)", "*") + return name.replace(" (forward only)", "*").replace(" (cast-first)", "\n(cast-first)") def plot_op(op: str, data: dict, title: str, out: Path) -> None: names = list(data["row_invariance"]) color = {n: COLORS[i % len(COLORS)] for i, n in enumerate(names)} - fig, axes = plt.subplots(2, 2, figsize=(13, 9)) + fig, axes = plt.subplots(2, 2, figsize=(14, 10), layout="constrained") fig.suptitle(title, fontsize=13) for ax, key, label in ( @@ -52,10 +52,12 @@ def plot_op(op: str, data: dict, title: str, out: Path) -> None: ax = axes[1, 0] acc = data["accuracy"][max(data["accuracy"], key=int)] metrics = [ - ("forward_max_abs", "forward max |err|"), - ("dx_max_abs_over_absmax", "dx max |err| / max|dx|"), - ("dweight_max_abs_over_absmax", "dweight max |err| / max|dw|"), + ("forward_max_abs", "forward\nmax |err|"), + ("dx_max_abs_over_absmax", "dx\nmax |err| / max"), + ("dweight_max_abs_over_absmax", "dweight\nmax |err| / max"), + ("dgate_max_abs_over_absmax", "dgate\nmax |err| / max"), ] + metrics = [m for m in metrics if any(acc[n].get(m[0]) is not None for n in names)] width = 0.8 / len(names) for i, name in enumerate(names): vals = [acc[name].get(m) for m, _ in metrics] @@ -87,14 +89,13 @@ def plot_op(op: str, data: dict, title: str, out: Path) -> None: no_bwd = bi[n]["dx_rows_differing"] is None ax.text(max(f, d) + 0.2, y, f"{f} / {'n/a' if no_bwd else d}", va="center", fontsize=8) ax.set_yticks(list(ys), [_short(n) for n in names], fontsize=8) + ax.set_xlim(0, max(3, max(fwd + dx) * 1.4)) ax.invert_yaxis() ax.set_xlabel(f"rows differing (of {checked}; row alone vs inside a batch, bitwise)") ax.set_title("row invariance (0 = batch-invariant)") ax.legend(fontsize=8) ax.grid(True, axis="x", alpha=0.3) - fig.text(0.01, 0.005, "* forward only (no backward)", fontsize=8) - fig.tight_layout(rect=(0, 0.02, 1, 0.96)) fig.savefig(out, dpi=130) print(f"wrote {out}") @@ -106,9 +107,10 @@ def main() -> None: ops = report["ops"] for op, data in ops.items(): name = "figure.png" if len(ops) == 1 else f"figure-{op}.png" + hidden = data.get("hidden", report.get("hidden")) title = ( - f"Qwen3-Next {op.replace('_', ' ')} — {env['gpu']}, hidden {report['hidden']}, " - f"BF16, commit {report['git_commit'][:7]}" + f"Qwen3-Next {op.replace('_', ' ')} — {env['gpu']}, hidden {hidden}, " + f"BF16, commit {report['git_commit'][:7]} (* forward only)" ) plot_op(op, data, title, path.parent / name) From ba467508cb935d4049552436c4beef2a60c1a75f Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Thu, 8 Oct 2026 18:32:22 +0000 Subject: [PATCH 11/15] docs(norm): zero-centred RMSNorm evidence vs existing implementations on B200 Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- docs/operators/qwen3-next-rms-norm.md | 28 +++ .../qwen3-next-rms-norm-b200/figure.png | Bin 0 -> 241252 bytes .../qwen3-next-rms-norm-b200/report.json | 225 ++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 docs/usage/evidence/qwen3-next-rms-norm-b200/figure.png create mode 100644 docs/usage/evidence/qwen3-next-rms-norm-b200/report.json diff --git a/docs/operators/qwen3-next-rms-norm.md b/docs/operators/qwen3-next-rms-norm.md index 81fdde9b3..ede972b3a 100644 --- a/docs/operators/qwen3-next-rms-norm.md +++ b/docs/operators/qwen3-next-rms-norm.md @@ -98,6 +98,34 @@ The CUDA path reuses the existing `rmsnorm_fwd_kernel` reduction (`block_reduce_sum` over `choose_threads(H)`), so the offset costs one fp32 add per element and no extra memory traffic. +## Evidence + +![zero-centred RMSNorm vs existing implementations on B200](../usage/evidence/qwen3-next-rms-norm-b200/figure.png) + +[`report.json`](../usage/evidence/qwen3-next-rms-norm-b200/report.json) was written by +`scripts/qwen3_next_norm_evidence.py` from a clean tree at `3d0bae7`, on an otherwise idle +B200 (torch 2.13.0+cu130, transformers 5.17.0, vLLM 0.30.0, FlashInfer 0.6.18). Hidden 2048, +BF16. + +| | rl-kernel CUDA | PyTorch reference | transformers | vLLM `GemmaRMSNorm`* | FlashInfer `gemma_rmsnorm`* | +|---|---|---|---|---|---| +| rows differing alone vs in a batch, forward / `dx` (of 768) | **0 / 0** | 0 / 12 | 2 / 11 | 2 / n/a | 0 / n/a | +| forward, 65536 rows | 425 µs | 2148 µs | 1449 µs | 1449 µs | **90 µs** | +| backward, 65536 rows | 30.9 ms | **3.0 ms** | 3.1 ms | n/a | n/a | + +\* forward only, no backward. + +- **Accuracy is the same for every implementation:** forward max error 1.56e-2 against the + FP64 golden (BF16 output rounding; 99.999% of elements correctly rounded), `dx` and + `dweight` within 2.8e-3 and 2.1e-3 of their maximum. +- **Row invariance:** only this op and FlashInfer give every row the same bits alone and in a + batch; FlashInfer has no backward. transformers and vLLM differ on 2 forward rows in 768. +- **The backward is about 10× slower than transformers at 65536 rows.** `dweight` is folded + over rows in ascending order by `reduce_rows_fp32_left_fold`, one thread per column, so + that the batch `dweight` equals the in-order sum of single-row contributions bitwise (the + gradient-invariance contract's singleton-aggregate check). That serial fold over rows is + the cost; a faster tree fold would not pass that check. + ## Tests ```bash diff --git a/docs/usage/evidence/qwen3-next-rms-norm-b200/figure.png b/docs/usage/evidence/qwen3-next-rms-norm-b200/figure.png new file mode 100644 index 0000000000000000000000000000000000000000..a408aff9c5b251764da2c9a76b1b5bb69a61366f GIT binary patch literal 241252 zcmce;cRZH;-#>n$VKk6cAyKk-8D(TAWlLsO(y%2n6%v(QL_(Q`NTG~6BSHv8GNP== z-mBm9xUTzi|L*(u`2G9+{&9V-&*kAf9mo54zhAHCdL6fPPikzX-9<|xk+vSwRMjVu zHnWpR8=0s#;U@zY4&C^doQIl;hk^514=-ysd(sJO50{J19v2;LxGvkfxjQ;LNs5Sz zi%1A@o%8T;ahDSnz4YI|A>!=jAR2gQ9A84BanU^OP9p7CC;p+>94i|{q9BousU9`F zk~G%sWx~|nzIk$@C7g?kFN|71t>DbY!`uRCA1rO!JJLSHv)vK@aL%S)$9AH;xPwQ% z`g%vTh=2fXn*N5PBmPY*nsb+^iQ_YRGi~i|ne!94LB}u`5 zSFuw!IZ@g7_MmoLmWHf>c-*NUT!ohY!adG0o#MGDN#6}~*yk?Qd+S>Bgh zL}Xhyt7u4g`0;CBPcgmrnz&n4r8?IAhSk{EINf-gvCHP|oK?$nqo31{v#!pz>ZDt+ z%eoIXTzm9rPsYiIVVv?lv6o#t95iKWNGYfCEf>e%OfZSCGBRG*d#p}D^7HdcdHnc> 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"forward_correctly_rounded_fraction": 0.9999927282333374 + }, + "transformers Qwen3NextRMSNorm": { + "dx_max_abs_over_absmax": 0.0027934846392837836, + "dweight_max_abs_over_absmax": 0.002058919545322908, + "forward_max_abs": 0.015599696412158082, + "forward_correctly_rounded_fraction": 0.9999921321868896 + }, + "vLLM GemmaRMSNorm (forward only)": { + "forward_max_abs": 0.015599696412158082, + "forward_correctly_rounded_fraction": 0.9999921321868896 + }, + "FlashInfer gemma_rmsnorm (forward only)": { + "forward_max_abs": 0.015599696412158082, + "forward_correctly_rounded_fraction": 0.999992847442627 + } + } + }, + "row_invariance": { + "rl-kernel CUDA": { + "rows_checked": 768, + "forward_rows_differing": 0, + "dx_rows_differing": 0, + "batch_rows": 4096, + "seeds": [ + 3, + 4, + 5 + ] + }, + "rl-kernel PyTorch reference": { + "rows_checked": 768, + "forward_rows_differing": 0, + "dx_rows_differing": 12, + "batch_rows": 4096, + "seeds": [ + 3, + 4, + 5 + ] + }, + "transformers Qwen3NextRMSNorm": { + "rows_checked": 768, + "forward_rows_differing": 2, + "dx_rows_differing": 11, + "batch_rows": 4096, + "seeds": [ + 3, + 4, + 5 + ] + }, + "vLLM GemmaRMSNorm (forward only)": { + "rows_checked": 768, + "forward_rows_differing": 2, + "dx_rows_differing": null, + "batch_rows": 4096, + "seeds": [ + 3, + 4, + 5 + ] + }, + "FlashInfer gemma_rmsnorm (forward only)": { + "rows_checked": 768, + "forward_rows_differing": 0, + "dx_rows_differing": null, + "batch_rows": 4096, + "seeds": [ + 3, + 4, + 5 + ] + } + }, + "latency": { + "rl-kernel CUDA": { + "1024": { + "forward_us": 24.70399998128414, + "backward_us": 568.7519907951355 + }, + "4096": { + "forward_us": 39.16800022125244, + "backward_us": 1259.3119740486145 + }, + "16384": { + "forward_us": 122.36800044775009, + "backward_us": 7879.024028778076 + }, + "65536": { + "forward_us": 425.80799758434296, + "backward_us": 30937.551498413086 + } + }, + "rl-kernel PyTorch reference": { + "1024": { + "forward_us": 70.54400071501732, + "backward_us": 644.7039842605591 + }, + "4096": { + "forward_us": 155.90400248765945, + "backward_us": 624.2719888687134 + }, + "16384": { + "forward_us": 577.5039792060852, + "backward_us": 986.7520034313202 + }, + "65536": { + "forward_us": 2148.0319499969482, + "backward_us": 2990.224003791809 + } + }, + "transformers Qwen3NextRMSNorm": { + "1024": { + "forward_us": 69.34399902820587, + "backward_us": 608.5599958896637 + }, + "4096": { + "forward_us": 117.3119992017746, + "backward_us": 606.3359975814819 + }, + "16384": { + "forward_us": 407.50400722026825, + "backward_us": 1027.888000011444 + }, + "65536": { + "forward_us": 1449.4240283966064, + "backward_us": 3144.6080207824707 + } + }, + "vLLM GemmaRMSNorm (forward only)": { + "1024": { + "forward_us": 65.61600044369698 + }, + "4096": { + "forward_us": 118.40000003576279 + }, + "16384": { + "forward_us": 405.90400993824005 + }, + "65536": { + "forward_us": 1449.6000409126282 + } + }, + "FlashInfer gemma_rmsnorm (forward only)": { + "1024": { + "forward_us": 14.448000118136406 + }, + "4096": { + "forward_us": 16.24000072479248 + }, + "16384": { + "forward_us": 32.207999378442764 + }, + "65536": { + "forward_us": 90.55999666452408 + } + } + } + } + } +} From 904d6fc577fbdf002d587b96442426f7aebe1969 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Thu, 8 Oct 2026 22:43:59 +0000 Subject: [PATCH 12/15] feat(scripts): Qwen3-Next norm reuse check against existing implementations Measures the CUDA norm next to transformers, vLLM, FlashInfer, Liger, FLA, Transformer Engine and Megatron-LM, whichever import: batch invariance of every row (plus full workload batch vs covering sub-batches and a dense size sweep), accuracy against FP64 and latency, and this repository's C3/C4 gates run unchanged with the CUDA candidate swapped for each implementation (kept the op's FP32 dweight contributions, so the singleton-aggregate check is like for like). The gate part runs where the Qwen3-Next gate manifest exists. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- scripts/qwen3_next_norm_reuse_check.py | 678 +++++++++++++++++++++++++ 1 file changed, 678 insertions(+) create mode 100644 scripts/qwen3_next_norm_reuse_check.py diff --git a/scripts/qwen3_next_norm_reuse_check.py b/scripts/qwen3_next_norm_reuse_check.py new file mode 100644 index 000000000..3b5eded28 --- /dev/null +++ b/scripts/qwen3_next_norm_reuse_check.py @@ -0,0 +1,678 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2026 RL-Kernel Contributors + +"""Compare a Qwen3-Next norm with existing implementations: batch invariance, accuracy, gates. + +Checks, for the rl-kernel CUDA op and every existing implementation that imports here +(transformers, vLLM, FlashInfer, Liger, FLA, Transformer Engine, Megatron-LM from a source +tree): + +* ``bi``: bitwise batch invariance of the forward and the row gradients, and repeatability of + ``dweight``: every row computed alone vs inside full batches of three sizes (seeds 3-5); + the full workload-size batch vs sub-batches covering every row; eight probe rows at the + front, middle and back of batches of every size 1..9 and 2^k - 1, 2^k, 2^k + 1. Sparse probes + miss row-specific and large-batch dependence, which is why every row is checked. +* ``perf``: accuracy against FP64 (forward: fraction equal to the correctly rounded FP64 result; + gradients: max|err| / max|ref|) and median CUDA-event latency at the workload size. +* ``gates``: this repository's own C3/C4 gates (``scripts/check_forward_invariance.py``, + ``scripts/check_gradient_invariance.py`` with ``qwen3_next_norm_manifest.json``, the + arguments ``ci/run_ws1_gtest.sh`` uses), unchanged, with the CUDA candidate replaced by a + subclass of the rl-kernel op whose forward and backward call the other library. The subclass + keeps the op's ``parameter_vjp_contributions_fp32``, so the singleton-aggregate check + compares that library's ``dweight`` with the same FP32 row contributions. + + python scripts/qwen3_next_norm_reuse_check.py --op qwen3_next_rms_norm \\ + --out docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json \\ + [--checks bi,perf,gates] [--megatron-src /path/to/Megatron-LM] [--quick] + +Run on a clean tree on an otherwise idle GPU; the report records the commit, the tree state and +every library version. A figure is written next to the report when matplotlib is available. +""" + +from __future__ import annotations + +import argparse +import importlib.metadata as md +import json +import os +import statistics +import subprocess +import sys +from pathlib import Path +from typing import Any + +REPO_ROOT = Path(__file__).resolve().parents[1] +sys.path.insert(0, str(REPO_ROOT)) + +import torch # noqa: E402 +import torch.nn.functional as F # noqa: E402 + +DEV, EPS, DT = "cuda", 1e-6, torch.bfloat16 +SHAPES = { + # op: (hidden, all-rows batch sizes, full batch, covering sub-batch sizes, perf rows) + "qwen3_next_rms_norm": (2048, (64, 257, 2048), 65536, (1, 7, 2048, 4097, 32768), 65536), + "rms_norm_gated": (128, (64, 257, 4097), 262144, (1, 7, 4097, 65536, 131072), 262144), +} +LIBS = ("torch", "triton", "transformers", "vllm", "flashinfer-python", "liger-kernel", "fla-core") +LIBS += ("transformer_engine", "megatron-core") +MANIFEST = "rl_engine/testing/qwen3_next_norm_manifest.json" + + +def _version(name: str) -> str | None: + try: + return md.version(name) + except md.PackageNotFoundError: + return None + + +# --------------------------------------------------------------------------- # +# Candidates: fn(x, w) for the zero-centred norm, fn(x, z, w) for the gated norm +# --------------------------------------------------------------------------- # + + +def _vllm_module(build): + from vllm.config import VllmConfig, set_current_vllm_config + + with set_current_vllm_config(VllmConfig()): + return build() + + +def _c1_candidates(hidden: int) -> list[tuple[str, Any]]: + def ours(): + from rl_engine.kernels.ops.cuda.norm.rmsnorm import Qwen3NextRMSNormCudaOp + + o = Qwen3NextRMSNormCudaOp() + return "rl-kernel Qwen3NextRMSNormCudaOp", lambda x, w: o(x, w, eps=EPS), "full" + + def reference(): + from rl_engine.kernels.ops.pytorch.norm.qwen3_next_rms_norm import Qwen3NextRMSNormOp + + o = Qwen3NextRMSNormOp() + return "rl-kernel PyTorch reference", lambda x, w: o(x, w, eps=EPS), "full" + + def transformers(): + from transformers.models.qwen3_next.modeling_qwen3_next import Qwen3NextRMSNorm + + m = Qwen3NextRMSNorm(hidden, eps=EPS).to(DEV, DT) + + def fn(x, w): + return torch.func.functional_call(m, {"weight": w}, (x,)) + + return f"transformers {_version('transformers')} Qwen3NextRMSNorm", fn, "full" + + def liger(): + from liger_kernel.ops.rms_norm import LigerRMSNormFunction + + def fn(x, w): + return LigerRMSNormFunction.apply(x, w, EPS, 1.0, "gemma", False) + + return f"Liger {_version('liger-kernel')} RMSNorm, offset 1, gemma", fn, "full" + + def fla(): + from fla.modules.layernorm import rms_norm + + def fn(x, w): + return rms_norm(x, (1.0 + w.float()).to(x.dtype), None, eps=EPS) + + return f"FLA {_version('fla-core')} rms_norm, weight passed as 1 + w", fn, "full" + + def te(): + import transformer_engine.pytorch as te_ + + m = te_.RMSNorm(hidden, eps=EPS, zero_centered_gamma=True, params_dtype=DT, device=DEV) + + def fn(x, w): + # TE's backward reads its own parameter, so copy w in (functional_call gives + # a wrong dx); dweight is then TE's parameter gradient and is not checked. + with torch.no_grad(): + m.weight.copy_(w) + return m(x) + + return f"TE {_version('transformer_engine')} RMSNorm(zero_centered_gamma)", fn, "x-only" + + def megatron(): + from megatron.core.transformer.custom_layers.batch_invariant_kernels import ( + BatchInvariantRMSNormFn, + ) + + def fn(x, w): + return BatchInvariantRMSNormFn.apply(x, w, EPS, True) + + return "Megatron BatchInvariantRMSNormFn(zero_centered_gamma=True)", fn, "full" + + def flashinfer(): + import flashinfer as fi + + def fn(x, w): + return fi.gemma_rmsnorm(x, w, EPS) + + return f"FlashInfer {_version('flashinfer-python')} gemma_rmsnorm", fn, "none" + + def vllm(): + from vllm.model_executor.layers.layernorm import GemmaRMSNorm + + m = _vllm_module(lambda: GemmaRMSNorm(hidden, eps=EPS)).to(DEV, DT) + + def fn(x, w): + m.weight.data.copy_(w) + return m.forward_cuda(x) + + return f"vLLM {_version('vllm')} GemmaRMSNorm.forward_cuda", fn, "none" + + return [ + ("rl_kernel", ours), + ("reference", reference), + ("transformers", transformers), + ("liger", liger), + ("fla", fla), + ("transformer_engine", te), + ("megatron", megatron), + ("flashinfer", flashinfer), + ("vllm", vllm), + ] + + +def _gated_candidates(hidden: int) -> list[tuple[str, Any]]: + def ours(): + from rl_engine.kernels.ops.cuda.norm.rmsnorm import Qwen3NextRMSNormGatedCudaOp + + o = Qwen3NextRMSNormGatedCudaOp() + return "rl-kernel Qwen3NextRMSNormGatedCudaOp", lambda x, z, w: o(x, w, z, eps=EPS), "full" + + def reference(): + from rl_engine.kernels.ops.pytorch.norm.qwen3_next_rms_norm import Qwen3NextRMSNormGatedOp + + o = Qwen3NextRMSNormGatedOp() + return "rl-kernel PyTorch reference", lambda x, z, w: o(x, w, z, eps=EPS), "full" + + def transformers(): + from transformers.models.qwen3_next.modeling_qwen3_next import Qwen3NextRMSNormGated + + m = Qwen3NextRMSNormGated(hidden, eps=EPS).to(DEV, DT) + + def fn(x, z, w): + return torch.func.functional_call(m, {"weight": w}, (x, z)) + + return f"transformers {_version('transformers')} Qwen3NextRMSNormGated", fn, "full" + + def fla_lg(): + from fla.modules.layernorm_gated import rmsnorm_fn + + def fn(x, z, w): + return rmsnorm_fn(x, w, None, z=z, eps=EPS, group_size=None, norm_before_gate=True) + + return f"FLA {_version('fla-core')} layernorm_gated.rmsnorm_fn", fn, "full" + + def fla_fused(): + from fla.modules.fused_norm_gate import rms_norm_gated + + def fn(x, z, w): + return rms_norm_gated(x, z, w, None, activation="silu", eps=EPS) + + return f"FLA {_version('fla-core')} fused_norm_gate.rms_norm_gated", fn, "full" + + def vllm(): + from vllm.model_executor.layers.layernorm import RMSNormGated + + def build(): + return RMSNormGated( + hidden, eps=EPS, group_size=None, norm_before_gate=True, activation="silu" + ) + + m = _vllm_module(build).to(DEV, DT) + + def fn(x, z, w): + m.weight.data.copy_(w) + return m.forward_cuda(x, z) + + return f"vLLM {_version('vllm')} RMSNormGated.forward_cuda", fn, "none" + + return [ + ("rl_kernel", ours), + ("reference", reference), + ("transformers", transformers), + ("fla_layernorm_gated", fla_lg), + ("fla_fused_norm_gate", fla_fused), + ("vllm", vllm), + ] + + +def candidates(op: str) -> dict[str, dict[str, Any]]: + hidden = SHAPES[op][0] + found = _c1_candidates(hidden) if op == "qwen3_next_rms_norm" else _gated_candidates(hidden) + out: dict[str, dict[str, Any]] = {} + for name, factory in found: + try: + source, fn, backward = factory() + out[name] = {"source": source, "fn": fn, "backward": backward} + except Exception as exc: # noqa: BLE001 - optional library missing or unusable + out[name] = {"unavailable": f"{type(exc).__name__}: {exc}"[:300]} + return out + + +def _inputs(op: str, seed: int, n: int) -> dict[str, torch.Tensor]: + hidden = SHAPES[op][0] + g = torch.Generator(device=DEV).manual_seed(seed) + x = (torch.randn(n, hidden, device=DEV, generator=g) * 2).to(DT) + if op == "qwen3_next_rms_norm": + return {"x": x, "w": (torch.randn(hidden, device=DEV, generator=g) * 0.1).to(DT)} + z = torch.randn(n, hidden, device=DEV, generator=g).to(DT) + return {"x": x, "z": z, "w": (1 + torch.randn(hidden, device=DEV, generator=g) * 0.1).to(DT)} + + +def _reference(op: str, inputs: dict[str, torch.Tensor]): + x = inputs["x"].double() + n = x * torch.rsqrt(x.pow(2).mean(-1, keepdim=True) + EPS) + if op == "qwen3_next_rms_norm": + return n * (1 + inputs["w"].double()) + return n * inputs["w"].double() * F.silu(inputs["z"].double()) + + +# --------------------------------------------------------------------------- # +# Batch invariance +# --------------------------------------------------------------------------- # + + +def _run(fn, inputs, rows, grads, ups, idx=None): + args = {} + for k, v in inputs.items(): + if idx is not None and k in rows: + v = v.index_select(0, idx) + args[k] = v.detach().clone().requires_grad_(True) if k in grads else v + out = fn(**args) + if grads: + out.backward(ups if idx is None else ups.index_select(0, idx)) + return out.detach(), {k: args[k].grad for k in grads} + + +def _sweep_sizes(n: int) -> list[int]: + sizes = set(range(1, min(n, 9) + 1)) + k = 16 + while k <= n: + sizes.update(v for v in (k - 1, k, k + 1) if v <= n) + k *= 2 + return sorted(sizes | {n}) + + +def batch_invariance(op: str, cand: dict[str, Any], quick: bool) -> dict[str, Any]: + _, full_sizes, big, subs, _ = SHAPES[op] + if quick: + full_sizes, big, subs = (17, 64), 512, (1, 7, 64) + fn = cand["fn"] + rows = ["x"] if op == "qwen3_next_rms_norm" else ["x", "z"] + grads = {"full": rows + ["w"], "x-only": rows, "none": []}[cand["backward"]] + row_grads = [k for k in rows if k in grads] + + def ups_for(seed, n): + g = torch.Generator(device=DEV).manual_seed(seed + 100) + return torch.randn(n, SHAPES[op][0], device=DEV, generator=g).to(DT) + + res: dict[str, Any] = {"all_rows": {}, "dweight_repeatable": None} + ok = True + for n in full_sizes: + fwd = grd = 0 + repeat = True + for seed in (3, 4, 5): + inp, ups = _inputs(op, seed, n), ups_for(seed, n) + fo, fg = _run(fn, inp, rows, grads, ups) + for i in range(n): + o, g = _run(fn, inp, rows, grads, ups, torch.tensor([i], device=DEV)) + fwd += not torch.equal(o[0], fo[i]) + grd += not all(torch.equal(g[k][0], fg[k][i]) for k in row_grads) + if "w" in grads: + _, again = _run(fn, inp, rows, grads, ups) + repeat &= torch.equal(again["w"], fg["w"]) + if "w" in grads: + res["dweight_repeatable"] = repeat and res["dweight_repeatable"] is not False + res["all_rows"][str(n)] = {"rows": 3 * n, "fwd_differ": fwd, "rowgrad_differ": grd} + ok &= fwd == 0 and grd == 0 and repeat + + fwd = grd = checked = 0 + for seed in (3, 4): + inp, ups = _inputs(op, seed, big), ups_for(seed, big) + fo, fg = _run(fn, inp, rows, grads, ups) + for sb in subs: + step = sb if sb >= 1024 else max(sb, big // 512) + for start in range(0, big, step): + idx = torch.arange(start, min(start + sb, big), device=DEV) + o, g = _run(fn, inp, rows, grads, ups, idx) + checked += 1 + fwd += not torch.equal(o, fo.index_select(0, idx)) + grd += not all(torch.equal(g[k], fg[k].index_select(0, idx)) for k in row_grads) + del inp, ups, fo, fg + torch.cuda.empty_cache() + res["full_vs_sub_batches"] = { + "full_batch": big, + "sub_batch_sizes": list(subs), + "sub_batches": checked, + "fwd_differ": fwd, + "rowgrad_differ": grd, + } + ok &= fwd == 0 and grd == 0 + + n = full_sizes[-1] + sizes = _sweep_sizes(n) + probes = sorted({0, n - 1, *list(range(n // 8 + 3, n - 1, n // 8))[:6]}) + compared = failed = 0 + for seed in (3, 4, 5): + inp, ups = _inputs(op, seed, n), ups_for(seed, n) + alone = {r: _run(fn, inp, rows, grads, ups, torch.tensor([r], device=DEV)) for r in probes} + gen = torch.Generator().manual_seed(seed) + for m in sizes: + for r in probes: + others = torch.randperm(n, generator=gen) + others = others[others != r][: m - 1] + for pos in sorted({0, (m - 1) // 2, m - 1}): + idx = torch.cat([others[:pos], torch.tensor([r]), others[pos:]]).to(DEV) + o, g = _run(fn, inp, rows, grads, ups, idx) + good = torch.equal(o[pos], alone[r][0][0]) + good &= all(torch.equal(g[k][pos], alone[r][1][k][0]) for k in row_grads) + compared += 1 + failed += not good + res["batch_size_sweep"] = { + "batch_sizes": sizes, + "probe_rows": probes, + "comparisons": compared, + "differ": failed, + } + ok &= failed == 0 + res["batch_invariant"] = bool(ok) + return res + + +# --------------------------------------------------------------------------- # +# Accuracy and latency +# --------------------------------------------------------------------------- # + + +def _time_us(fn, warmup=10, iters=50) -> float: + for _ in range(warmup): + fn() + torch.cuda.synchronize() + samples = [] + for _ in range(iters): + start, end = torch.cuda.Event(enable_timing=True), torch.cuda.Event(enable_timing=True) + start.record() + fn() + end.record() + end.synchronize() + samples.append(start.elapsed_time(end) * 1e3) + return statistics.median(samples) + + +def accuracy_latency(op: str, cand: dict[str, Any], quick: bool) -> dict[str, Any]: + n = 4096 if quick else SHAPES[op][4] + inp = _inputs(op, 11, n) + keys = list(inp) + gk = {"full": keys, "x-only": [k for k in keys if k != "w"], "none": []}[cand["backward"]] + fn = cand["fn"] + leaves64 = {k: v.double().requires_grad_(k in gk) for k, v in inp.items()} + ref = _reference(op, leaves64) + with torch.no_grad(): + y = fn(**inp) + out: dict[str, Any] = { + "rows": n, + "fwd_correctly_rounded": (y == ref.detach().to(DT)).float().mean().item(), + "fwd_max_abs_err": (y.double() - ref.detach()).abs().max().item(), + "fwd_us": _time_us(lambda: fn(**inp)), + } + if gk: + gen = torch.Generator(device=DEV).manual_seed(5) + dy = torch.randn(n, SHAPES[op][0], device=DEV, generator=gen).to(DT) + rg = torch.autograd.grad(ref, [leaves64[k] for k in gk], dy.double()) + lv = {k: v.detach().clone().requires_grad_(k in gk) for k, v in inp.items()} + gs = torch.autograd.grad(fn(**lv), [lv[k] for k in gk], dy) + out["grad_rel_err"] = { + k: ((g.double() - r).abs().max() / r.abs().max()).item() for k, g, r in zip(gk, gs, rg) + } + + def step(): + lv = {k: v.detach().clone().requires_grad_(k in gk) for k, v in inp.items()} + torch.autograd.grad(fn(**lv), [lv[k] for k in gk], dy) + + out["fwd_bwd_us"] = _time_us(step) + return out + + +# --------------------------------------------------------------------------- # +# The repository's C3/C4 gates with an existing implementation swapped in +# --------------------------------------------------------------------------- # + + +def _gate_child(which: str, op: str, impl: str) -> None: + """Run scripts/check_{which}_invariance.py with the CUDA candidate replaced by ``impl``.""" + + import importlib.util + + from rl_engine.kernels.ops.cuda.norm import rmsnorm as R + + path = REPO_ROOT / "scripts" / f"check_{which}_invariance.py" + spec = importlib.util.spec_from_file_location("gate", path) + gate = importlib.util.module_from_spec(spec) + sys.argv = [ + str(path), + "--manifest", + MANIFEST, + "--op", + op, + "--candidate", + "cuda", + "--backend-profile", + "cuda_bf16", + "--hidden", + "2048", + "--head-dim", + "128", + ] + spec.loader.exec_module(gate) + if impl != "rl_kernel": + fn = candidates(op)[impl]["fn"] + if op == "qwen3_next_rms_norm": + + class Swapped(R.Qwen3NextRMSNormCudaOp): + def forward(self, x, weight, *, eps=EPS): + return fn(x.reshape(-1, x.shape[-1]), weight).view_as(x) + + else: + + class Swapped(R.Qwen3NextRMSNormGatedCudaOp): + def __call__(self, x, weight, gate, *, eps=EPS): + return self.forward(x, weight, gate, eps=eps) + + def forward(self, x, weight, gate, *, eps=EPS): + return fn(x, gate, weight) + + original = gate.load_adapter_operator + + def load_adapter_operator(op_name, candidate): + return Swapped() if candidate == "cuda" else original(op_name, candidate) + + gate.load_adapter_operator = load_adapter_operator + gate.main() + + +def contract_gates(op: str, impl: str, megatron_src: str | None) -> dict[str, Any]: + if not (REPO_ROOT / MANIFEST).exists(): + # The Qwen3-Next C3/C4 gate adapters and manifest arrive with the gated-norm PR. + return {"unavailable": f"{MANIFEST} is not on this branch"} + out: dict[str, Any] = {} + for which in ("forward", "gradient"): + cmd = [ + sys.executable, + __file__, + "--op", + op, + "--out", + os.devnull, + "--gate-child", + which, + impl, + ] + if megatron_src: + cmd += ["--megatron-src", megatron_src] + proc = subprocess.run( + cmd, capture_output=True, text=True, env={**os.environ, "RL_KERNEL_REQUIRE_EXT": "1"} + ) + lines = proc.stdout.splitlines() + summary = next((ln for ln in lines if ln.startswith("op=")), "") + out[which] = { + "returncode": proc.returncode, + "passed": "passed=True" in summary and proc.returncode == 0, + "failed_lines": [ln.strip() for ln in lines if "passed=False" in ln][:10], + "singleton_aggregate": [ln.strip() for ln in lines if "singleton_aggregate pair" in ln], + "stderr_tail": proc.stderr.strip().splitlines()[-3:] if proc.returncode else [], + } + return out + + +# --------------------------------------------------------------------------- # +# Report and figure +# --------------------------------------------------------------------------- # + + +def plot(report: dict[str, Any], path: Path) -> None: + try: + import matplotlib + + matplotlib.use("Agg") + import matplotlib.pyplot as plt + except ImportError: + return + entries = [(n, e) for n, e in report["results"].items() if "unavailable" not in e] + names = [e["source"] for _, e in entries] + ys = list(range(len(entries))) + fig, axes = plt.subplots(1, 3, figsize=(22, 0.55 * len(entries) + 3), layout="constrained") + fig.suptitle( + f"{report['op']} vs existing implementations — {report['environment']['gpu']}, " + f"commit {report['rl_kernel_commit'][:7]}" + ) + ax = axes[0] + for key, off, label in (("fwd_us", -0.2, "forward"), ("fwd_bwd_us", 0.2, "fwd + bwd")): + vals = [e.get("accuracy_latency", {}).get(key, float("nan")) for _, e in entries] + ax.barh([y + off for y in ys], vals, 0.4, label=label) + ax.set_xscale("log") + ax.set_yticks(ys, names, fontsize=7) + ax.invert_yaxis() + ax.set_xlabel("µs, median") + ax.set_title("latency at the workload size") + ax.legend(fontsize=7) + ax.grid(True, axis="x", alpha=0.3) + ax = axes[1] + acc = [e.get("accuracy_latency", {}) for _, e in entries] + cr = [a.get("fwd_correctly_rounded", float("nan")) for a in acc] + ax.barh(ys, [max(1 - c, 1e-7) for c in cr]) + for y, c, a in zip(ys, cr, acc): + grads = a.get("grad_rel_err", {}) + worst = f"; worst grad err {max(grads.values()):.1e}" if grads else "" + ax.text(1.5e-7, y, f"{c:.4%} correctly rounded{worst}", va="center", fontsize=7) + ax.set_xscale("log") + ax.set_xlim(1e-7, 1) + ax.set_yticks(ys, [""] * len(entries)) + ax.invert_yaxis() + ax.set_title("forward: fraction NOT equal to the correctly rounded FP64 result") + ax = axes[2] + for y, (_, e) in zip(ys, entries): + bi = e.get("batch_invariance") + gates = e.get("contract_gates") + text = "batch-invariant: " + ( + "n/a" if bi is None else ("yes" if bi["batch_invariant"] else "NO") + ) + if gates and "unavailable" not in gates: + text += " | C3/C4 gates: " + ( + "pass" if all(g["passed"] for g in gates.values()) else "FAIL" + ) + good = bi is not None and bi["batch_invariant"] + ax.text(0.02, y, text, va="center", fontsize=8, color="#3aa676" if good else "#d14b4b") + ax.set_ylim(len(entries) - 0.5, -0.5) + ax.axis("off") + ax.set_title("every-row batch invariance and this repository's gates") + fig.savefig(path.with_suffix(".png"), dpi=120) + + +def _git(*args: str) -> str: + return subprocess.run( + ["git", *args], cwd=REPO_ROOT, capture_output=True, text=True + ).stdout.strip() + + +def main() -> None: + parser = argparse.ArgumentParser( + description=__doc__, formatter_class=argparse.RawDescriptionHelpFormatter + ) + parser.add_argument("--op", required=True, choices=sorted(SHAPES)) + parser.add_argument("--out", type=Path, required=True) + parser.add_argument("--checks", default="bi,perf,gates") + parser.add_argument("--megatron-src", default=None, help="Megatron-LM source tree (optional)") + parser.add_argument("--quick", action="store_true", help="small sizes, for a smoke test only") + parser.add_argument("--gate-child", nargs=2, default=None, help=argparse.SUPPRESS) + args = parser.parse_args() + if args.megatron_src: + sys.path.insert(0, args.megatron_src) + if not torch.cuda.is_available(): + raise SystemExit("needs a CUDA device") + if args.gate_child: + _gate_child(args.gate_child[0], args.op, args.gate_child[1]) + return + if args.op == "rms_norm_gated": + from rl_engine.kernels.ops.cuda.norm import rmsnorm as R + + if not hasattr(R, "Qwen3NextRMSNormGatedCudaOp"): + raise SystemExit("rms_norm_gated: the gated CUDA op is not on this branch") + torch.backends.cuda.matmul.allow_tf32 = False + checks = set(args.checks.split(",")) + results: dict[str, Any] = {} + for name, cand in candidates(args.op).items(): + if "unavailable" in cand: + results[name] = cand + print(f"{name}: unavailable ({cand['unavailable'][:80]})", flush=True) + continue + entry: dict[str, Any] = {"source": cand["source"], "backward": cand["backward"]} + if "bi" in checks: + entry["batch_invariance"] = batch_invariance(args.op, cand, args.quick) + if "perf" in checks: + entry["accuracy_latency"] = accuracy_latency(args.op, cand, args.quick) + if "gates" in checks and cand["backward"] == "full" and name != "reference": + entry["contract_gates"] = contract_gates(args.op, name, args.megatron_src) + results[name] = entry + summary = {k: v for k, v in entry.items() if k != "source"} + print(f"{name}: {json.dumps(summary)[:300]}", flush=True) + torch.cuda.empty_cache() + + megatron_commit = None + if args.megatron_src: + megatron_commit = ( + subprocess.run( + ["git", "rev-parse", "--short", "HEAD"], + cwd=args.megatron_src, + capture_output=True, + text=True, + ).stdout.strip() + or None + ) + report = { + "kind": "qwen3_next_norm_reuse_check", + "rfc": "RL-Align/RL-Kernel#428", + "op": args.op, + "rl_kernel_commit": _git("rev-parse", "HEAD"), + "tracked_tree_dirty": bool(_git("status", "--porcelain", "--untracked-files=no")), + "environment": { + "gpu": torch.cuda.get_device_name(), + "capability": list(torch.cuda.get_device_capability()), + "cuda": torch.version.cuda, + "libraries": {lib: _version(lib) for lib in LIBS}, + "megatron_source_commit": megatron_commit, + }, + "quick": args.quick, + "checks": sorted(checks), + "results": results, + } + args.out.parent.mkdir(parents=True, exist_ok=True) + args.out.write_text(json.dumps(report, indent=2) + "\n") + plot(report, args.out) + commit, dirty = report["rl_kernel_commit"][:7], report["tracked_tree_dirty"] + print(f"wrote {args.out} (commit {commit}, dirty={dirty})") + + +if __name__ == "__main__": + main() From 791e40d7d758177025cca649a73005ea0cffdbb6 Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Thu, 8 Oct 2026 23:18:00 +0000 Subject: [PATCH 13/15] docs(norm): qwen3_next_rms_norm vs existing implementations, every-row batch invariance (B200, a66493c) Batch invariance of every row (plus full batch vs covering sub-batches and a size sweep), accuracy against FP64, latency, and the repository's C3/C4 gates with each implementation swapped in, from scripts/qwen3_next_norm_reuse_check.py. Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- docs/operators/qwen3-next-rms-norm.md | 31 + .../qwen3_next_rms_norm.json | 912 ++++++++++++++++++ .../qwen3_next_rms_norm.png | Bin 0 -> 165808 bytes 3 files changed, 943 insertions(+) create mode 100644 docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json create mode 100644 docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.png diff --git a/docs/operators/qwen3-next-rms-norm.md b/docs/operators/qwen3-next-rms-norm.md index ede972b3a..814d26de2 100644 --- a/docs/operators/qwen3-next-rms-norm.md +++ b/docs/operators/qwen3-next-rms-norm.md @@ -126,6 +126,37 @@ BF16. gradient-invariance contract's singleton-aggregate check). That serial fold over rows is the cost; a faster tree fold would not pass that check. +## Existing implementations: batch invariance of every row, accuracy, gates + +![qwen3_next_rms_norm vs existing implementations](../usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.png) + +| Implementation | Batch-invariant | Forward correctly rounded | Worst grad err | Forward / fwd+bwd | C3/C4 gates | +|---|---|---|---|---|---| +| rl-kernel Qwen3NextRMSNormCudaOp | yes | 99.9993% | 2.4e-03 | 426 / 31485 µs | not on this branch | +| rl-kernel PyTorch reference | **no** (49 rows, 94 sub-batches) | 99.9993% | 2.4e-03 | 2146 / 5024 µs | — | +| transformers 5.17.0 Qwen3NextRMSNorm | **no** (90 rows, 142 sub-batches) | 99.9992% | 2.4e-03 | 1449 / 4468 µs | not on this branch | +| Liger 0.8.4 RMSNorm, offset 1, gemma | yes | 99.9993% | 2.4e-03 | 133 / 974 µs | not on this branch | +| FLA 0.5.2 rms_norm, weight passed as 1 + w | yes | 73.0161% | 5.5e-03 | 147 / 1051 µs | not on this branch | +| TE 2.20.2 RMSNorm(zero_centered_gamma) | **no** (175 rows, 245 sub-batches) | 99.9992% | 2.4e-03 | 156 / 779 µs | — | +| Megatron BatchInvariantRMSNormFn(zero_centered_gamma=True) | **no** (47 rows, 62 sub-batches, 92 sweep cases) | 0.0000% | 1.2e-02 | 1439 / 5507 µs | not on this branch | +| FlashInfer 0.6.18.post1 gemma_rmsnorm | yes | 99.9992% | — | 91 / — µs | — | +| vLLM 0.30.0 GemmaRMSNorm.forward_cuda | **no** (16 rows, 26 sub-batches) | 99.9992% | — | 1454 / — µs | — | + +Batch invariance is bitwise and covers three checks: every row computed alone vs inside full +batches of three sizes; the full workload-size batch vs sub-batches that together cover every +row; and a dense batch-size sweep. A "no" counts the rows, sub-batches or sweep cases that +differed. Accuracy is against FP64 at the workload size; latency is the median on an otherwise +idle B200. The C3/C4 column runs this repository's own gate scripts unchanged, with the CUDA +candidate replaced by a subclass of this op whose forward and backward call the other library. +The subclass keeps this op's FP32 `dweight` row contributions, so singleton-aggregate compares +like with like. The gate scripts for this op arrive with #468 (`qwen3_next_norm_manifest.json`); its gate results are in #468's copy of this page. [`qwen3_next_rms_norm.json`](../usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json) +was written from a clean tree at `a66493c` by + +```bash +python scripts/qwen3_next_norm_reuse_check.py --op qwen3_next_rms_norm \ + --out docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json [--megatron-src ] +``` + ## Tests ```bash diff --git a/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json b/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json new file mode 100644 index 000000000..8cae3400d --- /dev/null +++ b/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json @@ -0,0 +1,912 @@ +{ + "kind": "qwen3_next_norm_reuse_check", + "rfc": "RL-Align/RL-Kernel#428", + "op": "qwen3_next_rms_norm", + "rl_kernel_commit": "a66493c6d0b49d78aec6df3519b70fb45eace24f", + "tracked_tree_dirty": false, + "environment": { + "gpu": "NVIDIA B200", + "capability": [ + 10, + 0 + ], + "cuda": "13.0", + "libraries": { + "torch": "2.13.0", + "triton": "3.7.1", + "transformers": "5.17.0", + "vllm": "0.30.0", + "flashinfer-python": "0.6.18.post1", + "liger-kernel": "0.8.4", + "fla-core": "0.5.2", + "transformer_engine": "2.20.2", + "megatron-core": null + }, + "megatron_source_commit": "52fbcbc" + }, + "quick": false, + "checks": [ + "bi", + "gates", + "perf" + ], + "results": { + "rl_kernel": { + "source": "rl-kernel Qwen3NextRMSNormCudaOp", + "backward": "full", + "batch_invariance": { + "all_rows": { + "64": { + "rows": 192, + "fwd_differ": 0, + "rowgrad_differ": 0 + }, + "257": { + "rows": 771, + "fwd_differ": 0, + "rowgrad_differ": 0 + }, + "2048": { + "rows": 6144, + "fwd_differ": 0, + "rowgrad_differ": 0 + } + }, + "dweight_repeatable": true, + "full_vs_sub_batches": { + "full_batch": 65536, + "sub_batch_sizes": [ + 1, + 7, + 2048, + 4097, + 32768 + ], + "sub_batches": 2148, + "fwd_differ": 0, + "rowgrad_differ": 0 + }, + "batch_size_sweep": { + "batch_sizes": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 15, + 16, + 17, + 31, + 32, + 33, + 63, + 64, + 65, + 127, + 128, + 129, + 255, + 256, + 257, + 511, + 512, + 513, + 1023, + 1024, + 1025, + 2047, + 2048 + ], + "probe_rows": [ + 0, + 259, + 515, + 771, + 1027, + 1283, + 1539, + 2047 + ], + "comparisons": 2232, + "differ": 0 + }, + "batch_invariant": true + }, + "accuracy_latency": { + "rows": 65536, + "fwd_correctly_rounded": 0.9999926686286926, + "fwd_max_abs_err": 0.015624080561254416, + "fwd_us": 426.4480024576187, + "grad_rel_err": { + "x": 0.0023939748586017722, + "w": 0.0019861680402388695 + }, + "fwd_bwd_us": 31485.487937927246 + }, + "contract_gates": { + "unavailable": "rl_engine/testing/qwen3_next_norm_manifest.json is not on this branch" + } + }, + "reference": { + "source": "rl-kernel PyTorch reference", + "backward": "full", + "batch_invariance": { + "all_rows": { + "64": { + "rows": 192, + "fwd_differ": 0, + "rowgrad_differ": 2 + }, + "257": { + "rows": 771, + "fwd_differ": 0, + "rowgrad_differ": 7 + }, + "2048": { + "rows": 6144, + "fwd_differ": 0, + "rowgrad_differ": 40 + } + }, + "dweight_repeatable": true, + "full_vs_sub_batches": { + "full_batch": 65536, + "sub_batch_sizes": [ + 1, + 7, + 2048, + 4097, + 32768 + ], + "sub_batches": 2148, + "fwd_differ": 0, + "rowgrad_differ": 94 + }, + "batch_size_sweep": { + "batch_sizes": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 15, + 16, + 17, + 31, + 32, + 33, + 63, + 64, + 65, + 127, + 128, + 129, + 255, + 256, + 257, + 511, + 512, + 513, + 1023, + 1024, + 1025, + 2047, + 2048 + ], + "probe_rows": [ + 0, + 259, + 515, + 771, + 1027, + 1283, + 1539, + 2047 + ], + "comparisons": 2232, + "differ": 0 + }, + "batch_invariant": false + }, + "accuracy_latency": { + "rows": 65536, + "fwd_correctly_rounded": 0.9999927282333374, + "fwd_max_abs_err": 0.015624080561254416, + "fwd_us": 2145.951986312866, + "grad_rel_err": { + "x": 0.0023939748586017722, + "w": 0.0019861680402388695 + }, + "fwd_bwd_us": 5024.384021759033 + } + }, + "transformers": { + "source": "transformers 5.17.0 Qwen3NextRMSNorm", + "backward": "full", + "batch_invariance": { + "all_rows": { + "64": { + "rows": 192, + "fwd_differ": 0, + "rowgrad_differ": 3 + }, + "257": { + "rows": 771, + "fwd_differ": 0, + "rowgrad_differ": 10 + }, + "2048": { + "rows": 6144, + "fwd_differ": 16, + "rowgrad_differ": 61 + } + }, + "dweight_repeatable": true, + "full_vs_sub_batches": { + "full_batch": 65536, + "sub_batch_sizes": [ + 1, + 7, + 2048, + 4097, + 32768 + ], + "sub_batches": 2148, + "fwd_differ": 26, + "rowgrad_differ": 116 + }, + "batch_size_sweep": { + "batch_sizes": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 15, + 16, + 17, + 31, + 32, + 33, + 63, + 64, + 65, + 127, + 128, + 129, + 255, + 256, + 257, + 511, + 512, + 513, + 1023, + 1024, + 1025, + 2047, + 2048 + ], + "probe_rows": [ + 0, + 259, + 515, + 771, + 1027, + 1283, + 1539, + 2047 + ], + "comparisons": 2232, + "differ": 0 + }, + "batch_invariant": false + }, + "accuracy_latency": { + "rows": 65536, + "fwd_correctly_rounded": 0.9999924898147583, + "fwd_max_abs_err": 0.015624080561254416, + "fwd_us": 1449.1679668426514, + "grad_rel_err": { + "x": 0.0023939748586017722, + "w": 0.0019861680402388695 + }, + "fwd_bwd_us": 4467.727899551392 + }, + "contract_gates": { + "unavailable": "rl_engine/testing/qwen3_next_norm_manifest.json is not on this branch" + } + }, + "liger": { + "source": "Liger 0.8.4 RMSNorm, offset 1, gemma", + "backward": "full", + "batch_invariance": { + "all_rows": { + "64": { + "rows": 192, + "fwd_differ": 0, + "rowgrad_differ": 0 + }, + "257": { + "rows": 771, + "fwd_differ": 0, + "rowgrad_differ": 0 + }, + "2048": { + "rows": 6144, + "fwd_differ": 0, + "rowgrad_differ": 0 + } + }, + "dweight_repeatable": true, + "full_vs_sub_batches": { + "full_batch": 65536, + "sub_batch_sizes": [ + 1, + 7, + 2048, + 4097, + 32768 + ], + "sub_batches": 2148, + "fwd_differ": 0, + "rowgrad_differ": 0 + }, + "batch_size_sweep": { + "batch_sizes": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 15, + 16, + 17, + 31, + 32, + 33, + 63, + 64, + 65, + 127, + 128, + 129, + 255, + 256, + 257, + 511, + 512, + 513, + 1023, + 1024, + 1025, + 2047, + 2048 + ], + "probe_rows": [ + 0, + 259, + 515, + 771, + 1027, + 1283, + 1539, + 2047 + ], + "comparisons": 2232, + "differ": 0 + }, + "batch_invariant": true + }, + "accuracy_latency": { + "rows": 65536, + "fwd_correctly_rounded": 0.9999925494194031, + "fwd_max_abs_err": 0.015624080561254416, + "fwd_us": 133.31200182437897, + "grad_rel_err": { + "x": 0.0023939748586017722, + "w": 0.0019861680402388695 + }, + "fwd_bwd_us": 973.6000001430511 + }, + "contract_gates": { + "unavailable": "rl_engine/testing/qwen3_next_norm_manifest.json is not on this branch" + } + }, + "fla": { + "source": "FLA 0.5.2 rms_norm, weight passed as 1 + w", + "backward": "full", + "batch_invariance": { + "all_rows": { + "64": { + "rows": 192, + "fwd_differ": 0, + "rowgrad_differ": 0 + }, + "257": { + "rows": 771, + "fwd_differ": 0, + "rowgrad_differ": 0 + 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zBkG6W<7_O~?%mZrqnOqj{-lGCh#89mDAxhSM>4!0{HI_uLHlkY4C7k`B&o%1m^S*IH?(GSO4Ut{Qm&5 z0&oCGIY06u+Nj_bLwH&M4JZW}l(WvRuE7^N5IPtzWCsjEEOXLN2K@?2TDRw1r{^;a zNyt;fNG;gQG8MdId?%&w}^ll#; z{&6W{teN@Lx2Do-t^S4mqy>s)H8)jL&;x+ckBc%b(C=we0pE#3&koN%U^?`W^v^ zm=-U`2O>>pI$Kd$zc-j0UP}=f*dI^H`+xJ3PZjnpE8JejMxP_V6v0UyF9kestEOhn zH=M%gX@G!FlOgEEsW1EX-yiqI*aDA(<>TfwR3IpUuD8hle$(i`7g&D37%M_RY41W< zH7Wl0552B#_)G5LkMF+d_<)1yE(g_XUp%6A*?c+aPCxlyK6^XoS)ApLn)L8S*U Date: Thu, 8 Oct 2026 23:31:45 +0000 Subject: [PATCH 14/15] fix(scripts): keep local paths and warnings out of norm reuse-check gate output Signed-off-by: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> --- scripts/qwen3_next_norm_reuse_check.py | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/scripts/qwen3_next_norm_reuse_check.py b/scripts/qwen3_next_norm_reuse_check.py index 3b5eded28..b80522eae 100644 --- a/scripts/qwen3_next_norm_reuse_check.py +++ b/scripts/qwen3_next_norm_reuse_check.py @@ -492,6 +492,22 @@ def load_adapter_operator(op_name, candidate): gate.main() +def _clean(lines: list[str], megatron_src: str | None) -> list[str]: + """Drop warnings and replace machine-specific paths, so reports carry no local paths.""" + + subs = [(str(REPO_ROOT), ""), (sys.prefix, ""), (str(Path.home()), "")] + if megatron_src: + subs.insert(0, (str(Path(megatron_src).resolve()), "")) + out = [] + for line in lines: + if "Warning" in line or "warnings.warn" in line: + continue + for path, name in subs: + line = line.replace(path, name) + out.append(line) + return out + + def contract_gates(op: str, impl: str, megatron_src: str | None) -> dict[str, Any]: if not (REPO_ROOT / MANIFEST).exists(): # The Qwen3-Next C3/C4 gate adapters and manifest arrive with the gated-norm PR. @@ -514,14 +530,18 @@ def contract_gates(op: str, impl: str, megatron_src: str | None) -> dict[str, An proc = subprocess.run( cmd, capture_output=True, text=True, env={**os.environ, "RL_KERNEL_REQUIRE_EXT": "1"} ) - lines = proc.stdout.splitlines() + lines = _clean(proc.stdout.splitlines(), megatron_src) summary = next((ln for ln in lines if ln.startswith("op=")), "") out[which] = { "returncode": proc.returncode, "passed": "passed=True" in summary and proc.returncode == 0, "failed_lines": [ln.strip() for ln in lines if "passed=False" in ln][:10], "singleton_aggregate": [ln.strip() for ln in lines if "singleton_aggregate pair" in ln], - "stderr_tail": proc.stderr.strip().splitlines()[-3:] if proc.returncode else [], + "stderr_tail": ( + _clean(proc.stderr.strip().splitlines(), megatron_src)[-3:] + if proc.returncode + else [] + ), } return out From e39f307d8b5f046716eb480abbe2392a987827fa Mon Sep 17 00:00:00 2001 From: Wenbo Ji <36562829+fusheng-ji@users.noreply.github.com> Date: Fri, 9 Oct 2026 10:19:31 +0000 Subject: [PATCH 15/15] fix: exclude invalid Megatron zero-centered norm evidence --- docs/operators/qwen3-next-rms-norm.md | 15 ++- .../qwen3_next_rms_norm.json | 104 +----------------- .../qwen3_next_rms_norm.png | Bin 165808 -> 127897 bytes scripts/qwen3_next_norm_reuse_check.py | 11 ++ tests/test_qwen3_next_norm_reuse_check.py | 49 +++++++++ 5 files changed, 76 insertions(+), 103 deletions(-) create mode 100644 tests/test_qwen3_next_norm_reuse_check.py diff --git a/docs/operators/qwen3-next-rms-norm.md b/docs/operators/qwen3-next-rms-norm.md index 814d26de2..ecf0925c3 100644 --- a/docs/operators/qwen3-next-rms-norm.md +++ b/docs/operators/qwen3-next-rms-norm.md @@ -43,8 +43,8 @@ y = rmsnorm_cuda(x, weight, eps=1e-6, weight_offset=1.0) | Argument | Shape | Dtype | Requirements | | --- | --- | --- | --- | -| `x` | `[..., H]` | fp32 / bf16 / fp16 | CUDA path requires contiguous | -| `weight` | `[H]` | matches `x` | zero-centred (upstream inits to zeros) | +| `x` | `[..., H]` | fp32 / bf16 / fp16 | CUDA wrapper copies non-contiguous inputs; low-level `rmsnorm_cuda` requires contiguous inputs | +| `weight` | `[H]` | matches `x` | zero-centred (upstream inits to zeros); CUDA wrapper copies non-contiguous weights; low-level `rmsnorm_cuda` requires contiguous weights | | `eps` | scalar | float | inside the sqrt; `1e-6` for Qwen3-Next | ## Dispatch Behavior @@ -138,7 +138,6 @@ BF16. | Liger 0.8.4 RMSNorm, offset 1, gemma | yes | 99.9993% | 2.4e-03 | 133 / 974 µs | not on this branch | | FLA 0.5.2 rms_norm, weight passed as 1 + w | yes | 73.0161% | 5.5e-03 | 147 / 1051 µs | not on this branch | | TE 2.20.2 RMSNorm(zero_centered_gamma) | **no** (175 rows, 245 sub-batches) | 99.9992% | 2.4e-03 | 156 / 779 µs | — | -| Megatron BatchInvariantRMSNormFn(zero_centered_gamma=True) | **no** (47 rows, 62 sub-batches, 92 sweep cases) | 0.0000% | 1.2e-02 | 1439 / 5507 µs | not on this branch | | FlashInfer 0.6.18.post1 gemma_rmsnorm | yes | 99.9992% | — | 91 / — µs | — | | vLLM 0.30.0 GemmaRMSNorm.forward_cuda | **no** (16 rows, 26 sub-batches) | 99.9992% | — | 1454 / — µs | — | @@ -150,7 +149,15 @@ idle B200. The C3/C4 column runs this repository's own gate scripts unchanged, w candidate replaced by a subclass of this op whose forward and backward call the other library. The subclass keeps this op's FP32 `dweight` row contributions, so singleton-aggregate compares like with like. The gate scripts for this op arrive with #468 (`qwen3_next_norm_manifest.json`); its gate results are in #468's copy of this page. [`qwen3_next_rms_norm.json`](../usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json) -was written from a clean tree at `a66493c` by +was originally written from a clean tree at `a66493c` by the command below. The +Megatron `52fbcbc` result has been excluded from the report, table and figure: +that revision computes `weight_eff` but uses the original `weight` in its forward +output, so it does not implement the zero-centred operation despite accepting the +flag. The remaining measurements are unchanged; the figure was regenerated from +the corrected report without rerunning benchmarks. The reuse checker now rejects +Megatron implementations that fail a zero-weight probe before benchmarking them. + +Original command: ```bash python scripts/qwen3_next_norm_reuse_check.py --op qwen3_next_rms_norm \ diff --git a/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json b/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json index 8cae3400d..7886c8035 100644 --- a/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json +++ b/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json @@ -625,104 +625,7 @@ } }, "megatron": { - "source": "Megatron BatchInvariantRMSNormFn(zero_centered_gamma=True)", - "backward": "full", - "batch_invariance": { - "all_rows": { - "64": { - "rows": 192, - "fwd_differ": 0, - "rowgrad_differ": 0 - }, - "257": { - "rows": 771, - "fwd_differ": 0, - "rowgrad_differ": 3 - }, - "2048": { - "rows": 6144, - "fwd_differ": 0, - "rowgrad_differ": 44 - } - }, - "dweight_repeatable": true, - "full_vs_sub_batches": { - "full_batch": 65536, - "sub_batch_sizes": [ - 1, - 7, - 2048, - 4097, - 32768 - ], - "sub_batches": 2148, - "fwd_differ": 0, - "rowgrad_differ": 62 - }, - "batch_size_sweep": { - "batch_sizes": [ - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 15, - 16, - 17, - 31, - 32, - 33, - 63, - 64, - 65, - 127, - 128, - 129, - 255, - 256, - 257, - 511, - 512, - 513, - 1023, - 1024, - 1025, - 2047, - 2048 - ], - "probe_rows": [ - 0, - 259, - 515, - 771, - 1027, - 1283, - 1539, - 2047 - ], - "comparisons": 2232, - "differ": 92 - }, - "batch_invariant": false - }, - "accuracy_latency": { - "rows": 65536, - "fwd_correctly_rounded": 7.450580596923828e-08, - "fwd_max_abs_err": 5.5793535592200865, - "fwd_us": 1438.655972480774, - "grad_rel_err": { - "x": 0.012024440704548441, - "w": 0.0019861680402388695 - }, - "fwd_bwd_us": 5506.911993026733 - }, - "contract_gates": { - "unavailable": "rl_engine/testing/qwen3_next_norm_manifest.json is not on this branch" - } + "unavailable": "Excluded: Megatron 52fbcbc accepts zero_centered_gamma=True but uses the original weight instead of weight_eff in forward." }, "flashinfer": { "source": "FlashInfer 0.6.18.post1 gemma_rmsnorm", @@ -908,5 +811,8 @@ "fwd_us": 1454.3840289115906 } } - } + }, + "evidence_corrections": [ + "Removed the invalid Megatron 52fbcbc zero-centered comparison and regenerated the figure. All other measurements and original run provenance are unchanged; benchmarks were not rerun." + ] } diff --git a/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.png b/docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.png index 29fa0e94ceefdc93fa2bedcefd4874beb5d1a2a7..46e954979e47f33c2ed65fa4e836a14960dd3636 100644 GIT binary patch literal 127897 zcmbrmXH=70*EWg;-GYc)K|};}t4IeyDWTgCrB^8d5d$K<1SB*C#jRAOgQ52lssRE7 z5v3#)siB3S)Fco(q35jlyw5rB8Q;&3F&rc@z|Fenn)7Ol_xie;9BdcZSXfv%v>x0w zWMN^`XJI+=@~>my6?CEe68Hr1zW3PM$j#o{*VYrpqGRjr?(F96?D+JO56sic(alv> z^2QCx8{(IqdwaWkL8PQy{@-^;+%49AaV7 zx~pOQ^78_b^)vV2Zrh3jndTaE=Cr|St|P|U3$*TZBJsd^e}woi@vQ`#&_Bo69=vqa6|>+!V8bUGCt-ze+5+S!>b+oOD4>RkAbli(-*uaAtAB4*?4|LX2Dvd0|4GXsqY=9rr+w*r!(9c>UC;^G4h7QWL{fZEyKb;pZUKV^n2n4vq0?dZDTZ zUDk9ky1Kf$utBh?NszFd<(q5ebE}po1@zMz)^w?avh>FN%`u<-4Z>Kr(vow{1i}eN zZekql`fLoEjp-^aKC2=6SbkF$^qc;hI#T6;g{_Dh7d-j$Vz9C`l5Z@*($&#_@k=6n z{^#Wx#G8EHoBo^5WByBx66eB4aucmz9Ow7eZyggEk=dDX9xl(^SR5nhLdaL?OXV

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