configs,dev: reduce UARTLite console PIO latency

Change-Id: I066e3c04be47b2f20da2e3601c6476bfb4292d82

Author: jensen-yan

configs/common/FSConfig.py

@@ -682,6 +682,10 @@ def makeXiangshanPlatformSystem(mem_mode, mdesc=None, np=1, ruby=False):
         self.bridge.cpu_side_port = self.membus.mem_side_ports
 
     self.uartlite  = UartLite()
+    # Keep debug console output from dominating short bare-metal runs.
+    # We do not study UART timing here, so prefer a near-functional UART for
+    # printf-heavy debug/program output.
+    self.uartlite.pio_latency = '1ns'
     self.uartlite.pio = self.iobus.mem_side_ports
 
     self.lint = Clint()

src/dev/serial/Uart.py

@@ -88,4 +88,3 @@ class UartLite(BasicPioDevice):
     cxx_class = 'gem5::UartLite'
     pio_addr = 0x40600000
     pio_size = Param.Addr(0xd, "Size of address range")
-    tx_pio_latency = Param.Latency('1ns', "Latency for UART TX FIFO writes")

src/dev/serial/uartlite.cc

@@ -27,25 +27,21 @@ Tick UartLite::write(PacketPtr pkt)
     auto offset = pkt->getAddr() - pioAddr;
     assert(pkt->getSize() == 1);
 
-    Tick delay = pioDelay;
-
     switch (offset) {
         case UARTLITE_TX_FIFO:
             putc(pkt->getRaw<uint8_t>(), stdout);
-            delay = txPioDelay;
             break;
         default:
             warn("Write to other uartlite addr %i is not implemented\n",
                  offset);
     }
 
     pkt->makeAtomicResponse();
-    return delay;
+    return pioDelay;
 }
 
 UartLite::UartLite(const UartLiteParams *params)
-    : BasicPioDevice(*params, params->pio_size),
-      txPioDelay(params->tx_pio_latency)
+    : BasicPioDevice(*params, params->pio_size)
 {
 }
 

src/dev/serial/uartlite.hh

@@ -14,9 +14,6 @@ namespace gem5
 {
 class UartLite : public BasicPioDevice
 {
-  private:
-    Tick txPioDelay;
-
   public:
     Tick read(PacketPtr pkt) override;
     Tick write(PacketPtr pkt) override;