The Interface section of the README documents the power_squared port as:
| power_squared | OUT | 2*DATA_W-2 | Output power (magnitude squared) |
However the actual entity declaration in src/power_detector.vhd is:
vhdlpower_squared : OUT std_logic_vector(2*DATA_W - 2 DOWNTO 0)
The range (2DATA_W - 2 DOWNTO 0) has a width of 2DATA_W - 1 bits, not 2*DATA_W - 2. The README's value matches the MSB index, not the bit count.
Concrete examples:
DATA_W = 12 (default): README says width = 22, actual width = 23 bits
DATA_W = 16: README says width = 30, actual width = 31 bits
This came up when wiring power_squared into a connecting signal. Vivado elaboration caught the mismatch with [VRFC 10-8944] expression has 30 elements; formal 'power_squared' expects 31. Trivial to fix downstream but worth correcting upstream so others don't repeat the diagnostic.
Maybe change the Width column entry to 2DATA_W-1, or restructure the column to show the range (2DATA_W-2 downto 0) to make the off-by one super obvious? Definitely a "people like me" type of deal.
The Interface section of the README documents the power_squared port as:
| power_squared | OUT | 2*DATA_W-2 | Output power (magnitude squared) |
However the actual entity declaration in src/power_detector.vhd is:
vhdlpower_squared : OUT std_logic_vector(2*DATA_W - 2 DOWNTO 0)The range (2DATA_W - 2 DOWNTO 0) has a width of 2DATA_W - 1 bits, not 2*DATA_W - 2. The README's value matches the MSB index, not the bit count.
Concrete examples:
This came up when wiring power_squared into a connecting signal. Vivado elaboration caught the mismatch with
[VRFC 10-8944] expression has 30 elements; formal 'power_squared' expects 31. Trivial to fix downstream but worth correcting upstream so others don't repeat the diagnostic.Maybe change the Width column entry to 2DATA_W-1, or restructure the column to show the range (2DATA_W-2 downto 0) to make the off-by one super obvious? Definitely a "people like me" type of deal.