fpga_diff: expose extra IO with difftest createTopIOs

Author: klin02

Makefile

@@ -1,12 +1,10 @@
 TOP = TopMain
 SIM_TOP = SimTop
-FPGA_DIFF_TOP = FpgaDiffTop
 FPGATOP = Top
 # REAL_TOP selection:
-# - if BOARD is exactly "fpgadiff" -> use FPGA_DIFF_TOP
-# - else if BOARD starts with "sim" -> use SIM_TOP
+# - if BOARD is exactly "fpgadiff" or "sim" -> use FPGA_DIFF_TOP
 # - otherwise use FPGATOP
-REAL_TOP = $(if $(filter fpgadiff,$(BOARD)),$(FPGA_DIFF_TOP),$(if $(filter sim,$(BOARD)),$(SIM_TOP),$(FPGATOP)))
+REAL_TOP = $(if $(filter fpgadiff sim,$(BOARD)),$(SIM_TOP),$(FPGATOP))
 
 BUILD_DIR = $(abspath ./build)
 

src/main/scala/sim/NutShellSim.scala

@@ -45,7 +45,8 @@ class NutShellSim extends Module with HasDiffTestInterfaces {
 
   val uart = IO(new UARTIO)
   uart <> mmio.io.uart
-  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
+  override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
     difftest.uart <> uart
+    Seq.empty
   }
 }

src/test/scala/TopMain.scala

@@ -36,16 +36,11 @@ class Top extends Module {
   dontTouch(vga.io)
 }
 
-class FpgaDiffTop extends Module with HasDiffTestInterfaces {
-  lazy val config = NutCoreConfig(FPGADifftest = true)
-  val soc = Module(new NutShell()(config))
-  val io = IO(soc.io.cloneType)
-  soc.io <> io
-
+class FpgaDiffTop extends NutShell()(NutCoreConfig(FPGADifftest = true)) with HasDiffTestInterfaces {
+  override def desiredName: String = "NutShell"
   override def cpuName: Option[String] = Some("NutShell")
-  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
-    val io = IO(chiselTypeOf(this.io))
-    io <> this.io
+  override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
+    Seq(io)
   }
 }