Understanding the workarounds in chipset_pcie.c

[peat-psuwit]

So, I'm having some trouble with runtime D3 suspension with nouveau driver, and nouveau's maintainer points out that there exists a sort of workaround registry for PCI-E chipsets in src/nvidia/src/kernel/platform/chipset/chipset_pcie.c. So I just wonder, how do these workarounds come to be? Do they come from NVIDIA's own testing, or from partner's bug reports?

Also, a quick code search doesn't reveal me the place these workaround flags are used. So, could you please point me out on this?

[mtijanic]

Also, a quick code search doesn't reveal me the place these workaround flags are used. So, could you please point me out on this?

A lot of these PDB_PROP_CL_* workaround bits are collected at module init time before the firmware is loaded, and then they're sent over to GSP, and GSP then also changes behavior based on these.

Other reason why many might show up as unused is that they often apply to power management related paths that are missing from the current release. I don't know if any of the chipset workarounds are relevant to D3.