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Performance-aware topology planner + placement simulator (merged planner, cost model, scenario corpus) #1455

Description

@i386

Status: design proposal · Date: 2026-08-26 · Owner: TBD

Goal

Replace capacity-only split placement with one performance-aware planner that consumes the complete input set — memory, sustained node performance, directed link latency/bandwidth, model-family legality, workload intent, and operational stability — plus a simulator to evaluate placement decisions under synthetic conditions without a cluster.

Origin: Buzz skippy-topology channel discussion, 2026-08-26 (James). Full design: docs/design/PERFORMANCE_AWARE_TOPOLOGY_PLANNER.md (PR #1454).

Problem

Today's planner (crates/skippy-coordinator/src/topology.rs) places contiguous layer ranges by memory arithmetic only; its sole network term is stage_count × max RTT. The fleet already gossips gpu_mem_bandwidth_gbps and gpu_compute_tflops_fp16/fp32, and skippy-topology already models directed edges (StageEdgeSignal) — both are dropped before the planner sees them. Measured cost: 68 tok/s solo → 21 at 2-way → 12-13 at 3-way on documented Wi-Fi hardware (docs/BENCHMARKS.md).

Non-goals

  • No stage-runtime / wire-protocol / llama.cpp changes (placement only)
  • Contiguous layer pipelines only — no tensor/pipeline-parallel hybrid graphs
  • No live adaptive replanning until the cost model is calibrated (phase 5)

Workstreams

  1. Phase 0 — plumbing: thread gossiped perf metrics through SplitTopologyPlanInput → TopologyNode; instrument observed stage timings. No behavior change.
  2. Phase 1 — merged scoring: cost model (mem-bw/compute + directed edge time; pipeline TPOT = max over stages) in skippy-coordinator, legality from skippy-topology; absent-signal fallback must be bit-identical to current placement.
  3. Phase 2 — placement sim: deterministic scenario → planner → assert, in CI. Property tests: slower link moves the boundary; half-bandwidth node gets fewer layers; absent signals reproduce current placement.
  4. Phase 3 — execution sim: discrete-event pipeline, workload traces, TTFT/TPOT/throughput curves. Calibration gate: reproduce docs/BENCHMARKS.md ratios within tolerance.
  5. Phase 4 — default-on after staging A/B vs capacity-only.
  6. Phase 5 — adaptive replanning with hysteresis + migration budgets.

Scenario corpus

Node tiers from consumer laptops (CPU/iGPU) through A100/H100/MI300X; link tiers from loopback through intercontinental WAN, directed/asymmetric edges first-class; (hardware, backend, quant) triples; spec priors upgraded to mesh-llm-gpu-bench measurements over time. In-repo TOML shared by CI, planner tests, and sims.

Acceptance gates

  • Parity: signal-less inputs produce identical plans to the current planner
  • Calibration: execution sim reproduces BENCHMARKS.md anchors within tolerance
  • A/B: no regression vs capacity-only on staging meshes before default-on

Cross-team: simulator data realism (consumer → datacenter, multi-backend) flagged for @mic's agents once this issue lands.

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