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vivado_9580.backup.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Mon Jan 17 10:25:44 2022
# Process ID: 9580
# Current directory: D:/Projet_instrum_MHAH
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent4808 D:\Projet_instrum_MHAH\Projet_instrum_MHAH.xpr
# Log file: D:/Projet_instrum_MHAH/vivado.log
# Journal file: D:/Projet_instrum_MHAH\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/Projet_instrum_MHAH/Projet_instrum_MHAH.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 1091.258 ; gain = 0.000
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1091.258 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 1091.258 ; gain = 0.000
run 4ms
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/7segment_decoder.vhd w ]
add_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/7segment_decoder.vhd
update_compile_order -fileset sources_1
export_ip_user_files -of_objects [get_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/7segment_decoder.vhd] -no_script -reset -force -quiet
remove_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/7segment_decoder.vhd
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd w ]
add_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd
update_compile_order -fileset sources_1
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/Data_ctrler.vhd w ]
add_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/Data_ctrler.vhd
update_compile_order -fileset sources_1
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd w ]
add_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd
update_compile_order -fileset sources_1
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd w ]
add_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd
update_compile_order -fileset sources_1
set_property top display_module [current_fileset]
update_compile_order -fileset sources_1
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a100tcsg324-3
Top: display_module
INFO: [Device 21-403] Loading part xc7a100tcsg324-3
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1533.305 ; gain = 251.941
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'display_module' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:48]
INFO: [Synth 8-3491] module 'display_decoder' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd:32' bound to instance 'U_display_decoder' of component 'display_decoder' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:83]
INFO: [Synth 8-638] synthesizing module 'display_decoder' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'display_decoder' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd:38]
INFO: [Synth 8-637] synthesizing blackbox instance 'U_data_ctrler' of component 'Data_ctrler' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:89]
ERROR: [Synth 8-549] port width mismatch for port 'dp_vector': port width = 4, actual width = 8 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:98]
ERROR: [Synth 8-285] failed synthesizing module 'display_module' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:48]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1609.910 ; gain = 328.547
---------------------------------------------------------------------------------
RTL Elaboration failed
6 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a100tcsg324-3
Top: display_module
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1609.910 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'display_module' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:48]
INFO: [Synth 8-3491] module 'display_decoder' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd:32' bound to instance 'U_display_decoder' of component 'display_decoder' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:82]
INFO: [Synth 8-638] synthesizing module 'display_decoder' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'display_decoder' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_decoder.vhd:38]
INFO: [Synth 8-637] synthesizing blackbox instance 'U_data_ctrler' of component 'Data_ctrler' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:88]
INFO: [Synth 8-3491] module 'AN_generator' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd:35' bound to instance 'U_AN_generator' of component 'AN_generator' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:100]
INFO: [Synth 8-638] synthesizing module 'AN_generator' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd:42]
INFO: [Synth 8-637] synthesizing blackbox instance 'U_clk_divider' of component 'clk_divider' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd:54]
WARNING: [Synth 8-614] signal 'clk' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd:60]
WARNING: [Synth 8-614] signal 'AN_interne' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd:60]
INFO: [Synth 8-256] done synthesizing module 'AN_generator' (2#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/AN_generator.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'display_module' (3#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/display_module.vhd:48]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1609.910 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1616.930 ; gain = 7.020
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1616.930 ; gain = 7.020
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1616.930 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'global_output[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
WARNING: [Vivado 12-584] No ports matched 'global_output[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
WARNING: [Vivado 12-584] No ports matched 'global_output[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
WARNING: [Vivado 12-584] No ports matched 'global_output[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
WARNING: [Vivado 12-584] No ports matched 'global_output[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
WARNING: [Vivado 12-584] No ports matched 'global_output[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
WARNING: [Vivado 12-584] No ports matched 'global_output[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
WARNING: [Vivado 12-584] No ports matched 'global_output[7]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
WARNING: [Vivado 12-584] No ports matched 'vauxn3'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
WARNING: [Vivado 12-584] No ports matched 'vauxp3'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Finished Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/display_module_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1710.797 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
RTL Elaboration Complete: : Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 1812.508 ; gain = 202.598
12 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 1812.508 ; gain = 202.598
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/main.vhd w ]
add_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/main.vhd
update_compile_order -fileset sources_1
set_property top test_ADC [current_fileset]
update_compile_order -fileset sources_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1872.645 ; gain = 22.871
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:42]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:77]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
WARNING: [Synth 8-614] signal 'value_in' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:26]
WARNING: [Synth 8-614] signal 'buffer1' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:26]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:83]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (2#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:88]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'ADC' declared at 'd:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (3#1) [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (4#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-256] done synthesizing module 'test_ADC' (5#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:42]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1913.035 ; gain = 63.262
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1934.867 ; gain = 85.094
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1934.867 ; gain = 85.094
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1936.074 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'BCD[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:57]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:57]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:58]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:58]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:59]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:59]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:60]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:60]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:61]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:61]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:62]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:62]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:63]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:63]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'dp_int'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:64]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:64]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:65]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:65]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:66]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:66]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:67]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:67]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:68]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:68]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:69]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:69]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:70]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:70]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:71]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:71]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[7]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:72]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:72]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[7]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 1936.074 ; gain = 86.301
set_property top test_filter [current_fileset]
update_compile_order -fileset sources_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1936.074 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_filter' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:79]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-3491] module 'filter' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:33' bound to instance 'U_filter' of component 'filter' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:84]
INFO: [Synth 8-638] synthesizing module 'filter' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:41]
INFO: [Synth 8-256] done synthesizing module 'filter' (2#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:41]
INFO: [Synth 8-3491] module 'ADC_12b' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:34' bound to instance 'U_ADC_12b' of component 'ADC_12b' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:91]
INFO: [Synth 8-638] synthesizing module 'ADC_12b' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:76]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'ADC' declared at 'd:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (3#1) [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (4#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:85]
INFO: [Synth 8-256] done synthesizing module 'ADC_12b' (5#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:98]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
WARNING: [Synth 8-614] signal 'value_in' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:26]
WARNING: [Synth 8-614] signal 'buffer1' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:26]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (6#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-256] done synthesizing module 'test_filter' (7#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1936.074 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1936.074 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1936.074 ; gain = 0.000
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1936.074 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_12b/U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_12b/U_ADC_global/U_ADC/U0'
Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'BCD[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:57]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:57]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:58]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:58]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:59]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:59]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:60]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:60]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:61]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:61]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:62]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:62]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:63]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:63]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'dp_int'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:64]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:64]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:65]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:65]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:66]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:66]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:67]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:67]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:68]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:68]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:69]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:69]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:70]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:70]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:71]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:71]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[7]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:72]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:72]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 1964.145 ; gain = 28.070
set_property top test_derivation [current_fileset]
update_compile_order -fileset sources_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1975.223 ; gain = 5.953
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_derivation' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_derivation.vhd:22]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_derivation.vhd:60]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-3491] module 'derivation' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/derivation.vhd:14' bound to instance 'U_derivation' of component 'derivation' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_derivation.vhd:65]
INFO: [Synth 8-638] synthesizing module 'derivation' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/derivation.vhd:22]
INFO: [Synth 8-256] done synthesizing module 'derivation' (2#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/derivation.vhd:22]
INFO: [Synth 8-3491] module 'ADC_12b' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:34' bound to instance 'U_ADC_12b' of component 'ADC_12b' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_derivation.vhd:72]
INFO: [Synth 8-638] synthesizing module 'ADC_12b' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:76]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'ADC' declared at 'd:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (3#1) [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (4#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:85]
INFO: [Synth 8-256] done synthesizing module 'ADC_12b' (5#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_derivation.vhd:79]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
WARNING: [Synth 8-614] signal 'value_in' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:26]
WARNING: [Synth 8-614] signal 'buffer1' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:26]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (6#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-256] done synthesizing module 'test_derivation' (7#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_derivation.vhd:22]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1975.227 ; gain = 5.957
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1977.273 ; gain = 8.004
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1977.273 ; gain = 8.004
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.812 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_12b/U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_12b/U_ADC_global/U_ADC/U0'
Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'BCD[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:57]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:57]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:58]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:58]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:59]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:59]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:60]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:60]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:61]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:61]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:62]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:62]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'BCD[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:63]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:63]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'dp_int'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:64]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:64]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[0]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:65]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:65]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[1]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:66]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:66]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[2]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:67]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:67]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[3]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:68]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:68]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[4]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:69]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:69]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[5]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:70]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:70]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[6]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:71]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:71]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'AN[7]'. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:72]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:72]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 1980.812 ; gain = 11.543
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Mon Jan 17 11:44:16 2022...