Questions about optiga initialization #100
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Hi @ShaikKarishma0, any news about question '2'? |
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12 ms is the delay used inside the code, with all measured internal delays for the code execution etc. 15 ms is the value which shall be used as a guaranteed start-up time of the application. |
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Thank you @ShaikKarishma0 . If that's so that means i have to measure the reset time for every hardware and tweak the define if necessary. |
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Hi,
We have been working on optiga for 2 years and mostly everything is working great.
We are facing a rare issue on an NXP based board where initializations seems to fail sometimes after a test of 5K initializations.
I'm still investigating about it, but meanwhile i would like to ask you a couple of confirmations.
This is the log of Optiga initialization and read of slot 0 public key when eveything is working fine:
This is the log when optiga inits but read of slot 0 fails (sometimes it fails during initialization but it is hard to replicate).
1) Is it normal to have those "PAL Error" sometimes during initialization? Even when the result is success.
On the comments of the optiga library code i read that optiga may be sleeping, but since sleep occurs after 20ms of IDLE time it seems a bit strange to me (i verified the timings). Maybe the register read/write does not count as state change?
From the oscilloscope i can see that those "PAL Error" are caused by a NACK on I2C bus.
2) On the datasheet i see that startup time is 15ms, but STARTUP_TIME_MSEC is 12ms. Is it correct?
Can you answer me on those two points? Do you have any idea of the possible issue?
Thanks
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