testingigo_all.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 10.1 Build 153 11/29/2010 SJ Web Edition
# Date created = 11:46:54  February 11, 2011
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		testingigo_all_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #



# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:31:52  JANUARY 11, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 11.0
set_global_assignment -name MISC_FILE "C:/Users/Carla/Desktop/tagger/timetag/firmware/testingigo_all.dpf"
set_global_assignment -name MISC_FILE "C:/Documents and Settings/Ben/Desktop/timetag/firmware/testingigo_all.dpf"
set_global_assignment -name MISC_FILE "C:/Documents and Settings/Ben/Desktop/clean-timetag/testingigo_all.dpf"

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_22 -to fx2_flags[2]
set_location_assignment PIN_21 -to fx2_flags[1]
set_location_assignment PIN_18 -to fx2_flags[0]
set_location_assignment PIN_91 -to ext_clk
set_location_assignment PIN_63 -to push_button -disable
set_location_assignment PIN_72 -to led[0]
set_location_assignment PIN_71 -to led[1]
set_location_assignment PIN_17 -to fx2_clk
set_location_assignment PIN_40 -to fx2_fd[7]
set_location_assignment PIN_41 -to fx2_fd[6]
set_location_assignment PIN_42 -to fx2_fd[5]
set_location_assignment PIN_43 -to fx2_fd[4]
set_location_assignment PIN_9 -to fx2_fd[3]
set_location_assignment PIN_8 -to fx2_fd[2]
set_location_assignment PIN_7 -to fx2_fd[1]
set_location_assignment PIN_4 -to fx2_fd[0]
set_location_assignment PIN_24 -to fx2_slrd
set_location_assignment PIN_25 -to fx2_slwr
set_location_assignment PIN_32 -to fx2_sloe
set_location_assignment PIN_31 -to fx2_wu2
set_location_assignment PIN_27 -to fx2_pktend
set_location_assignment PIN_30 -to fx2_fifoadr[0]
set_location_assignment PIN_28 -to fx2_fifoadr[1]

# Classic Timing Assignments
# ==========================
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON
set_global_assignment -name FMAX_REQUIREMENT "48 MHz"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name SEARCH_PATH "c:\\users\\carla\\desktop\\tagger\\hssdrc\\trunk\\include"
set_global_assignment -name TOP_LEVEL_ENTITY fx2_timetag

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C5T144C8
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE ON

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name SETUP_HOLD_DETECTION OFF
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS ON
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE testingigo_all.vwf
set_global_assignment -name END_TIME "100 ns"

# start CLOCK(FX2 Clock)
# ----------------------

	# Classic Timing Assignments
	# ==========================
set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id "FX2 Clock"

# end CLOCK(FX2 Clock)
# --------------------

# start CLOCK(External clock)
# ---------------------------

	# Classic Timing Assignments
	# ==========================
set_global_assignment -name FMAX_REQUIREMENT "1003 MHz" -section_id "External clock"

# end CLOCK(External clock)
# -------------------------

# -------------------------
# start ENTITY(fx2_timetag)

	# Classic Timing Assignments
	# ==========================
set_instance_assignment -name CLOCK_SETTINGS "FX2 Clock" -to fx2_clk
set_instance_assignment -name CLOCK_SETTINGS "External clock" -to ext_clk

	# Fitter Assignments
	# ==================
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to fx2_clk

	# start LOGICLOCK_REGION(Root Region)
	# -----------------------------------

		# LogicLock Region Assignments
		# ============================
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

	# end LOGICLOCK_REGION(Root Region)
	# ---------------------------------

	# start DESIGN_PARTITION(Top)
	# ---------------------------

		# Incremental Compilation Assignments
		# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

	# end DESIGN_PARTITION(Top)
	# -------------------------

# end ENTITY(fx2_timetag)
# -----------------------
set_global_assignment -name MISC_FILE "/home/bgamari/trees/timetag-fpga/testingigo_all.dpf"
set_location_assignment PIN_74 -to strobe_in[3]
set_location_assignment PIN_73 -to strobe_in[2]
set_location_assignment PIN_70 -to strobe_in[1]
set_location_assignment PIN_69 -to strobe_in[0]
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, M101, M102, M103, M104, M105"
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "altpll0:b2v_inst2|altpll:altpll_component|_clk0"
set_instance_assignment -name STRATIX_CARRY_CHAIN_LENGTH 16 -to "timetag:tagger|apdtimer_all:apdtimer|event_tagger:tagger|timer"
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_79 -to delta_chs[0]
set_location_assignment PIN_92 -to delta_chs[1]
set_location_assignment PIN_93 -to delta_chs[2]
set_location_assignment PIN_97 -to delta_chs[3]
set_global_assignment -name VERILOG_FILE led_blinker.v
set_global_assignment -name VERILOG_FILE sequencer.v
set_global_assignment -name VERILOG_FILE config.v
set_global_assignment -name VERILOG_FILE strobe_latch.v
set_global_assignment -name VERILOG_FILE fx2_bidir.v
set_global_assignment -name VERILOG_FILE reg_manager.v
set_global_assignment -name VERILOG_FILE register.v
set_global_assignment -name VERILOG_FILE event_tagger.v
set_global_assignment -name VERILOG_FILE fx2_timetag.v
set_global_assignment -name VERILOG_FILE timetag.v
set_global_assignment -name VERILOG_FILE runonce.v
set_global_assignment -name VERILOG_FILE sample_multiplexer.v
set_global_assignment -name VERILOG_FILE altpll0.v
set_global_assignment -name VERILOG_FILE apdtimer_all.v
set_global_assignment -name VERILOG_FILE fx2_test.v
set_global_assignment -name QIP_FILE sample_fifo.qip
set_global_assignment -name SDC_FILE timetag.sdc
set_global_assignment -name VERILOG_FILE sample_fifo.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top