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patch-5.12-xenon0.20.diff
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diff -NurpP --minimal linux-5.12/arch/powerpc/Kconfig.debug linux-5.12-xenon/arch/powerpc/Kconfig.debug
--- linux-5.12/arch/powerpc/Kconfig.debug 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/Kconfig.debug 2021-06-01 21:43:02.547664369 +0200
@@ -257,6 +257,14 @@ config PPC_EARLY_DEBUG_PS3GELIC
Select this to enable early debugging for the PlayStation3 via
UDP broadcasts sent out through the Ethernet port.
+config PPC_EARLY_DEBUG_XENON
+ bool "Early debugging through Xenos framebuffer"
+ depends on PPC_XENON
+ select XENON_UDBG
+ help
+ Select this to enable early debugging for the Xenon via
+ early framebuffer support.
+
config PPC_EARLY_DEBUG_OPAL_RAW
bool "OPAL raw console"
depends on HVC_OPAL
diff -NurpP --minimal linux-5.12/arch/powerpc/boot/.gitignore linux-5.12-xenon/arch/powerpc/boot/.gitignore
--- linux-5.12/arch/powerpc/boot/.gitignore 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/boot/.gitignore 2021-06-01 21:43:02.547664369 +0200
@@ -33,6 +33,7 @@ zImage.maple
zImage.miboot
zImage.pmac
zImage.pseries
+zImage.xenon
zconf.h
zlib.h
zutil.h
diff -NurpP --minimal linux-5.12/arch/powerpc/boot/Makefile linux-5.12-xenon/arch/powerpc/boot/Makefile
--- linux-5.12/arch/powerpc/boot/Makefile 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/boot/Makefile 2021-06-01 21:43:02.547664369 +0200
@@ -264,6 +264,7 @@ image-$(CONFIG_PPC_POWERNV) += zImage.p
image-$(CONFIG_PPC_MAPLE) += zImage.maple
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
image-$(CONFIG_PPC_PS3) += dtbImage.ps3
+image-$(CONFIG_PPC_XENON) += zImage.xenon
image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
@@ -399,6 +400,11 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
+$(obj)/zImage.xenon: $(obj)/vmlinux.strip
+ @$(OBJCOPY) -O elf32-powerpc $< $@
+ @test -e /mnt/e/Misc/tftpd64 && \
+ cp -f $@ /mnt/e/Misc/tftpd64/vmlinux || true
+
$(obj)/uImage: vmlinux $(wrapperbits) FORCE
$(call if_changed,wrap,uboot)
diff -NurpP --minimal linux-5.12/arch/powerpc/boot/dts/xenon.dts linux-5.12-xenon/arch/powerpc/boot/dts/xenon.dts
--- linux-5.12/arch/powerpc/boot/dts/xenon.dts 1970-01-01 01:00:00.000000000 +0100
+++ linux-5.12-xenon/arch/powerpc/boot/dts/xenon.dts 2021-06-01 21:43:02.547664369 +0200
@@ -0,0 +1,131 @@
+/*
+ * xenon.dts - Xbox360 Game Console device tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Xenon Game Console";
+ compatible = "XENON";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ /*
+ * Bootargs will be created here, as well as initrd properties if relevant
+ */
+ chosen {
+ linux,platform = <0x00000801>;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x1e000000>;
+ };
+
+ cpus {
+ #cpus = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ Xenon,PPE@0 {
+ device_type = "cpu";
+ linux,boot-cpu;
+ reg = <0>;
+ ibm,ppc-interrupt-server#s = <0 1>;
+ timebase-frequency = <0x2FAF080>; // 50 MHz
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x80>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x80>;
+
+ /* this must be configured with regard to the HID6:LB value */
+ ibm,segment-page-sizes = <
+ 0xC 0 1 0xc 0 // 4k page
+ 0x10 0x100 1 0x10 00 // 64k pages
+ 0x18 0x110 1 0x18 01 // 16M pages
+ >;
+ };
+ Xenon,PPE@1 {
+ device_type = "cpu";
+ reg = <2>;
+ ibm,ppc-interrupt-server#s = <2 3>;
+ timebase-frequency = <0x2FAF080>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x80>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x80>;
+ };
+ Xenon,PPE@2 {
+ device_type = "cpu";
+ reg = <4>;
+ ibm,ppc-interrupt-server#s = <4 5>;
+ timebase-frequency = <0x2FAF080>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x80>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x80>;
+ };
+ };
+
+ pci {
+ compatible = "xenon";
+ device_type = "pci";
+ #address-cells = <3>; // phy up, mid, low
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <0x40000>;
+ // interrupts = <18 2>;
+ interrupt-map-mask = <0xf900 0 0 0>; // type, lower, upper, irq
+
+ interrupt-map = <
+ 0x0000 0 0 0 0x40000 0x40 // XMA
+ 0x0800 0 0 0 0x40000 0x24 // SATA cdrom
+ 0x1000 0 0 0 0x40000 0x20 // SATA disk
+ 0x2000 0 0 0 0x40000 0x2c // USB OHCI #1
+ 0x2100 0 0 0 0x40000 0x30 // USB EHCI #1
+ 0x2800 0 0 0 0x40000 0x34 // USB OHCI #2
+ 0x2900 0 0 0 0x40000 0x38 // USB EHCI #2
+ 0x3800 0 0 0 0x40000 0x4c // Enet
+ 0x4000 0 0 0 0x40000 0x18 // Flash
+ 0x4800 0 0 0 0x40000 0x44 // audio out
+ 0x5000 0 0 0 0x40000 0x14 // SMM, GPIO, ...
+ 0x7800 0 0 0 0x40000 0x58 // Xenos
+ >;
+
+ bus-range = <0 0>;
+ ranges = <
+ 0x02000000 0x00000000 0x80000000 0x00000200 0x80000000 0x80000000 // PCI space at 80000000 is mapped to 200 80000000
+ 0x02000000 0x00000000 0x00000000 0x00000000 0x00000000 0x20000000 // RAM is 1:1 mapped
+ >;
+ };
+
+ interrupt-controller {
+ compatible = "xenon";
+ linux,phandle = <0x40000>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ built-in;
+ reg = <0x00000200 0x00050000 0x6000>;
+ interrupts = <
+ 0x7c 0x78 0x74 0x70 0x6c 0x68 0x64 0x60
+ 0x5c 0x58 0x54 0x50 0x4c 0x48 0x44 0x40
+ 0x3c 0x38 0x34 0x30 0x2c 0x28 0x24 0x20
+ 0x1c 0x18 0x14 0x10 0x0c 0x08 0x04
+ >;
+ };
+};
diff -NurpP --minimal linux-5.12/arch/powerpc/include/asm/cputable.h linux-5.12-xenon/arch/powerpc/include/asm/cputable.h
--- linux-5.12/arch/powerpc/include/asm/cputable.h 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/include/asm/cputable.h 2021-06-01 21:43:02.547664369 +0200
@@ -456,6 +456,10 @@ static inline void cpu_feature_keys_init
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
+#define CPU_FTRS_XENON (CPU_FTR_LWSYNC | \
+ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
+ CPU_FTR_CELL_TB_BUG )
#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
@@ -513,6 +517,9 @@ enum {
#ifdef CONFIG_PPC_E500MC
CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
#endif
+#ifdef CONFIG_PPC_XENON
+ CPU_FTRS_XENON |
+#endif
0,
};
#endif /* __powerpc64__ */
diff -NurpP --minimal linux-5.12/arch/powerpc/include/asm/mmu.h linux-5.12-xenon/arch/powerpc/include/asm/mmu.h
--- linux-5.12/arch/powerpc/include/asm/mmu.h 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/include/asm/mmu.h 2021-06-01 21:43:02.547664369 +0200
@@ -141,6 +141,8 @@
#define MMU_FTRS_POWER10 MMU_FTRS_POWER6
#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
MMU_FTR_CI_LARGE_PAGE
+#define MMU_FTRS_XENON MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+ MMU_FTR_CI_LARGE_PAGE
#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
#ifndef __ASSEMBLY__
diff -NurpP --minimal linux-5.12/arch/powerpc/include/asm/udbg.h linux-5.12-xenon/arch/powerpc/include/asm/udbg.h
--- linux-5.12/arch/powerpc/include/asm/udbg.h 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/include/asm/udbg.h 2021-06-01 21:43:02.547664369 +0200
@@ -53,6 +53,7 @@ extern void __init udbg_init_ehv_bc(void
extern void __init udbg_init_ps3gelic(void);
extern void __init udbg_init_debug_opal_raw(void);
extern void __init udbg_init_debug_opal_hvsi(void);
+extern void __init udbg_init_xenon(void);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_UDBG_H */
diff -NurpP --minimal linux-5.12/arch/powerpc/kernel/cputable.c linux-5.12-xenon/arch/powerpc/kernel/cputable.c
--- linux-5.12/arch/powerpc/kernel/cputable.c 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/kernel/cputable.c 2021-06-01 21:43:02.551664435 +0200
@@ -539,6 +539,18 @@ static struct cpu_spec __initdata cpu_sp
.oprofile_cpu_type = "ppc64/cell-be",
.platform = "ppc-cell-be",
},
+ { /* Xenon */
+ .pvr_mask = 0xffff0000,
+ .pvr_value = 0x00710000,
+ .cpu_name = "Xenon",
+ .cpu_features = CPU_FTRS_XENON,
+ .cpu_user_features = COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP |
+ PPC_FEATURE_SMT,
+ .mmu_features = MMU_FTRS_XENON,
+ .icache_bsize = 128,
+ .dcache_bsize = 128,
+ .platform = "xenon",
+ },
{ /* PA Semi PA6T */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00900000,
diff -NurpP --minimal linux-5.12/arch/powerpc/kernel/misc_64.S linux-5.12-xenon/arch/powerpc/kernel/misc_64.S
--- linux-5.12/arch/powerpc/kernel/misc_64.S 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/kernel/misc_64.S 2021-06-01 21:43:02.551664435 +0200
@@ -95,7 +95,7 @@ _GLOBAL(rmci_off)
blr
#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
-#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
+#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) || defined(CONFIG_PPC_XENON)
/*
* Do an IO access in real mode
diff -NurpP --minimal linux-5.12/arch/powerpc/kernel/prom.c linux-5.12-xenon/arch/powerpc/kernel/prom.c
--- linux-5.12/arch/powerpc/kernel/prom.c 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/kernel/prom.c 2021-06-01 21:43:02.551664435 +0200
@@ -326,6 +326,7 @@ static int __init early_init_dt_scan_cpu
intserv = of_get_flat_dt_prop(node, "reg", &len);
nthreads = len / sizeof(int);
+ DBG("%s with %d threads \"%s\" v%d", type, nthreads, uname, fdt_version(initial_boot_params));
/*
* Now see if any of these threads match our boot cpu.
diff -NurpP --minimal linux-5.12/arch/powerpc/kernel/udbg.c linux-5.12-xenon/arch/powerpc/kernel/udbg.c
--- linux-5.12/arch/powerpc/kernel/udbg.c 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/kernel/udbg.c 2021-06-01 21:43:02.551664435 +0200
@@ -67,6 +67,8 @@ void __init udbg_early_init(void)
udbg_init_debug_opal_raw();
#elif defined(CONFIG_PPC_EARLY_DEBUG_OPAL_HVSI)
udbg_init_debug_opal_hvsi();
+#elif defined(CONFIG_PPC_EARLY_DEBUG_XENON)
+ udbg_init_xenon();
#endif
#ifdef CONFIG_PPC_EARLY_DEBUG
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/Kconfig linux-5.12-xenon/arch/powerpc/platforms/Kconfig
--- linux-5.12/arch/powerpc/platforms/Kconfig 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/platforms/Kconfig 2021-06-01 21:43:02.551664435 +0200
@@ -20,6 +20,7 @@ source "arch/powerpc/platforms/embedded6
source "arch/powerpc/platforms/44x/Kconfig"
source "arch/powerpc/platforms/40x/Kconfig"
source "arch/powerpc/platforms/amigaone/Kconfig"
+source "arch/powerpc/platforms/xenon/Kconfig"
config KVM_GUEST
bool "KVM Guest support"
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/Makefile linux-5.12-xenon/arch/powerpc/platforms/Makefile
--- linux-5.12/arch/powerpc/platforms/Makefile 2021-04-25 22:49:08.000000000 +0200
+++ linux-5.12-xenon/arch/powerpc/platforms/Makefile 2021-06-01 21:43:02.551664435 +0200
@@ -20,5 +20,6 @@ obj-$(CONFIG_PPC_MAPLE) += maple/
obj-$(CONFIG_PPC_PASEMI) += pasemi/
obj-$(CONFIG_PPC_CELL) += cell/
obj-$(CONFIG_PPC_PS3) += ps3/
+obj-$(CONFIG_PPC_XENON) += xenon/
obj-$(CONFIG_EMBEDDED6xx) += embedded6xx/
obj-$(CONFIG_AMIGAONE) += amigaone/
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/xenon/Kconfig linux-5.12-xenon/arch/powerpc/platforms/xenon/Kconfig
--- linux-5.12/arch/powerpc/platforms/xenon/Kconfig 1970-01-01 01:00:00.000000000 +0100
+++ linux-5.12-xenon/arch/powerpc/platforms/xenon/Kconfig 2021-06-01 21:43:02.551664435 +0200
@@ -0,0 +1,18 @@
+config PPC_XENON
+ bool "Xenon"
+ depends on PPC64
+ select PPC_NATIVE
+ select DMA_VIRT_OPS
+ select HAVE_PCI
+ default y
+ help
+ This option enables support for the Xbox 360 game console
+ without a hypervisor.
+
+config XENON_UDBG
+ bool "Xenon Early Console"
+ depends on PPC_XENON
+ select FONT_SUPPORT
+ help
+ This option enables early debugging over ethernet for the
+ Xenon platform.
\ No newline at end of file
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/xenon/Makefile linux-5.12-xenon/arch/powerpc/platforms/xenon/Makefile
--- linux-5.12/arch/powerpc/platforms/xenon/Makefile 1970-01-01 01:00:00.000000000 +0100
+++ linux-5.12-xenon/arch/powerpc/platforms/xenon/Makefile 2021-06-01 21:43:02.551664435 +0200
@@ -0,0 +1,4 @@
+obj-y += setup.o interrupt.o pci.o time.o hardware.o
+
+obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_XENON_UDBG) += xe_udbg.o
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/xenon/hardware.c linux-5.12-xenon/arch/powerpc/platforms/xenon/hardware.c
--- linux-5.12/arch/powerpc/platforms/xenon/hardware.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-5.12-xenon/arch/powerpc/platforms/xenon/hardware.c 2021-06-01 21:43:02.551664435 +0200
@@ -0,0 +1,37 @@
+/*
+ * Xenon hardware related routines.
+ *
+ * Copyright (C) 2010 Herbert Poetzl
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+
+static int __init xenon_hwmon_init(void)
+{
+ struct platform_device *pdev;
+
+ pdev = platform_device_register_simple("xenon-hwmon", -1, NULL, 0);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+
+module_init(xenon_hwmon_init);
+
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/xenon/interrupt.c linux-5.12-xenon/arch/powerpc/platforms/xenon/interrupt.c
--- linux-5.12/arch/powerpc/platforms/xenon/interrupt.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-5.12-xenon/arch/powerpc/platforms/xenon/interrupt.c 2021-06-01 21:43:02.551664435 +0200
@@ -0,0 +1,372 @@
+/*
+ * Xenon interrupt controller,
+ *
+ * Maintained by: Felix Domke <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License v2
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqnr.h>
+#include <linux/module.h>
+#include <linux/percpu.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/irqdesc.h>
+
+#ifdef CONFIG_SMP
+#include <linux/smp.h>
+#endif
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/prom.h>
+#include <asm/ptrace.h>
+#include <asm/machdep.h>
+#include <asm/udbg.h>
+
+#include "interrupt.h"
+
+#define DEBUG
+#if defined(DEBUG)
+#define DBG udbg_printf
+#else
+#define DBG pr_debug
+#endif
+
+static void *iic_base, // 00050000
+ *bridge_base, // ea000000
+ *biu, // e1000000
+ *graphics; // ec800000
+static struct irq_domain *host;
+
+#define XENON_NR_IRQS 128
+
+#define PRIO_IPI_4 0x08
+#define PRIO_IPI_3 0x10
+#define PRIO_SMM 0x14
+#define PRIO_SFCX 0x18
+#define PRIO_SATA_HDD 0x20
+#define PRIO_SATA_CDROM 0x24
+#define PRIO_OHCI_0 0x2C
+#define PRIO_EHCI_0 0x30
+#define PRIO_OHCI_1 0x34
+#define PRIO_EHCI_1 0x38
+#define PRIO_XMA 0x40
+#define PRIO_AUDIO 0x44
+#define PRIO_ENET 0x4C
+#define PRIO_XPS 0x54
+#define PRIO_GRAPHICS 0x58
+#define PRIO_PROFILER 0x60
+#define PRIO_BIU 0x64
+#define PRIO_IOC 0x68
+#define PRIO_FSB 0x6C
+#define PRIO_IPI_2 0x70
+#define PRIO_CLOCK 0x74
+#define PRIO_IPI_1 0x78
+#define PRIO_NONE 0x7C
+
+/*
+ * Important interrupt registers (per CPU):
+ *
+ * 0x00: CPU_WHOAMI
+ * 0x08: CPU_CURRENT_TASK_PRI: only receive interrupts higher than this
+ * 0x10: CPU_IPI_DISPATCH_0
+ * 0x18: unused(?)
+ * 0x20: ? (read changes)
+ * 0x28: ? (read changes)
+ * 0x30: ? (read changes)
+ * 0x38: same value as 0x20(?) (read changes)
+ * 0x40: unused(?)
+ * 0x48: unused(?)
+ * 0x50: ACK
+ * 0x58: ACK + set CPU_CURRENT_TASK_PRI
+ * 0x60: EOI
+ * 0x68: EOI + set CPU_CURRENT_TASK_PRI
+ * 0x70: interrupt MCACK? mask? max interrupt? CPU dies when writing stuff that isn't 0x7C
+ * 0xF0: ?
+ */
+
+/* CPU IRQ -> bridge (PCI) IRQ */
+static const uint8_t xenon_pci_irq_map[] = {
+ /* 0x00 */ -1,
+ /* 0x04 */ -1,
+ /* PRIO_IPI_4 */ -1,
+ /* 0x0C */ -1,
+ /* PRIO_IPI_3 */ -1,
+ /* PRIO_SMM */ 3,
+ /* PRIO_SFCX */ 13,
+ /* 0x1C */ -1,
+ /* PRIO_SATA_HDD */ 2,
+ /* PRIO_SATA_CDROM */ 1,
+ /* 0x28 */ -1,
+ /* PRIO_OHCI_0 */ 4,
+ /* PRIO_EHCI_0 */ 5,
+ /* PRIO_OHCI_1 */ 6,
+ /* PRIO_EHCI_1 */ 7,
+ /* 0x3C */ -1,
+ /* PRIO_XMA */ 11,
+ /* PRIO_AUDIO */ 12,
+ /* 0x48 */ -1,
+ /* PRIO_ENET */ 10,
+ /* 0x50 */ -1,
+ /* PRIO_XPS */ -1,
+ /* PRIO_GRAPHICS */ -1,
+ /* 0x5C */ -1,
+ /* PRIO_PROFILER */ -1,
+ /* PRIO_BIU */ -1,
+ /* PRIO_IOC */ -1,
+ /* PRIO_FSB */ -1,
+ /* PRIO_IPI_2 */ -1,
+ /* PRIO_CLOCK */ 0,
+ /* PRIO_IPI_1 */ -1,
+ /* PRIO_NONE */ -1,
+};
+
+static void disconnect_pci_irq(int prio)
+{
+ int i;
+
+ printk(KERN_INFO "xenon IIC: disconnect irq 0x%.2X\n", prio);
+
+ i = xenon_pci_irq_map[prio >> 2];
+ if (i != -1) {
+ writel(0, bridge_base + 0x10 + i * 4);
+ }
+}
+
+/* connects a PCI IRQ to a CPU */
+static void connect_pci_irq(int prio, int target_cpu)
+{
+ uint8_t i;
+
+ printk(KERN_INFO "xenon IIC: connect irq 0x%.2X\n", prio);
+
+ i = xenon_pci_irq_map[prio >> 2];
+ if (i != -1) {
+ /*
+ * Bits:
+ * 0x00800000 = enable(?)
+ * 0x00200000 = latched
+ * 0x00003F00 = cpu target
+ * 0x00000080 = level sensitive
+ * 0x0000007F = CPU IRQ
+ */
+ uint32_t bits = 0x00800080;
+ bits |= ((1 << target_cpu) & 0xFF) << 8;
+ bits |= (prio >> 2) & 0x3F;
+
+ writel(bits, bridge_base + 0x10 + i * 4);
+ }
+}
+
+static void iic_mask(struct irq_data *data)
+{
+ disconnect_pci_irq(data->hwirq);
+}
+
+static void iic_unmask(struct irq_data *data)
+{
+ connect_pci_irq(data->hwirq, 0);
+}
+
+static void xenon_ipi_send_mask(struct irq_data *data,
+ const struct cpumask *dest)
+{
+ int cpu = hard_smp_processor_id();
+ out_be64(iic_base + cpu * 0x1000 + 0x10,
+ ((cpumask_bits(dest)[0] << 16) & 0x3F) | (data->hwirq & 0x7C));
+}
+
+static struct irq_chip xenon_pic = {
+ .name = " XENON-PIC ",
+ .irq_mask = iic_mask,
+ .irq_unmask = iic_unmask,
+ .ipi_send_mask = xenon_ipi_send_mask,
+ .flags = 0,
+};
+
+void xenon_init_irq_on_cpu(int cpu)
+{
+ printk(KERN_INFO "xenon IIC: init on cpu %i\n", cpu);
+
+ /* init that cpu's interrupt controller */
+ out_be64(iic_base + cpu * 0x1000 + 0x70, 0x7C);
+ out_be64(iic_base + cpu * 0x1000 + 0x08, 0); /* Set priority to 0 */
+ out_be64(iic_base + cpu * 0x1000, 1 << cpu); /* "who am i" */
+
+ /* read in and ack all outstanding interrupts */
+ while (in_be64(iic_base + cpu * 0x1000 + 0x50) != PRIO_NONE);
+ out_be64(iic_base + cpu * 0x1000 + 0x68, 0); /* EOI and set priority to 0 */
+}
+
+/* Get an IRQ number from the pending state register of the IIC */
+static unsigned int iic_get_irq(void)
+{
+ int cpu = hard_smp_processor_id();
+ void *my_iic_base;
+ int index;
+
+ my_iic_base = iic_base + cpu * 0x1000;
+
+ /* read destructive pending interrupt */
+ index = in_be64(my_iic_base + 0x50) & 0x7C;
+ out_be64(my_iic_base + 0x60, 0x0); /* EOI this interrupt. */
+
+ /* HACK: we will handle some (otherwise unhandled) interrupts here
+ to prevent them flooding. */
+ switch (index) {
+ case PRIO_GRAPHICS:
+ writel(0, graphics + 0xed0); // RBBM_INT_CNTL
+ writel(0, graphics + 0x6540); // R500_DxMODE_INT_MASK
+ break;
+ case PRIO_IOC:
+ writel(0, biu + 0x4002c);
+ break;
+ case PRIO_CLOCK:
+ writel(0, bridge_base + 0x106C);
+ break;
+ default:
+ break;
+ }
+
+ /* No interrupt. This really shouldn't happen. */
+ if (index == PRIO_NONE) {
+ return NO_IRQ;
+ }
+
+ return irq_linear_revmap(host, index);
+}
+
+static int xenon_irq_host_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(virq, &xenon_pic, handle_percpu_irq);
+ return 0;
+}
+
+static int xenon_irq_host_match(struct irq_domain *h, struct device_node *node,
+ enum irq_domain_bus_token bus_token)
+{
+ return h->host_data != NULL && node == h->host_data;
+}
+
+static const struct irq_domain_ops xenon_irq_host_ops = {
+ .map = xenon_irq_host_map,
+ .match = xenon_irq_host_match,
+};
+
+void __init xenon_iic_init_IRQ(void)
+{
+ int i;
+ struct device_node *dn;
+ struct resource res;
+
+ printk(KERN_DEBUG "xenon IIC: init\n");
+ /* search for our interrupt controller inside the device tree */
+ for (dn = NULL;
+ (dn = of_find_node_by_name(dn, "interrupt-controller")) != NULL;) {
+ if (!of_device_is_compatible(dn, "xenon"))
+ continue;
+
+ if (of_address_to_resource(dn, 0, &res))
+ {
+ printk(KERN_WARNING "xenon IIC: Can't resolve addresses\n");
+ of_node_put(dn);
+ return;
+ }
+
+ iic_base = ioremap(res.start, 0x10000);
+
+ host = irq_domain_add_linear(NULL, XENON_NR_IRQS, &xenon_irq_host_ops, NULL);
+ host->host_data = of_node_get(dn);
+ BUG_ON(host == NULL);
+ irq_set_default_host(host);
+ }
+
+ ppc_md.get_irq = iic_get_irq;
+
+ bridge_base = ioremap(0xea000000, 0x10000);
+ biu = ioremap(0xe1000000, 0x2000000);
+ graphics = ioremap(0xec800000, 0x10000);
+
+ /* initialize interrupts */
+ writel(0, bridge_base);
+ writel(0x40000000, bridge_base + 4);
+
+ writel(0x40000000, biu + 0x40074);
+ writel(0xea000050, biu + 0x40078);
+
+ writel(0, bridge_base + 0xc); /* Interrupt mask register */
+ writel(0x3, bridge_base);
+
+ /* disconnect all PCI IRQs until they are requested */
+ for (i=0; i<0x10; ++i)
+ writel(0, bridge_base + 0x10 + i * 4);
+
+ xenon_init_irq_on_cpu(0);
+}
+
+#ifdef CONFIG_SMP
+
+static int ipi_to_prio(int ipi)
+{
+ switch (ipi) {
+ case PPC_MSG_NMI_IPI:
+ return PRIO_IPI_1;
+ break;
+ case PPC_MSG_CALL_FUNCTION:
+ return PRIO_IPI_2;
+ break;
+ case PPC_MSG_RESCHEDULE:
+ return PRIO_IPI_3;
+ break;
+ case PPC_MSG_TICK_BROADCAST:
+ return PRIO_IPI_4;
+ break;
+ default:
+ printk("unhandled ipi %d\n", ipi);
+ BUG();
+ }
+ return 0;
+}
+
+void xenon_cause_IPI(int target_cpu, int msg)
+{
+ int ipi_prio;
+ int cpu = hard_smp_processor_id();
+
+ ipi_prio = ipi_to_prio(msg);
+ out_be64(iic_base + cpu * 0x1000 + 0x10, (0x10000 << target_cpu) | ipi_prio);
+}
+
+static void xenon_request_ipi(int ipi)
+{
+ int virq;
+ int prio = ipi_to_prio(ipi);
+
+ virq = irq_create_mapping(host, prio);
+ if (virq == NO_IRQ) {
+ printk(KERN_ERR "xenon_request_ipi: failed to map IPI%d (%s)\n",
+ prio, smp_ipi_name[ipi]);
+ return;
+ }
+
+ if (smp_request_message_ipi(virq, ipi))
+ irq_dispose_mapping(virq);
+}
+
+void xenon_request_IPIs(void)
+{
+ xenon_request_ipi(PPC_MSG_TICK_BROADCAST);
+ xenon_request_ipi(PPC_MSG_CALL_FUNCTION);
+ xenon_request_ipi(PPC_MSG_RESCHEDULE);
+ xenon_request_ipi(PPC_MSG_NMI_IPI);
+}
+
+#endif
+
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/xenon/interrupt.h linux-5.12-xenon/arch/powerpc/platforms/xenon/interrupt.h
--- linux-5.12/arch/powerpc/platforms/xenon/interrupt.h 1970-01-01 01:00:00.000000000 +0100
+++ linux-5.12-xenon/arch/powerpc/platforms/xenon/interrupt.h 2021-06-01 21:43:02.551664435 +0200
@@ -0,0 +1,10 @@
+#ifndef XENON_INTERRUPT_H
+#define XENON_INTERRUPT_H
+
+extern void xenon_init_irq_on_cpu(int cpu);
+extern void __init xenon_iic_init_IRQ(void);
+extern void xenon_cause_IPI(int target, int msg);
+extern void xenon_request_IPIs(void);
+
+#endif /* ASM_XENON_PIC_H */
+
diff -NurpP --minimal linux-5.12/arch/powerpc/platforms/xenon/pci.c linux-5.12-xenon/arch/powerpc/platforms/xenon/pci.c
--- linux-5.12/arch/powerpc/platforms/xenon/pci.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-5.12-xenon/arch/powerpc/platforms/xenon/pci.c 2021-06-01 21:43:02.555664501 +0200
@@ -0,0 +1,306 @@
+/*
+ * Xenon PCI support
+ * Maintained by: Felix Domke <[email protected]>
+ * Minor modification by: wolie <[email protected]>
+ * based on:
+ * Copyright (C) 2004 Benjamin Herrenschmuidt ([email protected]),
+ * IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+
+#include <asm/sections.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/iommu.h>
+#include <asm/ppc-pci.h>
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#define OFFSET(bus, slot, func) \
+ ((((bus) << 8) + PCI_DEVFN(slot, func)) << 12)
+
+static int xenon_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val)
+{
+ struct pci_controller *hose;
+ unsigned int slot = PCI_SLOT(devfn);
+ unsigned int func = PCI_FUNC(devfn);
+ void* addr;
+
+ hose = pci_bus_to_host(bus);
+ if (hose == NULL)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ DBG("xenon_pci_read_config, slot %d, func %d\n", slot, func);
+
+#if 0
+ if (PCI_SLOT(devfn) >= 32)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (PCI_SLOT(devfn) == 3)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (PCI_SLOT(devfn) == 6)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (PCI_SLOT(devfn) == 0xB)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (PCI_FUNC(devfn) >= 2)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+ DBG("xenon_pci_read_config, %p, devfn=%d, offset=%d, len=%d\n", bus, devfn, offset, len);
+
+ addr = ((void*)hose->cfg_addr) + offset;
+
+ /* map GPU to slot 0x0f */
+ if (slot == 0x0f)
+ addr += OFFSET(0, 0x02, func);
+ else
+ addr += OFFSET(1, slot, func);
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ switch (len) {
+ case 1:
+ *val = in_8((u8 *)addr);
+ break;
+ case 2:
+ *val = in_le16((u16 *)addr);
+ break;
+ default:
+ *val = in_le32((u32 *)addr);
+ break;
+ }
+ DBG("->%08x\n", (int)*val);
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int xenon_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
+{
+ struct pci_controller *hose;
+ unsigned int slot = PCI_SLOT(devfn);
+ unsigned int func = PCI_FUNC(devfn);
+ void *addr;
+
+ hose = pci_bus_to_host(bus);
+ if (hose == NULL)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ DBG("xenon_pci_write_config, slot %d, func %d\n", slot, func);
+
+ if (PCI_SLOT(devfn) >= 32)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#if 0
+ if (PCI_SLOT(devfn) == 3)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+ DBG("xenon_pci_write_config, %p, devfn=%d, offset=%x, len=%d, val=%08x\n", bus, devfn, offset, len, val);
+
+ addr = ((void*)hose->cfg_addr) + offset;
+
+ /* map GPU to slot 0x0f */
+ if (slot == 0x0f)
+ addr += OFFSET(0, 0x02, func);
+ else
+ addr += OFFSET(1, slot, func);
+
+ if (len == 4)
+ DBG("was: %08x\n", readl(addr));
+ if (len == 2)
+ DBG("was: %04x\n", readw(addr));
+ if (len == 1)
+ DBG("was: %02x\n", readb(addr));
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ switch (len) {
+ case 1:
+ writeb(val, addr);
+ break;
+ case 2:
+ writew(val, addr);
+ break;
+ default:
+ writel(val, addr);
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops xenon_pci_ops =
+{
+ .read = xenon_pci_read_config,
+ .write = xenon_pci_write_config,
+};
+
+
+#if 1
+void __init xenon_pci_init(void)
+{
+ struct pci_controller *hose;
+ struct device_node *np, *root;
+ struct device_node *dev = NULL;
+
+ root = of_find_node_by_path("/");
+ if (root == NULL) {
+ printk(KERN_CRIT "xenon_pci_init: can't find root of device tree\n");
+ return;
+ }
+ for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
+ if (np->name == NULL)
+ continue;
+ // printk("found node %p %s\n", np, np->name);
+ if (strcmp(np->name, "pci") == 0) {
+ of_node_get(np);
+ dev = np;
+ }
+ }
+ of_node_put(root);
+
+ if (!dev)
+ {
+ printk("couldn't find PCI node!\n");
+ return;
+ }
+
+ hose = pcibios_alloc_controller(dev);
+ if (hose == NULL)
+ {
+ printk("pcibios_alloc_controller failed!\n");
+ return;
+ }
+
+ hose->first_busno = 0;
+ hose->last_busno = 1;
+
+ hose->ops = &xenon_pci_ops;
+ hose->cfg_addr = ioremap(0xd0000000, 0x1000000);
+
+ pci_process_bridge_OF_ranges(hose, dev, 1);
+
+// of_rescan_bus(root, ci_bus *bus)
+
+ /* Tell pci.c to not change any resource allocations. */
+ pci_set_flags(PCI_PROBE_ONLY);
+
+ of_node_put(dev);
+ DBG("PCI initialized\n");
+
+ pci_io_base = 0;
+
+ // pcibios_scan_phb(hose, dev);
+ set_pci_dma_ops(&dma_iommu_ops);
+}
+
+#else
+
+
+static int __init xenon_add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ char *disp_name;
+ const int *bus_range;
+ int primary = 1, has_address = 0;