diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210-cache.lib b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210-cache.lib new file mode 100644 index 000000000..4d3bf2d95 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dff +# +DEF dff X 0 40 Y Y 1 F N +F0 "X" -350 -500 60 H V C CNN +F1 "dff" -350 -400 60 H V C CNN +F2 "" -350 -400 60 H I C CNN +F3 "" -350 -400 60 H I C CNN +DRAW +S -200 150 350 -350 0 1 0 N +X D 1 -400 50 200 R 50 50 1 1 I +X CLK 2 -400 -150 200 R 50 50 1 1 I +X CLR 3 50 -550 200 U 50 50 1 1 I +X QBar 4 550 -150 200 L 50 50 1 1 O +X Q 5 550 50 200 L 50 50 1 1 O +X Preset 6 50 350 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir new file mode 100644 index 000000000..ec6ef73e2 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir @@ -0,0 +1,23 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\74AHC1G4210\74AHC1G4210.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 19:33:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_X1-Pad1_ /X2 ? Net-_X1-Pad1_ ? ? dff +X2 Net-_X2-Pad1_ Net-_X1-Pad1_ ? Net-_X2-Pad1_ ? ? dff +X3 Net-_X3-Pad1_ Net-_X2-Pad1_ ? Net-_X3-Pad1_ ? ? dff +X4 Net-_X4-Pad1_ Net-_X3-Pad1_ ? Net-_X4-Pad1_ ? ? dff +X5 Net-_X5-Pad1_ Net-_X4-Pad1_ ? Net-_X5-Pad1_ ? ? dff +X6 Net-_X6-Pad1_ Net-_X5-Pad1_ ? Net-_X6-Pad1_ ? ? dff +X7 Net-_X7-Pad1_ Net-_X6-Pad1_ ? Net-_X7-Pad1_ ? ? dff +X8 Net-_X8-Pad1_ Net-_X7-Pad1_ ? Net-_X8-Pad1_ ? ? dff +X9 Net-_X10-Pad2_ Net-_X8-Pad1_ ? Net-_X10-Pad2_ ? ? dff +X10 Net-_U3-Pad1_ Net-_X10-Pad2_ ? Net-_U3-Pad1_ ? ? dff +U3 Net-_U3-Pad1_ /Q d_inverter +U2 /X1 /X2 d_inverter +U1 /X1 /X2 ? /Q ? PORT + +.end diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir.out b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir.out new file mode 100644 index 000000000..c1609b894 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir.out @@ -0,0 +1,31 @@ +* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4210\74ahc1g4210.cir + +.include dff.sub +x1 net-_x1-pad1_ /x2 ? net-_x1-pad1_ ? ? dff +x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff +x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff +x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff +x5 net-_x5-pad1_ net-_x4-pad1_ ? net-_x5-pad1_ ? ? dff +x6 net-_x6-pad1_ net-_x5-pad1_ ? net-_x6-pad1_ ? ? dff +x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff +x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff +x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff +x10 net-_u3-pad1_ net-_x10-pad2_ ? net-_u3-pad1_ ? ? dff +* u3 net-_u3-pad1_ /q d_inverter +* u2 /x1 /x2 d_inverter +* u1 /x1 /x2 ? /q ? port +a1 net-_u3-pad1_ /q u3 +a2 /x1 /x2 u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.pro b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sch b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sch new file mode 100644 index 000000000..39c882d14 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sch @@ -0,0 +1,439 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74AHC1G4210-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dff X1 +U 1 1 6857B3A7 +P 5100 7300 +F 0 "X1" H 4750 6800 60 0000 C CNN +F 1 "dff" H 4750 6900 60 0000 C CNN +F 2 "" H 4750 6900 60 0001 C CNN +F 3 "" H 4750 6900 60 0001 C CNN + 1 5100 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X2 +U 1 1 6857B452 +P 6500 7300 +F 0 "X2" H 6150 6800 60 0000 C CNN +F 1 "dff" H 6150 6900 60 0000 C CNN +F 2 "" H 6150 6900 60 0001 C CNN +F 3 "" H 6150 6900 60 0001 C CNN + 1 6500 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X3 +U 1 1 6857B4F2 +P 7800 7300 +F 0 "X3" H 7450 6800 60 0000 C CNN +F 1 "dff" H 7450 6900 60 0000 C CNN +F 2 "" H 7450 6900 60 0001 C CNN +F 3 "" H 7450 6900 60 0001 C CNN + 1 7800 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X4 +U 1 1 6857B4F8 +P 9200 7300 +F 0 "X4" H 8850 6800 60 0000 C CNN +F 1 "dff" H 8850 6900 60 0000 C CNN +F 2 "" H 8850 6900 60 0001 C CNN +F 3 "" H 8850 6900 60 0001 C CNN + 1 9200 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X5 +U 1 1 6857BE1A +P 10400 7300 +F 0 "X5" H 10050 6800 60 0000 C CNN +F 1 "dff" H 10050 6900 60 0000 C CNN +F 2 "" H 10050 6900 60 0001 C CNN +F 3 "" H 10050 6900 60 0001 C CNN + 1 10400 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X6 +U 1 1 6857BE20 +P 11800 7300 +F 0 "X6" H 11450 6800 60 0000 C CNN +F 1 "dff" H 11450 6900 60 0000 C CNN +F 2 "" H 11450 6900 60 0001 C CNN +F 3 "" H 11450 6900 60 0001 C CNN + 1 11800 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X7 +U 1 1 6857BE26 +P 13100 7300 +F 0 "X7" H 12750 6800 60 0000 C CNN +F 1 "dff" H 12750 6900 60 0000 C CNN +F 2 "" H 12750 6900 60 0001 C CNN +F 3 "" H 12750 6900 60 0001 C CNN + 1 13100 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X8 +U 1 1 6857BE2C +P 14500 7300 +F 0 "X8" H 14150 6800 60 0000 C CNN +F 1 "dff" H 14150 6900 60 0000 C CNN +F 2 "" H 14150 6900 60 0001 C CNN +F 3 "" H 14150 6900 60 0001 C CNN + 1 14500 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X9 +U 1 1 6857D2EC +P 15700 7300 +F 0 "X9" H 15350 6800 60 0000 C CNN +F 1 "dff" H 15350 6900 60 0000 C CNN +F 2 "" H 15350 6900 60 0001 C CNN +F 3 "" H 15350 6900 60 0001 C CNN + 1 15700 7300 + 1 0 0 -1 +$EndComp +$Comp +L dff X10 +U 1 1 6857D2F2 +P 17100 7300 +F 0 "X10" H 16750 6800 60 0000 C CNN +F 1 "dff" H 16750 6900 60 0000 C CNN +F 2 "" H 16750 6900 60 0001 C CNN +F 3 "" H 16750 6900 60 0001 C CNN + 1 17100 7300 + 1 0 0 -1 +$EndComp +NoConn ~ 5150 6950 +NoConn ~ 5650 7250 +NoConn ~ 5150 7850 +NoConn ~ 6550 6950 +NoConn ~ 6550 7850 +NoConn ~ 7050 7250 +NoConn ~ 7850 6950 +NoConn ~ 7850 7850 +NoConn ~ 8350 7250 +NoConn ~ 9250 6950 +NoConn ~ 9250 7850 +NoConn ~ 9750 7250 +NoConn ~ 10450 7850 +NoConn ~ 10450 6950 +NoConn ~ 10950 7250 +NoConn ~ 11850 7850 +NoConn ~ 11850 6950 +NoConn ~ 12350 7250 +NoConn ~ 13150 6950 +NoConn ~ 13150 7850 +NoConn ~ 13650 7250 +NoConn ~ 14550 7850 +NoConn ~ 14550 6950 +NoConn ~ 15050 7250 +NoConn ~ 15750 7850 +NoConn ~ 15750 6950 +NoConn ~ 16250 7250 +NoConn ~ 17150 7850 +NoConn ~ 17150 6950 +NoConn ~ 17650 7250 +Wire Wire Line + 4700 7250 4500 7250 +Wire Wire Line + 4500 7250 4500 6600 +Wire Wire Line + 4500 6600 5800 6600 +Wire Wire Line + 5800 6600 5800 7450 +Wire Wire Line + 5800 7450 5650 7450 +Wire Wire Line + 5800 7350 6000 7350 +Wire Wire Line + 6000 7350 6000 7450 +Wire Wire Line + 6000 7450 6100 7450 +Connection ~ 5800 7350 +Wire Wire Line + 6100 7250 6100 6600 +Wire Wire Line + 6100 6600 7200 6600 +Wire Wire Line + 7200 6600 7200 7450 +Wire Wire Line + 7200 7450 7050 7450 +Wire Wire Line + 7200 7350 7300 7350 +Wire Wire Line + 7300 7350 7300 7450 +Wire Wire Line + 7300 7450 7400 7450 +Connection ~ 7200 7350 +Wire Wire Line + 7400 7250 7400 6600 +Wire Wire Line + 7400 6600 8500 6600 +Wire Wire Line + 8500 6600 8500 7450 +Wire Wire Line + 8500 7450 8350 7450 +Wire Wire Line + 8500 7350 8650 7350 +Wire Wire Line + 8650 7350 8650 7450 +Wire Wire Line + 8650 7450 8800 7450 +Connection ~ 8500 7350 +Wire Wire Line + 8800 7250 8800 6600 +Wire Wire Line + 8800 6600 9900 6600 +Wire Wire Line + 9900 6600 9900 7450 +Wire Wire Line + 9900 7450 9750 7450 +Wire Wire Line + 9900 7350 9950 7350 +Wire Wire Line + 9950 7350 9950 7450 +Wire Wire Line + 9950 7450 10000 7450 +Connection ~ 9900 7350 +Wire Wire Line + 10000 7250 10000 6600 +Wire Wire Line + 10000 6600 11050 6600 +Wire Wire Line + 11050 6600 11050 7450 +Wire Wire Line + 11050 7450 10950 7450 +Wire Wire Line + 11050 7350 11200 7350 +Wire Wire Line + 11200 7350 11200 7450 +Wire Wire Line + 11200 7450 11400 7450 +Connection ~ 11050 7350 +Wire Wire Line + 11400 7250 11400 6600 +Wire Wire Line + 11400 6600 12500 6600 +Wire Wire Line + 12500 6600 12500 7450 +Wire Wire Line + 12500 7450 12350 7450 +Wire Wire Line + 12500 7350 12600 7350 +Wire Wire Line + 12600 7350 12600 7450 +Wire Wire Line + 12600 7450 12700 7450 +Connection ~ 12500 7350 +Wire Wire Line + 12700 7250 12700 6600 +Wire Wire Line + 12700 6600 13800 6600 +Wire Wire Line + 13800 6600 13800 7450 +Wire Wire Line + 13800 7450 13650 7450 +Wire Wire Line + 13800 7300 13900 7300 +Wire Wire Line + 13900 7300 13900 7450 +Wire Wire Line + 13900 7450 14100 7450 +Connection ~ 13800 7300 +Wire Wire Line + 14100 7250 14100 6600 +Wire Wire Line + 14100 6600 15150 6600 +Wire Wire Line + 15150 6600 15150 7450 +Wire Wire Line + 15150 7450 15050 7450 +Wire Wire Line + 15150 7350 15200 7350 +Wire Wire Line + 15200 7350 15200 7450 +Wire Wire Line + 15200 7450 15300 7450 +Connection ~ 15150 7350 +Wire Wire Line + 15300 7250 15300 6600 +Wire Wire Line + 15300 6600 16400 6600 +Wire Wire Line + 16400 6600 16400 7450 +Wire Wire Line + 16400 7450 16250 7450 +Wire Wire Line + 16400 7350 16500 7350 +Wire Wire Line + 16500 7350 16500 7450 +Wire Wire Line + 16500 7450 16700 7450 +Connection ~ 16400 7350 +Wire Wire Line + 16700 7250 16700 6600 +Wire Wire Line + 16700 6600 17800 6600 +Wire Wire Line + 17800 6600 17800 7450 +Wire Wire Line + 17650 7450 17900 7450 +Connection ~ 17800 7450 +$Comp +L d_inverter U3 +U 1 1 68580C81 +P 18200 7450 +F 0 "U3" H 18200 7350 60 0000 C CNN +F 1 "d_inverter" H 18200 7600 60 0000 C CNN +F 2 "" H 18250 7400 60 0000 C CNN +F 3 "" H 18250 7400 60 0000 C CNN + 1 18200 7450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18500 7450 18700 7450 +$Comp +L d_inverter U2 +U 1 1 68585125 +P 3900 7450 +F 0 "U2" H 3900 7350 60 0000 C CNN +F 1 "d_inverter" H 3900 7600 60 0000 C CNN +F 2 "" H 3950 7400 60 0000 C CNN +F 3 "" H 3950 7400 60 0000 C CNN + 1 3900 7450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 7450 4700 7450 +Wire Wire Line + 3600 7450 2950 7450 +Wire Wire Line + 4350 7450 4350 6600 +Wire Wire Line + 4350 6600 3000 6600 +Connection ~ 4350 7450 +Text Label 3000 6600 0 60 ~ 0 +X2 +Text Label 2950 7450 0 60 ~ 0 +X1 +Text Label 18700 7450 0 60 ~ 0 +Q +$Comp +L PORT U1 +U 1 1 68585EDA +P 2700 7450 +F 0 "U1" H 2750 7550 30 0000 C CNN +F 1 "PORT" H 2700 7450 30 0000 C CNN +F 2 "" H 2700 7450 60 0000 C CNN +F 3 "" H 2700 7450 60 0000 C CNN + 1 2700 7450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68585F37 +P 3550 8200 +F 0 "U1" H 3600 8300 30 0000 C CNN +F 1 "PORT" H 3550 8200 30 0000 C CNN +F 2 "" H 3550 8200 60 0000 C CNN +F 3 "" H 3550 8200 60 0000 C CNN + 3 3550 8200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68585F7E +P 4050 8200 +F 0 "U1" H 4100 8300 30 0000 C CNN +F 1 "PORT" H 4050 8200 30 0000 C CNN +F 2 "" H 4050 8200 60 0000 C CNN +F 3 "" H 4050 8200 60 0000 C CNN + 5 4050 8200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68585FB7 +P 2750 6600 +F 0 "U1" H 2800 6700 30 0000 C CNN +F 1 "PORT" H 2750 6600 30 0000 C CNN +F 2 "" H 2750 6600 60 0000 C CNN +F 3 "" H 2750 6600 60 0000 C CNN + 2 2750 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68585FEC +P 18950 7450 +F 0 "U1" H 19000 7550 30 0000 C CNN +F 1 "PORT" H 18950 7450 30 0000 C CNN +F 2 "" H 18950 7450 60 0000 C CNN +F 3 "" H 18950 7450 60 0000 C CNN + 4 18950 7450 + -1 0 0 1 +$EndComp +NoConn ~ 3800 8200 +NoConn ~ 4300 8200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sub b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sub new file mode 100644 index 000000000..27720ad38 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sub @@ -0,0 +1,25 @@ +* Subcircuit 74AHC1G4210 +.subckt 74AHC1G4210 /x1 /x2 ? /q ? +* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4210\74ahc1g4210.cir +.include dff.sub +x1 net-_x1-pad1_ /x2 ? net-_x1-pad1_ ? ? dff +x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff +x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff +x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff +x5 net-_x5-pad1_ net-_x4-pad1_ ? net-_x5-pad1_ ? ? dff +x6 net-_x6-pad1_ net-_x5-pad1_ ? net-_x6-pad1_ ? ? dff +x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff +x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff +x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff +x10 net-_u3-pad1_ net-_x10-pad2_ ? net-_u3-pad1_ ? ? dff +* u3 net-_u3-pad1_ /q d_inverter +* u2 /x1 /x2 d_inverter +a1 net-_u3-pad1_ /q u3 +a2 /x1 /x2 u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74AHC1G4210 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210_Previous_Values.xml new file mode 100644 index 000000000..3aa4f1058 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dfftruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4210/analysis b/library/SubcircuitLibrary/74AHC1G4210/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff-cache.lib b/library/SubcircuitLibrary/74AHC1G4210/dff-cache.lib new file mode 100644 index 000000000..440552005 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/dff-cache.lib @@ -0,0 +1,92 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.cir b/library/SubcircuitLibrary/74AHC1G4210/dff.cir new file mode 100644 index 000000000..883325a5e --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/dff.cir @@ -0,0 +1,18 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\dff\dff.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 11:41:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U2-Pad6_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_and +U6 Net-_U4-Pad3_ Net-_U2-Pad3_ Net-_U6-Pad3_ d_and +U7 Net-_U2-Pad4_ Net-_U5-Pad3_ Net-_U2-Pad5_ d_nand +U8 Net-_U2-Pad5_ Net-_U6-Pad3_ Net-_U2-Pad4_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.cir.out b/library/SubcircuitLibrary/74AHC1G4210/dff.cir.out new file mode 100644 index 000000000..849212938 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/dff.cir.out @@ -0,0 +1,40 @@ +* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir + +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and +* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand +* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7 +a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8 +a7 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.pro b/library/SubcircuitLibrary/74AHC1G4210/dff.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/dff.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.sch b/library/SubcircuitLibrary/74AHC1G4210/dff.sch new file mode 100644 index 000000000..675737646 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/dff.sch @@ -0,0 +1,273 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 6851060F +P 3700 2300 +F 0 "U3" H 3700 2300 60 0000 C CNN +F 1 "d_nand" H 3750 2400 60 0000 C CNN +F 2 "" H 3700 2300 60 0000 C CNN +F 3 "" H 3700 2300 60 0000 C CNN + 1 3700 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68510656 +P 3700 3300 +F 0 "U4" H 3700 3300 60 0000 C CNN +F 1 "d_nand" H 3750 3400 60 0000 C CNN +F 2 "" H 3700 3300 60 0000 C CNN +F 3 "" H 3700 3300 60 0000 C CNN + 1 3700 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68510666 +P 5400 2300 +F 0 "U5" H 5400 2300 60 0000 C CNN +F 1 "d_and" H 5450 2400 60 0000 C CNN +F 2 "" H 5400 2300 60 0000 C CNN +F 3 "" H 5400 2300 60 0000 C CNN + 1 5400 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 685106C5 +P 5400 3300 +F 0 "U6" H 5400 3300 60 0000 C CNN +F 1 "d_and" H 5450 3400 60 0000 C CNN +F 2 "" H 5400 3300 60 0000 C CNN +F 3 "" H 5400 3300 60 0000 C CNN + 1 5400 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 685106D1 +P 7100 2300 +F 0 "U7" H 7100 2300 60 0000 C CNN +F 1 "d_nand" H 7150 2400 60 0000 C CNN +F 2 "" H 7100 2300 60 0000 C CNN +F 3 "" H 7100 2300 60 0000 C CNN + 1 7100 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 68510816 +P 7150 3300 +F 0 "U8" H 7150 3300 60 0000 C CNN +F 1 "d_nand" H 7200 3400 60 0000 C CNN +F 2 "" H 7150 3300 60 0000 C CNN +F 3 "" H 7150 3300 60 0000 C CNN + 1 7150 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 3250 6150 3250 +Wire Wire Line + 6150 3250 6150 3300 +Wire Wire Line + 6150 3300 6700 3300 +Wire Wire Line + 5850 2250 6050 2250 +Wire Wire Line + 6050 2250 6050 2300 +Wire Wire Line + 6050 2300 6650 2300 +Wire Wire Line + 7550 2250 8000 2250 +Wire Wire Line + 7600 3250 8150 3250 +Wire Wire Line + 4950 2200 4750 2200 +Wire Wire Line + 4750 2200 4750 1750 +Wire Wire Line + 4950 3300 4750 3300 +Wire Wire Line + 4750 3300 4750 3800 +Wire Wire Line + 4150 3250 4500 3250 +Wire Wire Line + 4500 3250 4500 3200 +Wire Wire Line + 4500 3200 4950 3200 +Wire Wire Line + 4150 2250 4400 2250 +Wire Wire Line + 4400 2250 4400 2300 +Wire Wire Line + 4400 2300 4950 2300 +Wire Wire Line + 7850 2250 7850 2600 +Wire Wire Line + 7850 2600 6450 2600 +Wire Wire Line + 6450 2600 6450 3200 +Wire Wire Line + 6450 3200 6700 3200 +Connection ~ 7850 2250 +Wire Wire Line + 7750 3250 7750 2750 +Wire Wire Line + 7750 2750 6250 2750 +Wire Wire Line + 6250 2750 6250 2200 +Wire Wire Line + 6250 2200 6650 2200 +Connection ~ 7750 3250 +Wire Wire Line + 3250 2200 2100 2200 +Wire Wire Line + 3250 2300 3000 2300 +Wire Wire Line + 3000 2300 3000 3200 +Wire Wire Line + 3000 3200 3250 3200 +Wire Wire Line + 2300 2200 2300 3300 +Connection ~ 2300 2200 +$Comp +L d_inverter U1 +U 1 1 68510965 +P 2700 3300 +F 0 "U1" H 2700 3200 60 0000 C CNN +F 1 "d_inverter" H 2700 3450 60 0000 C CNN +F 2 "" H 2750 3250 60 0000 C CNN +F 3 "" H 2750 3250 60 0000 C CNN + 1 2700 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 3300 3250 3300 +Wire Wire Line + 2300 3300 2400 3300 +Wire Wire Line + 3000 2750 1950 2750 +Wire Wire Line + 1950 2750 1950 3750 +Connection ~ 3000 2750 +$Comp +L PORT U2 +U 1 1 68510A2C +P 1850 2200 +F 0 "U2" H 1900 2300 30 0000 C CNN +F 1 "PORT" H 1850 2200 30 0000 C CNN +F 2 "" H 1850 2200 60 0000 C CNN +F 3 "" H 1850 2200 60 0000 C CNN + 1 1850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 2 1 68510A87 +P 1700 3750 +F 0 "U2" H 1750 3850 30 0000 C CNN +F 1 "PORT" H 1700 3750 30 0000 C CNN +F 2 "" H 1700 3750 60 0000 C CNN +F 3 "" H 1700 3750 60 0000 C CNN + 2 1700 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 3 1 68510ACA +P 4500 3800 +F 0 "U2" H 4550 3900 30 0000 C CNN +F 1 "PORT" H 4500 3800 30 0000 C CNN +F 2 "" H 4500 3800 60 0000 C CNN +F 3 "" H 4500 3800 60 0000 C CNN + 3 4500 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 5 1 68510AFD +P 8000 2500 +F 0 "U2" H 8050 2600 30 0000 C CNN +F 1 "PORT" H 8000 2500 30 0000 C CNN +F 2 "" H 8000 2500 60 0000 C CNN +F 3 "" H 8000 2500 60 0000 C CNN + 5 8000 2500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 4 1 68510B2C +P 8150 3500 +F 0 "U2" H 8200 3600 30 0000 C CNN +F 1 "PORT" H 8150 3500 30 0000 C CNN +F 2 "" H 8150 3500 60 0000 C CNN +F 3 "" H 8150 3500 60 0000 C CNN + 4 8150 3500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 6 1 68510B5D +P 4500 1750 +F 0 "U2" H 4550 1850 30 0000 C CNN +F 1 "PORT" H 4500 1750 30 0000 C CNN +F 2 "" H 4500 1750 60 0000 C CNN +F 3 "" H 4500 1750 60 0000 C CNN + 6 4500 1750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.sub b/library/SubcircuitLibrary/74AHC1G4210/dff.sub new file mode 100644 index 000000000..885e878fc --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/dff.sub @@ -0,0 +1,34 @@ +* Subcircuit dff +.subckt dff net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ +* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and +* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand +* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7 +a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8 +a7 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends dff \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4210/dff_Previous_Values.xml new file mode 100644 index 000000000..2a57486b8 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4210/dff_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_andd_andd_nandd_nandd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212-cache.lib b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212-cache.lib new file mode 100644 index 000000000..4d3bf2d95 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dff +# +DEF dff X 0 40 Y Y 1 F N +F0 "X" -350 -500 60 H V C CNN +F1 "dff" -350 -400 60 H V C CNN +F2 "" -350 -400 60 H I C CNN +F3 "" -350 -400 60 H I C CNN +DRAW +S -200 150 350 -350 0 1 0 N +X D 1 -400 50 200 R 50 50 1 1 I +X CLK 2 -400 -150 200 R 50 50 1 1 I +X CLR 3 50 -550 200 U 50 50 1 1 I +X QBar 4 550 -150 200 L 50 50 1 1 O +X Q 5 550 50 200 L 50 50 1 1 O +X Preset 6 50 350 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir new file mode 100644 index 000000000..3fe1795a7 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir @@ -0,0 +1,25 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\74AHC1G4212\74AHC1G4212.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 19:44:41 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_X1-Pad1_ Net-_U1-Pad2_ ? Net-_X1-Pad1_ ? ? dff +X2 Net-_X2-Pad1_ Net-_X1-Pad1_ ? Net-_X2-Pad1_ ? ? dff +X3 Net-_X3-Pad1_ Net-_X2-Pad1_ ? Net-_X3-Pad1_ ? ? dff +X4 Net-_X4-Pad1_ Net-_X3-Pad1_ ? Net-_X4-Pad1_ ? ? dff +X5 ? Net-_X4-Pad1_ ? Net-_X5-Pad4_ ? Net-_X5-Pad4_ dff +X6 Net-_X6-Pad1_ Net-_X5-Pad4_ ? Net-_X6-Pad1_ ? ? dff +X7 Net-_X7-Pad1_ Net-_X6-Pad1_ ? Net-_X7-Pad1_ ? ? dff +X8 Net-_X8-Pad1_ Net-_X7-Pad1_ ? Net-_X8-Pad1_ ? ? dff +X9 Net-_X10-Pad2_ Net-_X8-Pad1_ ? Net-_X10-Pad2_ ? ? dff +X10 Net-_X10-Pad1_ Net-_X10-Pad2_ ? Net-_X10-Pad1_ ? ? dff +X11 Net-_X11-Pad1_ Net-_X10-Pad1_ ? Net-_X11-Pad1_ ? ? dff +X12 Net-_U3-Pad1_ Net-_X11-Pad1_ ? Net-_U3-Pad1_ ? ? dff +U3 Net-_U3-Pad1_ Net-_U1-Pad4_ d_inverter +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ ? Net-_U1-Pad4_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir.out b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir.out new file mode 100644 index 000000000..0ab970978 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir.out @@ -0,0 +1,33 @@ +* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4212\74ahc1g4212.cir + +.include dff.sub +x1 net-_x1-pad1_ net-_u1-pad2_ ? net-_x1-pad1_ ? ? dff +x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff +x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff +x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff +x5 ? net-_x4-pad1_ ? net-_x5-pad4_ ? net-_x5-pad4_ dff +x6 net-_x6-pad1_ net-_x5-pad4_ ? net-_x6-pad1_ ? ? dff +x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff +x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff +x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff +x10 net-_x10-pad1_ net-_x10-pad2_ ? net-_x10-pad1_ ? ? dff +x11 net-_x11-pad1_ net-_x10-pad1_ ? net-_x11-pad1_ ? ? dff +x12 net-_u3-pad1_ net-_x11-pad1_ ? net-_u3-pad1_ ? ? dff +* u3 net-_u3-pad1_ net-_u1-pad4_ d_inverter +* u2 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ ? net-_u1-pad4_ ? port +a1 net-_u3-pad1_ net-_u1-pad4_ u3 +a2 net-_u1-pad1_ net-_u1-pad2_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.pro b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sch b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sch new file mode 100644 index 000000000..4b0870536 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sch @@ -0,0 +1,497 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74AHC1G4212-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dff X1 +U 1 1 68693108 +P 7100 8700 +F 0 "X1" H 6750 8200 60 0000 C CNN +F 1 "dff" H 6750 8300 60 0000 C CNN +F 2 "" H 6750 8300 60 0001 C CNN +F 3 "" H 6750 8300 60 0001 C CNN + 1 7100 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X2 +U 1 1 686931A9 +P 8850 8700 +F 0 "X2" H 8500 8200 60 0000 C CNN +F 1 "dff" H 8500 8300 60 0000 C CNN +F 2 "" H 8500 8300 60 0001 C CNN +F 3 "" H 8500 8300 60 0001 C CNN + 1 8850 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X3 +U 1 1 68693239 +P 10600 8700 +F 0 "X3" H 10250 8200 60 0000 C CNN +F 1 "dff" H 10250 8300 60 0000 C CNN +F 2 "" H 10250 8300 60 0001 C CNN +F 3 "" H 10250 8300 60 0001 C CNN + 1 10600 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X4 +U 1 1 6869323F +P 12350 8700 +F 0 "X4" H 12000 8200 60 0000 C CNN +F 1 "dff" H 12000 8300 60 0000 C CNN +F 2 "" H 12000 8300 60 0001 C CNN +F 3 "" H 12000 8300 60 0001 C CNN + 1 12350 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X5 +U 1 1 686936B9 +P 14000 8700 +F 0 "X5" H 13650 8200 60 0000 C CNN +F 1 "dff" H 13650 8300 60 0000 C CNN +F 2 "" H 13650 8300 60 0001 C CNN +F 3 "" H 13650 8300 60 0001 C CNN + 1 14000 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X6 +U 1 1 686936BF +P 15750 8700 +F 0 "X6" H 15400 8200 60 0000 C CNN +F 1 "dff" H 15400 8300 60 0000 C CNN +F 2 "" H 15400 8300 60 0001 C CNN +F 3 "" H 15400 8300 60 0001 C CNN + 1 15750 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X7 +U 1 1 686936C5 +P 17500 8700 +F 0 "X7" H 17150 8200 60 0000 C CNN +F 1 "dff" H 17150 8300 60 0000 C CNN +F 2 "" H 17150 8300 60 0001 C CNN +F 3 "" H 17150 8300 60 0001 C CNN + 1 17500 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X8 +U 1 1 686936CB +P 19250 8700 +F 0 "X8" H 18900 8200 60 0000 C CNN +F 1 "dff" H 18900 8300 60 0000 C CNN +F 2 "" H 18900 8300 60 0001 C CNN +F 3 "" H 18900 8300 60 0001 C CNN + 1 19250 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X9 +U 1 1 68693C01 +P 20850 8700 +F 0 "X9" H 20500 8200 60 0000 C CNN +F 1 "dff" H 20500 8300 60 0000 C CNN +F 2 "" H 20500 8300 60 0001 C CNN +F 3 "" H 20500 8300 60 0001 C CNN + 1 20850 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X10 +U 1 1 68693C07 +P 22600 8700 +F 0 "X10" H 22250 8200 60 0000 C CNN +F 1 "dff" H 22250 8300 60 0000 C CNN +F 2 "" H 22250 8300 60 0001 C CNN +F 3 "" H 22250 8300 60 0001 C CNN + 1 22600 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X11 +U 1 1 68693C0D +P 24350 8700 +F 0 "X11" H 24000 8200 60 0000 C CNN +F 1 "dff" H 24000 8300 60 0000 C CNN +F 2 "" H 24000 8300 60 0001 C CNN +F 3 "" H 24000 8300 60 0001 C CNN + 1 24350 8700 + 1 0 0 -1 +$EndComp +$Comp +L dff X12 +U 1 1 68693C13 +P 26100 8700 +F 0 "X12" H 25750 8200 60 0000 C CNN +F 1 "dff" H 25750 8300 60 0000 C CNN +F 2 "" H 25750 8300 60 0001 C CNN +F 3 "" H 25750 8300 60 0001 C CNN + 1 26100 8700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 8650 6650 8650 +Wire Wire Line + 6650 8650 6650 8100 +Wire Wire Line + 6650 8100 7950 8100 +Wire Wire Line + 7950 8100 7950 8850 +Wire Wire Line + 7950 8850 7650 8850 +Wire Wire Line + 7950 8750 8150 8750 +Wire Wire Line + 8150 8750 8150 8850 +Wire Wire Line + 8150 8850 8450 8850 +Connection ~ 7950 8750 +Wire Wire Line + 8450 8650 8450 8100 +Wire Wire Line + 8450 8100 9700 8100 +Wire Wire Line + 9700 8100 9700 8850 +Wire Wire Line + 9700 8850 9400 8850 +Wire Wire Line + 9700 8750 10000 8750 +Wire Wire Line + 10000 8750 10000 8850 +Wire Wire Line + 10000 8850 10200 8850 +Connection ~ 9700 8750 +Wire Wire Line + 10200 8650 10200 8100 +Wire Wire Line + 10200 8100 11550 8100 +Wire Wire Line + 11550 8100 11550 8850 +Wire Wire Line + 11550 8850 11150 8850 +Wire Wire Line + 11550 8750 11700 8750 +Wire Wire Line + 11700 8750 11700 8850 +Wire Wire Line + 11700 8850 11950 8850 +Connection ~ 11550 8750 +Wire Wire Line + 11950 8650 11950 8100 +Wire Wire Line + 11950 8100 13250 8100 +Wire Wire Line + 13250 8100 13250 8850 +Wire Wire Line + 13250 8850 12900 8850 +Wire Wire Line + 13250 8750 13400 8750 +Wire Wire Line + 13400 8750 13400 8850 +Wire Wire Line + 13400 8850 13600 8850 +Connection ~ 13250 8750 +Wire Wire Line + 14050 8350 14050 8150 +Wire Wire Line + 14050 8150 14800 8150 +Wire Wire Line + 14800 8150 14800 8850 +Wire Wire Line + 14800 8850 14550 8850 +Wire Wire Line + 14800 8750 15050 8750 +Wire Wire Line + 15050 8750 15050 8850 +Wire Wire Line + 15050 8850 15350 8850 +Connection ~ 14800 8750 +Wire Wire Line + 15350 8650 15250 8650 +Wire Wire Line + 15250 8650 15250 8150 +Wire Wire Line + 15250 8150 16600 8150 +Wire Wire Line + 16600 8150 16600 8850 +Wire Wire Line + 16600 8850 16300 8850 +Wire Wire Line + 16600 8750 16800 8750 +Wire Wire Line + 16800 8750 16800 8850 +Wire Wire Line + 16800 8850 17100 8850 +Connection ~ 16600 8750 +Wire Wire Line + 17100 8650 16950 8650 +Wire Wire Line + 16950 8650 16950 8200 +Wire Wire Line + 16950 8200 18350 8200 +Wire Wire Line + 18350 8200 18350 8850 +Wire Wire Line + 18350 8850 18050 8850 +Wire Wire Line + 18350 8750 18550 8750 +Wire Wire Line + 18550 8750 18550 8850 +Wire Wire Line + 18550 8850 18850 8850 +Connection ~ 18350 8750 +Wire Wire Line + 18850 8650 18750 8650 +Wire Wire Line + 18750 8650 18750 8200 +Wire Wire Line + 18750 8200 20000 8200 +Wire Wire Line + 20000 8200 20000 8850 +Wire Wire Line + 20000 8850 19800 8850 +Wire Wire Line + 20000 8750 20150 8750 +Wire Wire Line + 20150 8750 20150 8850 +Wire Wire Line + 20150 8850 20450 8850 +Connection ~ 20000 8750 +Wire Wire Line + 20450 8650 20300 8650 +Wire Wire Line + 20300 8650 20300 8200 +Wire Wire Line + 20300 8200 21650 8200 +Wire Wire Line + 21650 8200 21650 8850 +Wire Wire Line + 21650 8850 21400 8850 +Wire Wire Line + 22200 8650 22000 8650 +Wire Wire Line + 22000 8650 22000 8100 +Wire Wire Line + 22000 8100 23350 8100 +Wire Wire Line + 23350 8100 23350 8850 +Wire Wire Line + 23350 8850 23150 8850 +Wire Wire Line + 21650 8800 21950 8800 +Wire Wire Line + 21950 8800 21950 8850 +Wire Wire Line + 21950 8850 22200 8850 +Connection ~ 21650 8800 +Wire Wire Line + 23350 8750 23600 8750 +Wire Wire Line + 23600 8750 23600 8850 +Wire Wire Line + 23600 8850 23950 8850 +Connection ~ 23350 8750 +Wire Wire Line + 23950 8650 23750 8650 +Wire Wire Line + 23750 8650 23750 8100 +Wire Wire Line + 23750 8100 25300 8100 +Wire Wire Line + 25300 8100 25300 8850 +Wire Wire Line + 25300 8850 24900 8850 +Wire Wire Line + 25300 8750 25450 8750 +Wire Wire Line + 25450 8750 25450 8850 +Wire Wire Line + 25450 8850 25700 8850 +Connection ~ 25300 8750 +Wire Wire Line + 25700 8650 25700 8100 +Wire Wire Line + 25700 8100 27050 8100 +Wire Wire Line + 27050 8100 27050 8850 +Wire Wire Line + 26650 8850 27400 8850 +$Comp +L d_inverter U3 +U 1 1 686957E9 +P 27700 8850 +F 0 "U3" H 27700 8750 60 0000 C CNN +F 1 "d_inverter" H 27700 9000 60 0000 C CNN +F 2 "" H 27750 8800 60 0000 C CNN +F 3 "" H 27750 8800 60 0000 C CNN + 1 27700 8850 + 1 0 0 -1 +$EndComp +Connection ~ 27050 8850 +Wire Wire Line + 28000 8850 28450 8850 +$Comp +L d_inverter U2 +U 1 1 6869621C +P 5850 8850 +F 0 "U2" H 5850 8750 60 0000 C CNN +F 1 "d_inverter" H 5850 9000 60 0000 C CNN +F 2 "" H 5900 8800 60 0000 C CNN +F 3 "" H 5900 8800 60 0000 C CNN + 1 5850 8850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 8850 6700 8850 +Wire Wire Line + 5550 8850 5050 8850 +Wire Wire Line + 5000 8250 6350 8250 +Wire Wire Line + 6350 8250 6350 8850 +Connection ~ 6350 8850 +NoConn ~ 7150 9250 +NoConn ~ 7150 8350 +NoConn ~ 7650 8650 +NoConn ~ 8900 8350 +NoConn ~ 8900 9250 +NoConn ~ 9400 8650 +NoConn ~ 10650 8350 +NoConn ~ 10650 9250 +NoConn ~ 11150 8650 +NoConn ~ 12400 8350 +NoConn ~ 12400 9250 +NoConn ~ 14050 9250 +NoConn ~ 15800 8350 +NoConn ~ 15800 9250 +NoConn ~ 16300 8650 +NoConn ~ 17550 9250 +NoConn ~ 17550 8350 +NoConn ~ 18050 8650 +NoConn ~ 19300 9250 +NoConn ~ 19300 8350 +NoConn ~ 19800 8650 +NoConn ~ 20900 9250 +NoConn ~ 20900 8350 +NoConn ~ 21400 8650 +NoConn ~ 24400 9250 +NoConn ~ 24400 8350 +NoConn ~ 24900 8650 +NoConn ~ 26150 9250 +NoConn ~ 26150 8350 +NoConn ~ 26650 8650 +$Comp +L PORT U1 +U 1 1 68699175 +P 4800 8850 +F 0 "U1" H 4850 8950 30 0000 C CNN +F 1 "PORT" H 4800 8850 30 0000 C CNN +F 2 "" H 4800 8850 60 0000 C CNN +F 3 "" H 4800 8850 60 0000 C CNN + 1 4800 8850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 686991EA +P 4750 8250 +F 0 "U1" H 4800 8350 30 0000 C CNN +F 1 "PORT" H 4750 8250 30 0000 C CNN +F 2 "" H 4750 8250 60 0000 C CNN +F 3 "" H 4750 8250 60 0000 C CNN + 2 4750 8250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68699237 +P 6450 9700 +F 0 "U1" H 6500 9800 30 0000 C CNN +F 1 "PORT" H 6450 9700 30 0000 C CNN +F 2 "" H 6450 9700 60 0000 C CNN +F 3 "" H 6450 9700 60 0000 C CNN + 3 6450 9700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6869927E +P 28700 8850 +F 0 "U1" H 28750 8950 30 0000 C CNN +F 1 "PORT" H 28700 8850 30 0000 C CNN +F 2 "" H 28700 8850 60 0000 C CNN +F 3 "" H 28700 8850 60 0000 C CNN + 4 28700 8850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 686992CD +P 7000 9850 +F 0 "U1" H 7050 9950 30 0000 C CNN +F 1 "PORT" H 7000 9850 30 0000 C CNN +F 2 "" H 7000 9850 60 0000 C CNN +F 3 "" H 7000 9850 60 0000 C CNN + 5 7000 9850 + 1 0 0 -1 +$EndComp +NoConn ~ 6700 9700 +NoConn ~ 7250 9850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sub b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sub new file mode 100644 index 000000000..1f6ad5429 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sub @@ -0,0 +1,27 @@ +* Subcircuit 74AHC1G4212 +.subckt 74AHC1G4212 net-_u1-pad1_ net-_u1-pad2_ ? net-_u1-pad4_ ? +* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4212\74ahc1g4212.cir +.include dff.sub +x1 net-_x1-pad1_ net-_u1-pad2_ ? net-_x1-pad1_ ? ? dff +x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff +x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff +x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff +x5 ? net-_x4-pad1_ ? net-_x5-pad4_ ? net-_x5-pad4_ dff +x6 net-_x6-pad1_ net-_x5-pad4_ ? net-_x6-pad1_ ? ? dff +x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff +x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff +x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff +x10 net-_x10-pad1_ net-_x10-pad2_ ? net-_x10-pad1_ ? ? dff +x11 net-_x11-pad1_ net-_x10-pad1_ ? net-_x11-pad1_ ? ? dff +x12 net-_u3-pad1_ net-_x11-pad1_ ? net-_u3-pad1_ ? ? dff +* u3 net-_u3-pad1_ net-_u1-pad4_ d_inverter +* u2 net-_u1-pad1_ net-_u1-pad2_ d_inverter +a1 net-_u3-pad1_ net-_u1-pad4_ u3 +a2 net-_u1-pad1_ net-_u1-pad2_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74AHC1G4212 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212_Previous_Values.xml new file mode 100644 index 000000000..70969fd15 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dff \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4212/analysis b/library/SubcircuitLibrary/74AHC1G4212/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff-cache.lib b/library/SubcircuitLibrary/74AHC1G4212/dff-cache.lib new file mode 100644 index 000000000..440552005 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/dff-cache.lib @@ -0,0 +1,92 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.cir b/library/SubcircuitLibrary/74AHC1G4212/dff.cir new file mode 100644 index 000000000..883325a5e --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/dff.cir @@ -0,0 +1,18 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\dff\dff.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 11:41:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U2-Pad6_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_and +U6 Net-_U4-Pad3_ Net-_U2-Pad3_ Net-_U6-Pad3_ d_and +U7 Net-_U2-Pad4_ Net-_U5-Pad3_ Net-_U2-Pad5_ d_nand +U8 Net-_U2-Pad5_ Net-_U6-Pad3_ Net-_U2-Pad4_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.cir.out b/library/SubcircuitLibrary/74AHC1G4212/dff.cir.out new file mode 100644 index 000000000..849212938 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/dff.cir.out @@ -0,0 +1,40 @@ +* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir + +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and +* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand +* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7 +a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8 +a7 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.pro b/library/SubcircuitLibrary/74AHC1G4212/dff.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/dff.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.sch b/library/SubcircuitLibrary/74AHC1G4212/dff.sch new file mode 100644 index 000000000..675737646 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/dff.sch @@ -0,0 +1,273 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 6851060F +P 3700 2300 +F 0 "U3" H 3700 2300 60 0000 C CNN +F 1 "d_nand" H 3750 2400 60 0000 C CNN +F 2 "" H 3700 2300 60 0000 C CNN +F 3 "" H 3700 2300 60 0000 C CNN + 1 3700 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68510656 +P 3700 3300 +F 0 "U4" H 3700 3300 60 0000 C CNN +F 1 "d_nand" H 3750 3400 60 0000 C CNN +F 2 "" H 3700 3300 60 0000 C CNN +F 3 "" H 3700 3300 60 0000 C CNN + 1 3700 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68510666 +P 5400 2300 +F 0 "U5" H 5400 2300 60 0000 C CNN +F 1 "d_and" H 5450 2400 60 0000 C CNN +F 2 "" H 5400 2300 60 0000 C CNN +F 3 "" H 5400 2300 60 0000 C CNN + 1 5400 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 685106C5 +P 5400 3300 +F 0 "U6" H 5400 3300 60 0000 C CNN +F 1 "d_and" H 5450 3400 60 0000 C CNN +F 2 "" H 5400 3300 60 0000 C CNN +F 3 "" H 5400 3300 60 0000 C CNN + 1 5400 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 685106D1 +P 7100 2300 +F 0 "U7" H 7100 2300 60 0000 C CNN +F 1 "d_nand" H 7150 2400 60 0000 C CNN +F 2 "" H 7100 2300 60 0000 C CNN +F 3 "" H 7100 2300 60 0000 C CNN + 1 7100 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 68510816 +P 7150 3300 +F 0 "U8" H 7150 3300 60 0000 C CNN +F 1 "d_nand" H 7200 3400 60 0000 C CNN +F 2 "" H 7150 3300 60 0000 C CNN +F 3 "" H 7150 3300 60 0000 C CNN + 1 7150 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 3250 6150 3250 +Wire Wire Line + 6150 3250 6150 3300 +Wire Wire Line + 6150 3300 6700 3300 +Wire Wire Line + 5850 2250 6050 2250 +Wire Wire Line + 6050 2250 6050 2300 +Wire Wire Line + 6050 2300 6650 2300 +Wire Wire Line + 7550 2250 8000 2250 +Wire Wire Line + 7600 3250 8150 3250 +Wire Wire Line + 4950 2200 4750 2200 +Wire Wire Line + 4750 2200 4750 1750 +Wire Wire Line + 4950 3300 4750 3300 +Wire Wire Line + 4750 3300 4750 3800 +Wire Wire Line + 4150 3250 4500 3250 +Wire Wire Line + 4500 3250 4500 3200 +Wire Wire Line + 4500 3200 4950 3200 +Wire Wire Line + 4150 2250 4400 2250 +Wire Wire Line + 4400 2250 4400 2300 +Wire Wire Line + 4400 2300 4950 2300 +Wire Wire Line + 7850 2250 7850 2600 +Wire Wire Line + 7850 2600 6450 2600 +Wire Wire Line + 6450 2600 6450 3200 +Wire Wire Line + 6450 3200 6700 3200 +Connection ~ 7850 2250 +Wire Wire Line + 7750 3250 7750 2750 +Wire Wire Line + 7750 2750 6250 2750 +Wire Wire Line + 6250 2750 6250 2200 +Wire Wire Line + 6250 2200 6650 2200 +Connection ~ 7750 3250 +Wire Wire Line + 3250 2200 2100 2200 +Wire Wire Line + 3250 2300 3000 2300 +Wire Wire Line + 3000 2300 3000 3200 +Wire Wire Line + 3000 3200 3250 3200 +Wire Wire Line + 2300 2200 2300 3300 +Connection ~ 2300 2200 +$Comp +L d_inverter U1 +U 1 1 68510965 +P 2700 3300 +F 0 "U1" H 2700 3200 60 0000 C CNN +F 1 "d_inverter" H 2700 3450 60 0000 C CNN +F 2 "" H 2750 3250 60 0000 C CNN +F 3 "" H 2750 3250 60 0000 C CNN + 1 2700 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 3300 3250 3300 +Wire Wire Line + 2300 3300 2400 3300 +Wire Wire Line + 3000 2750 1950 2750 +Wire Wire Line + 1950 2750 1950 3750 +Connection ~ 3000 2750 +$Comp +L PORT U2 +U 1 1 68510A2C +P 1850 2200 +F 0 "U2" H 1900 2300 30 0000 C CNN +F 1 "PORT" H 1850 2200 30 0000 C CNN +F 2 "" H 1850 2200 60 0000 C CNN +F 3 "" H 1850 2200 60 0000 C CNN + 1 1850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 2 1 68510A87 +P 1700 3750 +F 0 "U2" H 1750 3850 30 0000 C CNN +F 1 "PORT" H 1700 3750 30 0000 C CNN +F 2 "" H 1700 3750 60 0000 C CNN +F 3 "" H 1700 3750 60 0000 C CNN + 2 1700 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 3 1 68510ACA +P 4500 3800 +F 0 "U2" H 4550 3900 30 0000 C CNN +F 1 "PORT" H 4500 3800 30 0000 C CNN +F 2 "" H 4500 3800 60 0000 C CNN +F 3 "" H 4500 3800 60 0000 C CNN + 3 4500 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 5 1 68510AFD +P 8000 2500 +F 0 "U2" H 8050 2600 30 0000 C CNN +F 1 "PORT" H 8000 2500 30 0000 C CNN +F 2 "" H 8000 2500 60 0000 C CNN +F 3 "" H 8000 2500 60 0000 C CNN + 5 8000 2500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 4 1 68510B2C +P 8150 3500 +F 0 "U2" H 8200 3600 30 0000 C CNN +F 1 "PORT" H 8150 3500 30 0000 C CNN +F 2 "" H 8150 3500 60 0000 C CNN +F 3 "" H 8150 3500 60 0000 C CNN + 4 8150 3500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 6 1 68510B5D +P 4500 1750 +F 0 "U2" H 4550 1850 30 0000 C CNN +F 1 "PORT" H 4500 1750 30 0000 C CNN +F 2 "" H 4500 1750 60 0000 C CNN +F 3 "" H 4500 1750 60 0000 C CNN + 6 4500 1750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.sub b/library/SubcircuitLibrary/74AHC1G4212/dff.sub new file mode 100644 index 000000000..885e878fc --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/dff.sub @@ -0,0 +1,34 @@ +* Subcircuit dff +.subckt dff net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ +* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and +* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand +* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7 +a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8 +a7 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends dff \ No newline at end of file diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4212/dff_Previous_Values.xml new file mode 100644 index 000000000..2a57486b8 --- /dev/null +++ b/library/SubcircuitLibrary/74AHC1G4212/dff_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_andd_andd_nandd_nandd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC563/74HC563-cache.lib b/library/SubcircuitLibrary/74HC563/74HC563-cache.lib new file mode 100644 index 000000000..bdc2c17eb --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/74HC563-cache.lib @@ -0,0 +1,89 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dlatch_own +# +DEF dlatch_own X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "dlatch_own" 50 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +S -500 400 550 -550 0 1 0 N +X D 1 -700 200 200 R 50 50 1 1 I +X G 2 -700 -200 200 R 50 50 1 1 I +X QBar 3 750 -200 200 L 50 50 1 1 O +X Q 4 750 200 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HC563/74HC563.cir b/library/SubcircuitLibrary/74HC563/74HC563.cir new file mode 100644 index 000000000..58e66e0c1 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/74HC563.cir @@ -0,0 +1,37 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\74HC563\74HC563.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 19:18:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U4-Pad1_ Net-_U11-Pad2_ Net-_U4-Pad3_ d_tristate +U5 Net-_U4-Pad3_ /19 d_inverter +U1 /11 Net-_U1-Pad2_ d_inverter +U2 /1 Net-_U11-Pad2_ d_inverter +U8 Net-_U8-Pad1_ Net-_U11-Pad2_ Net-_U8-Pad3_ d_tristate +U9 Net-_U8-Pad3_ /18 d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_tristate +U12 Net-_U11-Pad3_ /17 d_inverter +U14 Net-_U14-Pad1_ Net-_U11-Pad2_ Net-_U14-Pad3_ d_tristate +U15 Net-_U14-Pad3_ /16 d_inverter +U17 Net-_U17-Pad1_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_tristate +U18 Net-_U17-Pad3_ /15 d_inverter +U20 Net-_U20-Pad1_ Net-_U11-Pad2_ Net-_U20-Pad3_ d_tristate +U21 Net-_U20-Pad3_ /14 d_inverter +U23 Net-_U23-Pad1_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_tristate +U24 Net-_U23-Pad3_ /13 d_inverter +U26 Net-_U26-Pad1_ Net-_U11-Pad2_ Net-_U26-Pad3_ d_tristate +U27 Net-_U26-Pad3_ /12 d_inverter +U7 /1 /2 /3 /4 /5 /6 /7 /8 /9 ? /11 /12 /13 /14 /15 /16 /17 /18 /19 ? PORT +X1 /2 Net-_U1-Pad2_ ? Net-_U4-Pad1_ dlatch_own +X2 /3 Net-_U1-Pad2_ ? Net-_U8-Pad1_ dlatch_own +X3 /4 Net-_U1-Pad2_ ? Net-_U11-Pad1_ dlatch_own +X4 /5 Net-_U1-Pad2_ ? Net-_U14-Pad1_ dlatch_own +X5 /6 Net-_U1-Pad2_ ? Net-_U17-Pad1_ dlatch_own +X6 /7 Net-_U1-Pad2_ ? Net-_U20-Pad1_ dlatch_own +X7 /8 Net-_U1-Pad2_ ? Net-_U23-Pad1_ dlatch_own +X8 /9 Net-_U1-Pad2_ ? Net-_U26-Pad1_ dlatch_own + +.end diff --git a/library/SubcircuitLibrary/74HC563/74HC563.cir.out b/library/SubcircuitLibrary/74HC563/74HC563.cir.out new file mode 100644 index 000000000..2bfd978f9 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/74HC563.cir.out @@ -0,0 +1,93 @@ +* d:\fossee\esim\library\subcircuitlibrary\74hc563\74hc563.cir + +.include dlatch_own.sub +* u4 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ d_tristate +* u5 net-_u4-pad3_ /19 d_inverter +* u1 /11 net-_u1-pad2_ d_inverter +* u2 /1 net-_u11-pad2_ d_inverter +* u8 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ d_tristate +* u9 net-_u8-pad3_ /18 d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_tristate +* u12 net-_u11-pad3_ /17 d_inverter +* u14 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ d_tristate +* u15 net-_u14-pad3_ /16 d_inverter +* u17 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ d_tristate +* u18 net-_u17-pad3_ /15 d_inverter +* u20 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_tristate +* u21 net-_u20-pad3_ /14 d_inverter +* u23 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ d_tristate +* u24 net-_u23-pad3_ /13 d_inverter +* u26 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_tristate +* u27 net-_u26-pad3_ /12 d_inverter +* u7 /1 /2 /3 /4 /5 /6 /7 /8 /9 ? /11 /12 /13 /14 /15 /16 /17 /18 /19 ? port +x1 /2 net-_u1-pad2_ ? net-_u4-pad1_ dlatch_own +x2 /3 net-_u1-pad2_ ? net-_u8-pad1_ dlatch_own +x3 /4 net-_u1-pad2_ ? net-_u11-pad1_ dlatch_own +x4 /5 net-_u1-pad2_ ? net-_u14-pad1_ dlatch_own +x5 /6 net-_u1-pad2_ ? net-_u17-pad1_ dlatch_own +x6 /7 net-_u1-pad2_ ? net-_u20-pad1_ dlatch_own +x7 /8 net-_u1-pad2_ ? net-_u23-pad1_ dlatch_own +x8 /9 net-_u1-pad2_ ? net-_u26-pad1_ dlatch_own +a1 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ u4 +a2 net-_u4-pad3_ /19 u5 +a3 /11 net-_u1-pad2_ u1 +a4 /1 net-_u11-pad2_ u2 +a5 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ u8 +a6 net-_u8-pad3_ /18 u9 +a7 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ u11 +a8 net-_u11-pad3_ /17 u12 +a9 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ u14 +a10 net-_u14-pad3_ /16 u15 +a11 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ u17 +a12 net-_u17-pad3_ /15 u18 +a13 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ u20 +a14 net-_u20-pad3_ /14 u21 +a15 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ u23 +a16 net-_u23-pad3_ /13 u24 +a17 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ u26 +a18 net-_u26-pad3_ /12 u27 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HC563/74HC563.pro b/library/SubcircuitLibrary/74HC563/74HC563.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/74HC563.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC563/74HC563.sch b/library/SubcircuitLibrary/74HC563/74HC563.sch new file mode 100644 index 000000000..d100461d9 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/74HC563.sch @@ -0,0 +1,831 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74HC563-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_tristate U4 +U 1 1 6856A572 +P 7800 5900 +F 0 "U4" H 7550 6150 60 0000 C CNN +F 1 "d_tristate" H 7600 6350 60 0000 C CNN +F 2 "" H 7700 6250 60 0000 C CNN +F 3 "" H 7700 6250 60 0000 C CNN + 1 7800 5900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6856A681 +P 8150 7050 +F 0 "U5" H 8150 6950 60 0000 C CNN +F 1 "d_inverter" H 8150 7200 60 0000 C CNN +F 2 "" H 8200 7000 60 0000 C CNN +F 3 "" H 8200 7000 60 0000 C CNN + 1 8150 7050 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U1 +U 1 1 6856A7FD +P 5650 5300 +F 0 "U1" H 5650 5200 60 0000 C CNN +F 1 "d_inverter" H 5650 5450 60 0000 C CNN +F 2 "" H 5700 5250 60 0000 C CNN +F 3 "" H 5700 5250 60 0000 C CNN + 1 5650 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6856A88B +P 5700 6650 +F 0 "U2" H 5700 6550 60 0000 C CNN +F 1 "d_inverter" H 5700 6800 60 0000 C CNN +F 2 "" H 5750 6600 60 0000 C CNN +F 3 "" H 5750 6600 60 0000 C CNN + 1 5700 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U8 +U 1 1 6856AEA8 +P 9850 5950 +F 0 "U8" H 9600 6200 60 0000 C CNN +F 1 "d_tristate" H 9650 6400 60 0000 C CNN +F 2 "" H 9750 6300 60 0000 C CNN +F 3 "" H 9750 6300 60 0000 C CNN + 1 9850 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6856AEAE +P 10200 7100 +F 0 "U9" H 10200 7000 60 0000 C CNN +F 1 "d_inverter" H 10200 7250 60 0000 C CNN +F 2 "" H 10250 7050 60 0000 C CNN +F 3 "" H 10250 7050 60 0000 C CNN + 1 10200 7100 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U11 +U 1 1 6856B40C +P 12050 6000 +F 0 "U11" H 11800 6250 60 0000 C CNN +F 1 "d_tristate" H 11850 6450 60 0000 C CNN +F 2 "" H 11950 6350 60 0000 C CNN +F 3 "" H 11950 6350 60 0000 C CNN + 1 12050 6000 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6856B412 +P 12400 7150 +F 0 "U12" H 12400 7050 60 0000 C CNN +F 1 "d_inverter" H 12400 7300 60 0000 C CNN +F 2 "" H 12450 7100 60 0000 C CNN +F 3 "" H 12450 7100 60 0000 C CNN + 1 12400 7150 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U14 +U 1 1 6856B422 +P 14100 6050 +F 0 "U14" H 13850 6300 60 0000 C CNN +F 1 "d_tristate" H 13900 6500 60 0000 C CNN +F 2 "" H 14000 6400 60 0000 C CNN +F 3 "" H 14000 6400 60 0000 C CNN + 1 14100 6050 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6856B428 +P 14450 7200 +F 0 "U15" H 14450 7100 60 0000 C CNN +F 1 "d_inverter" H 14450 7350 60 0000 C CNN +F 2 "" H 14500 7150 60 0000 C CNN +F 3 "" H 14500 7150 60 0000 C CNN + 1 14450 7200 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U17 +U 1 1 6856D4A0 +P 16250 6000 +F 0 "U17" H 16000 6250 60 0000 C CNN +F 1 "d_tristate" H 16050 6450 60 0000 C CNN +F 2 "" H 16150 6350 60 0000 C CNN +F 3 "" H 16150 6350 60 0000 C CNN + 1 16250 6000 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6856D4A6 +P 16600 7250 +F 0 "U18" H 16600 7150 60 0000 C CNN +F 1 "d_inverter" H 16600 7400 60 0000 C CNN +F 2 "" H 16650 7200 60 0000 C CNN +F 3 "" H 16650 7200 60 0000 C CNN + 1 16600 7250 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U20 +U 1 1 6856D4B6 +P 18300 5950 +F 0 "U20" H 18050 6200 60 0000 C CNN +F 1 "d_tristate" H 18100 6400 60 0000 C CNN +F 2 "" H 18200 6300 60 0000 C CNN +F 3 "" H 18200 6300 60 0000 C CNN + 1 18300 5950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U21 +U 1 1 6856D4BC +P 18650 7300 +F 0 "U21" H 18650 7200 60 0000 C CNN +F 1 "d_inverter" H 18650 7450 60 0000 C CNN +F 2 "" H 18700 7250 60 0000 C CNN +F 3 "" H 18700 7250 60 0000 C CNN + 1 18650 7300 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U23 +U 1 1 6856D4CC +P 20500 6200 +F 0 "U23" H 20250 6450 60 0000 C CNN +F 1 "d_tristate" H 20300 6650 60 0000 C CNN +F 2 "" H 20400 6550 60 0000 C CNN +F 3 "" H 20400 6550 60 0000 C CNN + 1 20500 6200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 6856D4D2 +P 20850 7350 +F 0 "U24" H 20850 7250 60 0000 C CNN +F 1 "d_inverter" H 20850 7500 60 0000 C CNN +F 2 "" H 20900 7300 60 0000 C CNN +F 3 "" H 20900 7300 60 0000 C CNN + 1 20850 7350 + 0 1 1 0 +$EndComp +$Comp +L d_tristate U26 +U 1 1 6856D4E2 +P 22550 6250 +F 0 "U26" H 22300 6500 60 0000 C CNN +F 1 "d_tristate" H 22350 6700 60 0000 C CNN +F 2 "" H 22450 6600 60 0000 C CNN +F 3 "" H 22450 6600 60 0000 C CNN + 1 22550 6250 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U27 +U 1 1 6856D4E8 +P 22900 7400 +F 0 "U27" H 22900 7300 60 0000 C CNN +F 1 "d_inverter" H 22900 7550 60 0000 C CNN +F 2 "" H 22950 7350 60 0000 C CNN +F 3 "" H 22950 7350 60 0000 C CNN + 1 22900 7400 + 0 1 1 0 +$EndComp +Wire Wire Line + 8150 4100 8150 5300 +Wire Wire Line + 8150 6450 8150 6750 +Wire Wire Line + 8150 7350 8150 7700 +Wire Wire Line + 10200 4100 10200 5350 +Wire Wire Line + 10200 6500 10200 6800 +Wire Wire Line + 10200 7400 10200 7750 +Wire Wire Line + 12400 4150 12400 5400 +Wire Wire Line + 12400 6550 12400 6850 +Wire Wire Line + 12400 7450 12400 7800 +Wire Wire Line + 14450 4100 14450 5450 +Wire Wire Line + 14450 6600 14450 6900 +Wire Wire Line + 14450 7500 14450 7850 +Wire Wire Line + 16600 6550 16600 6950 +Wire Wire Line + 16600 7550 16600 7900 +Wire Wire Line + 18650 6500 18650 7000 +Wire Wire Line + 18650 7600 18650 7950 +Wire Wire Line + 20850 4250 20850 5600 +Wire Wire Line + 20850 6750 20850 7050 +Wire Wire Line + 20850 7650 20850 8000 +Wire Wire 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4500 6100 5300 +Connection ~ 6100 5300 +Wire Wire Line + 5400 6650 5100 6650 +Wire Wire Line + 5350 5300 5050 5300 +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 8300 3200 8300 4100 +Wire Wire Line + 10450 3200 10450 4150 +Wire Wire Line + 12550 4100 12800 4100 +Wire Wire Line + 12550 4100 12550 3150 +Wire Wire Line + 14650 4150 14950 4150 +Wire Wire Line + 14650 4150 14650 3300 +Wire Wire Line + 16900 4200 16750 4200 +Wire Wire Line + 16750 4200 16750 3300 +Wire Wire Line + 19100 4250 18850 4250 +Wire Wire Line + 18850 4250 18850 3350 +Wire Wire Line + 21150 4300 20950 4300 +Wire Wire Line + 20950 4300 20950 3400 +$Comp +L PORT U7 +U 1 1 68589A5A +P 4850 6650 +F 0 "U7" H 4900 6750 30 0000 C CNN +F 1 "PORT" H 4850 6650 30 0000 C CNN +F 2 "" H 4850 6650 60 0000 C CNN +F 3 "" H 4850 6650 60 0000 C CNN + 1 4850 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 5 1 68589B7D +P 12300 3150 +F 0 "U7" H 12350 3250 30 0000 C CNN +F 1 "PORT" H 12300 3150 30 0000 C CNN +F 2 "" H 12300 3150 60 0000 C CNN +F 3 "" H 12300 3150 60 0000 C CNN + 5 12300 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 9 1 68589BCA +P 20700 3400 +F 0 "U7" H 20750 3500 30 0000 C CNN +F 1 "PORT" H 20700 3400 30 0000 C CNN +F 2 "" H 20700 3400 60 0000 C CNN +F 3 "" H 20700 3400 60 0000 C CNN + 9 20700 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 13 1 68589C1D +P 20850 8250 +F 0 "U7" H 20900 8350 30 0000 C CNN +F 1 "PORT" H 20850 8250 30 0000 C CNN +F 2 "" H 20850 8250 60 0000 C CNN +F 3 "" H 20850 8250 60 0000 C CNN + 13 20850 8250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 17 1 68589C74 +P 12400 8050 +F 0 "U7" H 12450 8150 30 0000 C CNN +F 1 "PORT" H 12400 8050 30 0000 C CNN +F 2 "" H 12400 8050 60 0000 C CNN +F 3 "" H 12400 8050 60 0000 C CNN + 17 12400 8050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 2 1 68589CCB +P 5800 3200 +F 0 "U7" H 5850 3300 30 0000 C CNN +F 1 "PORT" H 5800 3200 30 0000 C CNN +F 2 "" H 5800 3200 60 0000 C CNN +F 3 "" H 5800 3200 60 0000 C CNN + 2 5800 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 6 1 68589D22 +P 14400 3300 +F 0 "U7" H 14450 3400 30 0000 C CNN +F 1 "PORT" H 14400 3300 30 0000 C CNN +F 2 "" H 14400 3300 60 0000 C CNN +F 3 "" H 14400 3300 60 0000 C CNN + 6 14400 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 10 1 68589D79 +P 4550 4400 +F 0 "U7" H 4600 4500 30 0000 C CNN +F 1 "PORT" H 4550 4400 30 0000 C CNN +F 2 "" H 4550 4400 60 0000 C CNN +F 3 "" H 4550 4400 60 0000 C CNN + 10 4550 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 14 1 68589DD2 +P 18650 8200 +F 0 "U7" H 18700 8300 30 0000 C CNN +F 1 "PORT" H 18650 8200 30 0000 C CNN +F 2 "" H 18650 8200 60 0000 C CNN +F 3 "" H 18650 8200 60 0000 C CNN + 14 18650 8200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 18 1 68589E33 +P 10200 8000 +F 0 "U7" H 10250 8100 30 0000 C CNN +F 1 "PORT" H 10200 8000 30 0000 C CNN +F 2 "" H 10200 8000 60 0000 C CNN +F 3 "" H 10200 8000 60 0000 C CNN + 18 10200 8000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 3 1 68589E94 +P 8050 3200 +F 0 "U7" H 8100 3300 30 0000 C CNN +F 1 "PORT" H 8050 3200 30 0000 C CNN +F 2 "" H 8050 3200 60 0000 C CNN +F 3 "" H 8050 3200 60 0000 C CNN + 3 8050 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 7 1 68589EF3 +P 16500 3300 +F 0 "U7" H 16550 3400 30 0000 C CNN +F 1 "PORT" H 16500 3300 30 0000 C CNN +F 2 "" H 16500 3300 60 0000 C CNN +F 3 "" H 16500 3300 60 0000 C CNN + 7 16500 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 11 1 68589F54 +P 4800 5300 +F 0 "U7" H 4850 5400 30 0000 C CNN +F 1 "PORT" H 4800 5300 30 0000 C CNN +F 2 "" H 4800 5300 60 0000 C CNN +F 3 "" H 4800 5300 60 0000 C CNN + 11 4800 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 15 1 68589FBB +P 16600 8150 +F 0 "U7" H 16650 8250 30 0000 C CNN +F 1 "PORT" H 16600 8150 30 0000 C CNN +F 2 "" H 16600 8150 60 0000 C CNN +F 3 "" H 16600 8150 60 0000 C CNN + 15 16600 8150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 19 1 6858A022 +P 8150 7950 +F 0 "U7" H 8200 8050 30 0000 C CNN +F 1 "PORT" H 8150 7950 30 0000 C CNN +F 2 "" H 8150 7950 60 0000 C CNN +F 3 "" H 8150 7950 60 0000 C CNN + 19 8150 7950 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 4 1 6858A089 +P 10200 3200 +F 0 "U7" H 10250 3300 30 0000 C CNN +F 1 "PORT" H 10200 3200 30 0000 C CNN +F 2 "" H 10200 3200 60 0000 C CNN +F 3 "" H 10200 3200 60 0000 C CNN + 4 10200 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 8 1 6858A0F8 +P 18600 3350 +F 0 "U7" H 18650 3450 30 0000 C CNN +F 1 "PORT" H 18600 3350 30 0000 C CNN +F 2 "" H 18600 3350 60 0000 C CNN +F 3 "" H 18600 3350 60 0000 C CNN + 8 18600 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U7 +U 12 1 6858A167 +P 22900 8300 +F 0 "U7" H 22950 8400 30 0000 C CNN +F 1 "PORT" H 22900 8300 30 0000 C CNN +F 2 "" H 22900 8300 60 0000 C CNN +F 3 "" H 22900 8300 60 0000 C CNN + 12 22900 8300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 16 1 6858A1D4 +P 14450 8100 +F 0 "U7" H 14500 8200 30 0000 C CNN +F 1 "PORT" H 14450 8100 30 0000 C CNN +F 2 "" H 14450 8100 60 0000 C CNN +F 3 "" H 14450 8100 60 0000 C CNN + 16 14450 8100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U7 +U 20 1 6858A243 +P 4550 4600 +F 0 "U7" H 4600 4700 30 0000 C CNN +F 1 "PORT" H 4550 4600 30 0000 C CNN +F 2 "" H 4550 4600 60 0000 C CNN +F 3 "" H 4550 4600 60 0000 C CNN + 20 4550 4600 + 1 0 0 -1 +$EndComp +Text Label 5100 6650 0 60 ~ 0 +1 +Text Label 6050 3200 0 60 ~ 0 +2 +Text Label 8300 3200 0 60 ~ 0 +3 +Text Label 10450 3200 0 60 ~ 0 +4 +Text Label 12550 3150 0 60 ~ 0 +5 +Text Label 14650 3300 0 60 ~ 0 +6 +Text Label 16750 3300 0 60 ~ 0 +7 +Text Label 18850 3350 0 60 ~ 0 +8 +Text Label 20950 3400 0 60 ~ 0 +9 +Text Label 5050 5300 0 60 ~ 0 +11 +Text Label 22900 8050 0 60 ~ 0 +12 +Text Label 20850 8000 0 60 ~ 0 +13 +Text Label 18650 7950 0 60 ~ 0 +14 +Text Label 16600 7900 0 60 ~ 0 +15 +Text Label 14450 7850 0 60 ~ 0 +16 +Text Label 12400 7800 0 60 ~ 0 +17 +Text Label 10200 7750 0 60 ~ 0 +18 +Text Label 8150 7700 0 60 ~ 0 +19 +NoConn ~ 4800 4400 +NoConn ~ 4800 4600 +$Comp +L dlatch_own X1 +U 1 1 6856BAE2 +P 7000 4300 +F 0 "X1" H 7000 4250 60 0000 C CNN +F 1 "dlatch_own" H 7050 4350 60 0000 C CNN +F 2 "" H 7000 4250 60 0001 C CNN +F 3 "" H 7000 4250 60 0001 C CNN + 1 7000 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 4100 6300 4100 +Wire Wire Line + 6100 4500 6300 4500 +Wire Wire Line + 7750 4100 8150 4100 +NoConn ~ 7750 4500 +$Comp +L dlatch_own X2 +U 1 1 6856C093 +P 9100 4300 +F 0 "X2" H 9100 4250 60 0000 C CNN +F 1 "dlatch_own" H 9150 4350 60 0000 C CNN +F 2 "" H 9100 4250 60 0001 C CNN +F 3 "" H 9100 4250 60 0001 C CNN + 1 9100 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10200 4100 9850 4100 +Wire Wire Line + 8300 4100 8400 4100 +Wire Wire Line + 8300 4500 8400 4500 +NoConn ~ 9850 4500 +$Comp +L dlatch_own X3 +U 1 1 6856CA39 +P 11300 4350 +F 0 "X3" H 11300 4300 60 0000 C CNN +F 1 "dlatch_own" H 11350 4400 60 0000 C CNN +F 2 "" H 11300 4300 60 0001 C CNN +F 3 "" H 11300 4300 60 0001 C CNN + 1 11300 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10450 4150 10600 4150 +Wire Wire Line + 10350 4550 10600 4550 +NoConn ~ 12050 4550 +Wire Wire Line + 12050 4150 12400 4150 +$Comp +L dlatch_own X4 +U 1 1 6856E6F1 +P 13500 4300 +F 0 "X4" H 13500 4250 60 0000 C CNN +F 1 "dlatch_own" H 13550 4350 60 0000 C CNN +F 2 "" H 13500 4250 60 0001 C CNN +F 3 "" H 13500 4250 60 0001 C CNN + 1 13500 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14450 4100 14250 4100 +Wire Wire Line + 12700 4750 12700 4500 +Wire Wire Line + 12700 4500 12800 4500 +NoConn ~ 14250 4500 +$Comp +L dlatch_own X5 +U 1 1 6856E9A6 +P 15650 4350 +F 0 "X5" H 15650 4300 60 0000 C CNN +F 1 "dlatch_own" H 15700 4400 60 0000 C CNN +F 2 "" H 15650 4300 60 0001 C CNN +F 3 "" H 15650 4300 60 0001 C CNN + 1 15650 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14850 4800 14850 4550 +Wire Wire Line + 14850 4550 14950 4550 +Wire Wire Line + 16600 4150 16400 4150 +NoConn ~ 16400 4550 +$Comp +L dlatch_own X6 +U 1 1 6856F59B +P 17600 4400 +F 0 "X6" H 17600 4350 60 0000 C CNN +F 1 "dlatch_own" H 17650 4450 60 0000 C CNN +F 2 "" H 17600 4350 60 0001 C CNN +F 3 "" H 17600 4350 60 0001 C CNN + 1 17600 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18350 4200 18650 4200 +NoConn ~ 18350 4600 +Wire Wire Line + 16900 4850 16900 4750 +Wire Wire Line + 16900 4750 16700 4750 +Wire Wire Line + 16700 4750 16700 4600 +Wire Wire Line + 16700 4600 16900 4600 +$Comp +L dlatch_own X7 +U 1 1 68570F1C +P 19800 4450 +F 0 "X7" H 19800 4400 60 0000 C CNN +F 1 "dlatch_own" H 19850 4500 60 0000 C CNN +F 2 "" H 19800 4400 60 0001 C CNN +F 3 "" H 19800 4400 60 0001 C CNN + 1 19800 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20550 4250 20850 4250 +NoConn ~ 20550 4650 +Wire Wire Line + 19100 4900 19100 4800 +Wire Wire Line + 19100 4800 18850 4800 +Wire Wire Line + 18850 4800 18850 4650 +Wire Wire Line + 18850 4650 19100 4650 +$Comp +L dlatch_own X8 +U 1 1 68571CD8 +P 21850 4500 +F 0 "X8" H 21850 4450 60 0000 C CNN +F 1 "dlatch_own" H 21900 4550 60 0000 C CNN +F 2 "" H 21850 4450 60 0001 C CNN +F 3 "" H 21850 4450 60 0001 C CNN + 1 21850 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 22600 4300 22900 4300 +NoConn ~ 22600 4700 +Wire Wire Line + 21000 4700 21150 4700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HC563/74HC563.sub b/library/SubcircuitLibrary/74HC563/74HC563.sub new file mode 100644 index 000000000..7c25f3637 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/74HC563.sub @@ -0,0 +1,87 @@ +* Subcircuit 74HC563 +.subckt 74HC563 /1 /2 /3 /4 /5 /6 /7 /8 /9 ? /11 /12 /13 /14 /15 /16 /17 /18 /19 ? +* d:\fossee\esim\library\subcircuitlibrary\74hc563\74hc563.cir +.include dlatch_own.sub +* u4 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ d_tristate +* u5 net-_u4-pad3_ /19 d_inverter +* u1 /11 net-_u1-pad2_ d_inverter +* u2 /1 net-_u11-pad2_ d_inverter +* u8 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ d_tristate +* u9 net-_u8-pad3_ /18 d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_tristate +* u12 net-_u11-pad3_ /17 d_inverter +* u14 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ d_tristate +* u15 net-_u14-pad3_ /16 d_inverter +* u17 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ d_tristate +* u18 net-_u17-pad3_ /15 d_inverter +* u20 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_tristate +* u21 net-_u20-pad3_ /14 d_inverter +* u23 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ d_tristate +* u24 net-_u23-pad3_ /13 d_inverter +* u26 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_tristate +* u27 net-_u26-pad3_ /12 d_inverter +x1 /2 net-_u1-pad2_ ? net-_u4-pad1_ dlatch_own +x2 /3 net-_u1-pad2_ ? net-_u8-pad1_ dlatch_own +x3 /4 net-_u1-pad2_ ? net-_u11-pad1_ dlatch_own +x4 /5 net-_u1-pad2_ ? net-_u14-pad1_ dlatch_own +x5 /6 net-_u1-pad2_ ? net-_u17-pad1_ dlatch_own +x6 /7 net-_u1-pad2_ ? net-_u20-pad1_ dlatch_own +x7 /8 net-_u1-pad2_ ? net-_u23-pad1_ dlatch_own +x8 /9 net-_u1-pad2_ ? net-_u26-pad1_ dlatch_own +a1 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ u4 +a2 net-_u4-pad3_ /19 u5 +a3 /11 net-_u1-pad2_ u1 +a4 /1 net-_u11-pad2_ u2 +a5 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ u8 +a6 net-_u8-pad3_ /18 u9 +a7 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ u11 +a8 net-_u11-pad3_ /17 u12 +a9 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ u14 +a10 net-_u14-pad3_ /16 u15 +a11 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ u17 +a12 net-_u17-pad3_ /15 u18 +a13 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ u20 +a14 net-_u20-pad3_ /14 u21 +a15 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ u23 +a16 net-_u23-pad3_ /13 u24 +a17 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ u26 +a18 net-_u26-pad3_ /12 u27 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74HC563 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC563/74HC563_Previous_Values.xml b/library/SubcircuitLibrary/74HC563/74HC563_Previous_Values.xml new file mode 100644 index 000000000..18576c0c0 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/74HC563_Previous_Values.xml @@ -0,0 +1 @@ +d_dlatchd_tristated_inverterd_inverterd_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_owntruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC563/analysis b/library/SubcircuitLibrary/74HC563/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own-cache.lib b/library/SubcircuitLibrary/74HC563/dlatch_own-cache.lib new file mode 100644 index 000000000..c743d042c --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/dlatch_own-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.cir b/library/SubcircuitLibrary/74HC563/dlatch_own.cir new file mode 100644 index 000000000..f79b758d8 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/dlatch_own.cir @@ -0,0 +1,16 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_own\dlatch_own.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 19:09:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and +U4 Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U4-Pad3_ d_and +U5 Net-_U3-Pad3_ Net-_U2-Pad3_ Net-_U2-Pad4_ d_nor +U6 Net-_U2-Pad4_ Net-_U4-Pad3_ Net-_U2-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.cir.out b/library/SubcircuitLibrary/74HC563/dlatch_own.cir.out new file mode 100644 index 000000000..5bcd05907 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/dlatch_own.cir.out @@ -0,0 +1,32 @@ +* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir + +* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and +* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor +* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ port +a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5 +a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6 +a5 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.pro b/library/SubcircuitLibrary/74HC563/dlatch_own.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/dlatch_own.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.sch b/library/SubcircuitLibrary/74HC563/dlatch_own.sch new file mode 100644 index 000000000..9ed392a0c --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/dlatch_own.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U3 +U 1 1 6856B545 +P 4350 3350 +F 0 "U3" H 4350 3350 60 0000 C CNN +F 1 "d_and" H 4400 3450 60 0000 C CNN +F 2 "" H 4350 3350 60 0000 C CNN +F 3 "" H 4350 3350 60 0000 C CNN + 1 4350 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 6856B5D2 +P 4400 4750 +F 0 "U4" H 4400 4750 60 0000 C CNN +F 1 "d_and" H 4450 4850 60 0000 C CNN +F 2 "" H 4400 4750 60 0000 C CNN +F 3 "" H 4400 4750 60 0000 C CNN + 1 4400 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 6856B5DC +P 7300 3350 +F 0 "U5" H 7300 3350 60 0000 C CNN +F 1 "d_nor" H 7350 3450 60 0000 C CNN +F 2 "" H 7300 3350 60 0000 C CNN +F 3 "" H 7300 3350 60 0000 C CNN + 1 7300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 6856B689 +P 7300 4750 +F 0 "U6" H 7300 4750 60 0000 C CNN +F 1 "d_nor" H 7350 4850 60 0000 C CNN +F 2 "" H 7300 4750 60 0000 C CNN +F 3 "" H 7300 4750 60 0000 C CNN + 1 7300 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 6856B986 +P 2800 3250 +F 0 "U1" H 2800 3150 60 0000 C CNN +F 1 "d_inverter" H 2800 3400 60 0000 C CNN +F 2 "" H 2850 3200 60 0000 C CNN +F 3 "" H 2850 3200 60 0000 C CNN + 1 2800 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3300 8750 3300 +Wire Wire Line + 7750 4700 9050 4700 +Wire Wire Line + 6850 4650 6500 4650 +Wire Wire Line + 6500 4650 6500 4300 +Wire Wire Line + 6500 4300 8400 4300 +Wire Wire Line + 8400 4300 8400 3300 +Connection ~ 8400 3300 +Wire Wire Line + 8250 4700 8250 3800 +Wire Wire Line + 8250 3800 6600 3800 +Wire Wire Line + 6600 3800 6600 3350 +Wire Wire Line + 6600 3350 6850 3350 +Connection ~ 8250 4700 +Wire Wire Line + 5150 4700 5150 4750 +Wire Wire Line + 5150 4750 6850 4750 +Wire Wire Line + 4850 4700 5150 4700 +Wire Wire Line + 4800 3300 6400 3300 +Wire Wire Line + 6400 3300 6400 3250 +Wire Wire Line + 6400 3250 6850 3250 +Wire Wire Line + 3900 3350 3450 3350 +Wire Wire Line + 3450 3350 3450 4650 +Wire Wire Line + 3450 4650 3950 4650 +Wire Wire Line + 3950 4750 2500 4750 +Wire Wire Line + 3100 3250 3900 3250 +Wire Wire Line + 2500 3250 2500 4150 +Wire Wire Line + 2500 4150 2800 4150 +Wire Wire Line + 2800 4150 2800 4750 +Connection ~ 2800 4750 +Wire Wire Line + 3450 3950 3200 3950 +Connection ~ 3450 3950 +$Comp +L PORT U2 +U 1 1 6856BAF3 +P 2250 4750 +F 0 "U2" H 2300 4850 30 0000 C CNN +F 1 "PORT" H 2250 4750 30 0000 C CNN +F 2 "" H 2250 4750 60 0000 C CNN +F 3 "" H 2250 4750 60 0000 C CNN + 1 2250 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 3 1 6856BB14 +P 9300 4700 +F 0 "U2" H 9350 4800 30 0000 C CNN +F 1 "PORT" H 9300 4700 30 0000 C CNN +F 2 "" H 9300 4700 60 0000 C CNN +F 3 "" H 9300 4700 60 0000 C CNN + 3 9300 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 6856BB59 +P 2950 3950 +F 0 "U2" H 3000 4050 30 0000 C CNN +F 1 "PORT" H 2950 3950 30 0000 C CNN +F 2 "" H 2950 3950 60 0000 C CNN +F 3 "" H 2950 3950 60 0000 C CNN + 2 2950 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 4 1 6856BB9A +P 9000 3300 +F 0 "U2" H 9050 3400 30 0000 C CNN +F 1 "PORT" H 9000 3300 30 0000 C CNN +F 2 "" H 9000 3300 60 0000 C CNN +F 3 "" H 9000 3300 60 0000 C CNN + 4 9000 3300 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.sub b/library/SubcircuitLibrary/74HC563/dlatch_own.sub new file mode 100644 index 000000000..38e1779a5 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/dlatch_own.sub @@ -0,0 +1,26 @@ +* Subcircuit dlatch_own +.subckt dlatch_own net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ +* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir +* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and +* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor +* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5 +a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6 +a5 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends dlatch_own \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own_Previous_Values.xml b/library/SubcircuitLibrary/74HC563/dlatch_own_Previous_Values.xml new file mode 100644 index 000000000..0a9ca5d55 --- /dev/null +++ b/library/SubcircuitLibrary/74HC563/dlatch_own_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nord_nord_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98-cache.lib b/library/SubcircuitLibrary/SN54L98/SN54L98-cache.lib new file mode 100644 index 000000000..5d02d5fe4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SN54L98-cache.lib @@ -0,0 +1,125 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# SR_FF1 +# +DEF SR_FF1 X 0 40 Y Y 1 F N +F0 "X" 0 -550 60 H V C CNN +F1 "SR_FF1" 0 250 60 H V C CNN +F2 "" 0 250 60 H I C CNN +F3 "" 0 250 60 H I C CNN +DRAW +S -250 200 250 -500 0 1 0 N +X S 1 -450 100 200 R 50 50 1 1 I +X CLK 2 -450 -100 200 R 50 50 1 1 I +X R 3 -450 -300 200 R 50 50 1 1 I +X QBar 4 450 -200 200 L 50 50 1 1 O +X Q 5 450 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.cir b/library/SubcircuitLibrary/SN54L98/SN54L98.cir new file mode 100644 index 000000000..6f0602b90 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SN54L98.cir @@ -0,0 +1,34 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN54L98\SN54L98.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 09:28:48 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 /2 Net-_U1-Pad2_ Net-_U12-Pad1_ d_and +U4 Net-_U10-Pad1_ /1 Net-_U12-Pad2_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nor +U5 Net-_U24-Pad3_ Net-_U1-Pad2_ Net-_U13-Pad1_ d_and +U6 Net-_U10-Pad1_ /4 Net-_U13-Pad2_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nor +U7 /5 Net-_U1-Pad2_ Net-_U14-Pad1_ d_and +U8 Net-_U10-Pad1_ /6 Net-_U14-Pad2_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U9 /12 Net-_U1-Pad2_ Net-_U15-Pad1_ d_and +U10 Net-_U10-Pad1_ /7 Net-_U10-Pad3_ d_and +U15 Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_nor +U1 /9 Net-_U1-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U10-Pad1_ d_inverter +U16 Net-_U12-Pad3_ Net-_U16-Pad2_ d_inverter +U17 Net-_U13-Pad3_ Net-_U17-Pad2_ d_inverter +U18 Net-_U14-Pad3_ Net-_U18-Pad2_ d_inverter +U19 Net-_U15-Pad3_ Net-_U19-Pad2_ d_inverter +U11 /10 Net-_U11-Pad2_ d_buffer +U24 /1 /2 Net-_U24-Pad3_ /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 Net-_U24-Pad15_ ? PORT +X1 Net-_U16-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad3_ ? Net-_U24-Pad15_ SR_FF1 +X2 Net-_U17-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad3_ ? /14 SR_FF1 +X3 Net-_U18-Pad2_ Net-_U11-Pad2_ Net-_U14-Pad3_ ? /13 SR_FF1 +X4 Net-_U19-Pad2_ Net-_U11-Pad2_ Net-_U15-Pad3_ ? /11 SR_FF1 + +.end diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.cir.out b/library/SubcircuitLibrary/SN54L98/SN54L98.cir.out new file mode 100644 index 000000000..ae6b014bc --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SN54L98.cir.out @@ -0,0 +1,93 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn54l98\sn54l98.cir + +.include SR_FF1.sub +* u3 /2 net-_u1-pad2_ net-_u12-pad1_ d_and +* u4 net-_u10-pad1_ /1 net-_u12-pad2_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor +* u5 net-_u24-pad3_ net-_u1-pad2_ net-_u13-pad1_ d_and +* u6 net-_u10-pad1_ /4 net-_u13-pad2_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor +* u7 /5 net-_u1-pad2_ net-_u14-pad1_ d_and +* u8 net-_u10-pad1_ /6 net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u9 /12 net-_u1-pad2_ net-_u15-pad1_ d_and +* u10 net-_u10-pad1_ /7 net-_u10-pad3_ d_and +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_nor +* u1 /9 net-_u1-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u10-pad1_ d_inverter +* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter +* u17 net-_u13-pad3_ net-_u17-pad2_ d_inverter +* u18 net-_u14-pad3_ net-_u18-pad2_ d_inverter +* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter +* u11 /10 net-_u11-pad2_ d_buffer +* u24 /1 /2 net-_u24-pad3_ /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 net-_u24-pad15_ ? port +x1 net-_u16-pad2_ net-_u11-pad2_ net-_u12-pad3_ ? net-_u24-pad15_ SR_FF1 +x2 net-_u17-pad2_ net-_u11-pad2_ net-_u13-pad3_ ? /14 SR_FF1 +x3 net-_u18-pad2_ net-_u11-pad2_ net-_u14-pad3_ ? /13 SR_FF1 +x4 net-_u19-pad2_ net-_u11-pad2_ net-_u15-pad3_ ? /11 SR_FF1 +a1 [/2 net-_u1-pad2_ ] net-_u12-pad1_ u3 +a2 [net-_u10-pad1_ /1 ] net-_u12-pad2_ u4 +a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a4 [net-_u24-pad3_ net-_u1-pad2_ ] net-_u13-pad1_ u5 +a5 [net-_u10-pad1_ /4 ] net-_u13-pad2_ u6 +a6 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a7 [/5 net-_u1-pad2_ ] net-_u14-pad1_ u7 +a8 [net-_u10-pad1_ /6 ] net-_u14-pad2_ u8 +a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a10 [/12 net-_u1-pad2_ ] net-_u15-pad1_ u9 +a11 [net-_u10-pad1_ /7 ] net-_u10-pad3_ u10 +a12 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a13 /9 net-_u1-pad2_ u1 +a14 net-_u1-pad2_ net-_u10-pad1_ u2 +a15 net-_u12-pad3_ net-_u16-pad2_ u16 +a16 net-_u13-pad3_ net-_u17-pad2_ u17 +a17 net-_u14-pad3_ net-_u18-pad2_ u18 +a18 net-_u15-pad3_ net-_u19-pad2_ u19 +a19 /10 net-_u11-pad2_ u11 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.pro b/library/SubcircuitLibrary/SN54L98/SN54L98.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SN54L98.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.sch b/library/SubcircuitLibrary/SN54L98/SN54L98.sch new file mode 100644 index 000000000..8e9c34e38 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SN54L98.sch @@ -0,0 +1,775 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN54L98-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U3 +U 1 1 684462F9 +P 7050 2750 +F 0 "U3" H 7050 2750 60 0000 C CNN +F 1 "d_and" H 7100 2850 60 0000 C CNN +F 2 "" H 7050 2750 60 0000 C CNN +F 3 "" H 7050 2750 60 0000 C CNN + 1 7050 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 6844638C +P 7050 3150 +F 0 "U4" H 7050 3150 60 0000 C CNN +F 1 "d_and" H 7100 3250 60 0000 C CNN +F 2 "" H 7050 3150 60 0000 C CNN +F 3 "" H 7050 3150 60 0000 C CNN + 1 7050 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 684463BD +P 8300 2950 +F 0 "U12" H 8300 2950 60 0000 C CNN +F 1 "d_nor" H 8350 3050 60 0000 C CNN +F 2 "" H 8300 2950 60 0000 C CNN +F 3 "" H 8300 2950 60 0000 C CNN + 1 8300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 684464BF +P 7050 3700 +F 0 "U5" H 7050 3700 60 0000 C CNN +F 1 "d_and" H 7100 3800 60 0000 C CNN +F 2 "" H 7050 3700 60 0000 C CNN +F 3 "" H 7050 3700 60 0000 C CNN + 1 7050 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 684464C5 +P 7050 4100 +F 0 "U6" H 7050 4100 60 0000 C CNN +F 1 "d_and" H 7100 4200 60 0000 C CNN +F 2 "" H 7050 4100 60 0000 C CNN +F 3 "" H 7050 4100 60 0000 C CNN + 1 7050 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U13 +U 1 1 684464CB +P 8300 3900 +F 0 "U13" H 8300 3900 60 0000 C CNN +F 1 "d_nor" H 8350 4000 60 0000 C CNN +F 2 "" H 8300 3900 60 0000 C CNN +F 3 "" H 8300 3900 60 0000 C CNN + 1 8300 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 684465EB +P 7050 4600 +F 0 "U7" H 7050 4600 60 0000 C CNN +F 1 "d_and" H 7100 4700 60 0000 C CNN +F 2 "" H 7050 4600 60 0000 C CNN +F 3 "" H 7050 4600 60 0000 C CNN + 1 7050 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 684465F1 +P 7050 5000 +F 0 "U8" H 7050 5000 60 0000 C CNN +F 1 "d_and" H 7100 5100 60 0000 C CNN +F 2 "" H 7050 5000 60 0000 C CNN +F 3 "" H 7050 5000 60 0000 C CNN + 1 7050 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 684465F7 +P 8300 4800 +F 0 "U14" H 8300 4800 60 0000 C CNN +F 1 "d_nor" H 8350 4900 60 0000 C CNN +F 2 "" H 8300 4800 60 0000 C CNN +F 3 "" H 8300 4800 60 0000 C CNN + 1 8300 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 684465FD +P 7050 5550 +F 0 "U9" H 7050 5550 60 0000 C CNN +F 1 "d_and" H 7100 5650 60 0000 C CNN +F 2 "" H 7050 5550 60 0000 C CNN +F 3 "" H 7050 5550 60 0000 C CNN + 1 7050 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 68446603 +P 7050 5950 +F 0 "U10" H 7050 5950 60 0000 C CNN +F 1 "d_and" H 7100 6050 60 0000 C CNN +F 2 "" H 7050 5950 60 0000 C CNN +F 3 "" H 7050 5950 60 0000 C CNN + 1 7050 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 68446609 +P 8300 5750 +F 0 "U15" H 8300 5750 60 0000 C CNN +F 1 "d_nor" H 8350 5850 60 0000 C CNN +F 2 "" H 8300 5750 60 0000 C CNN +F 3 "" H 8300 5750 60 0000 C CNN + 1 8300 5750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 68448362 +P 4050 2800 +F 0 "U1" H 4050 2700 60 0000 C CNN +F 1 "d_inverter" H 4050 2950 60 0000 C CNN +F 2 "" H 4100 2750 60 0000 C CNN +F 3 "" H 4100 2750 60 0000 C CNN + 1 4050 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6844844E +P 4450 3250 +F 0 "U2" H 4450 3150 60 0000 C CNN +F 1 "d_inverter" H 4450 3400 60 0000 C CNN +F 2 "" H 4500 3200 60 0000 C CNN +F 3 "" H 4500 3200 60 0000 C CNN + 1 4450 3250 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U16 +U 1 1 68448BC5 +P 9400 2900 +F 0 "U16" H 9400 2800 60 0000 C CNN +F 1 "d_inverter" H 9400 3050 60 0000 C CNN +F 2 "" H 9450 2850 60 0000 C CNN +F 3 "" H 9450 2850 60 0000 C CNN + 1 9400 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 68448C3E +P 9400 3850 +F 0 "U17" H 9400 3750 60 0000 C CNN +F 1 "d_inverter" H 9400 4000 60 0000 C CNN +F 2 "" H 9450 3800 60 0000 C CNN +F 3 "" H 9450 3800 60 0000 C CNN + 1 9400 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 68448CDD +P 9400 4750 +F 0 "U18" H 9400 4650 60 0000 C CNN +F 1 "d_inverter" H 9400 4900 60 0000 C CNN +F 2 "" H 9450 4700 60 0000 C CNN +F 3 "" H 9450 4700 60 0000 C CNN + 1 9400 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 68448CE3 +P 9450 5700 +F 0 "U19" H 9450 5600 60 0000 C CNN +F 1 "d_inverter" H 9450 5850 60 0000 C CNN +F 2 "" H 9500 5650 60 0000 C CNN +F 3 "" H 9500 5650 60 0000 C CNN + 1 9450 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U11 +U 1 1 6844B65C +P 7100 7150 +F 0 "U11" H 7100 7100 60 0000 C CNN +F 1 "d_buffer" H 7100 7200 60 0000 C CNN +F 2 "" H 7100 7150 60 0000 C CNN +F 3 "" H 7100 7150 60 0000 C CNN + 1 7100 7150 + 1 0 0 -1 +$EndComp +NoConn ~ 9500 350 +Text Label 12100 3400 0 60 ~ 0 +14 +Text Label 12200 5050 0 60 ~ 0 +13 +Text Label 12200 6750 0 60 ~ 0 +11 +Text Label 5000 7150 0 60 ~ 0 +10 +Text Label 5200 5950 0 60 ~ 0 +7 +Text Label 5000 5450 0 60 ~ 0 +12 +Text Label 5000 5000 0 60 ~ 0 +6 +Text Label 5000 4500 0 60 ~ 0 +5 +Text Label 5000 4100 0 60 ~ 0 +4 +Text Label 5000 3600 0 60 ~ 0 +3 +Text Label 5000 3150 0 60 ~ 0 +1 +Text Label 5000 2650 0 60 ~ 0 +2 +Text Label 3250 2800 0 60 ~ 0 +9 +$Comp +L PORT U24 +U 4 1 6845B79C +P 4750 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5950 60 0000 C CNN +F 3 "" H 4950 5950 60 0000 C CNN + 7 4950 5950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U24 +U 13 1 6845B975 +P 12450 5200 +F 0 "U24" H 12500 5300 30 0000 C CNN +F 1 "PORT" H 12450 5200 30 0000 C CNN +F 2 "" H 12450 5200 60 0000 C CNN +F 3 "" H 12450 5200 60 0000 C CNN + 13 12450 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U24 +U 5 1 6845B9C6 +P 4750 4500 +F 0 "U24" H 4800 4600 30 0000 C CNN +F 1 "PORT" H 4750 4500 30 0000 C CNN +F 2 "" H 4750 4500 60 0000 C CNN +F 3 "" H 4750 4500 60 0000 C CNN + 5 4750 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U24 +U 10 1 6845BA17 +P 4750 7150 +F 0 "U24" H 4800 7250 30 0000 C CNN +F 1 "PORT" H 4750 7150 30 0000 C CNN +F 2 "" H 4750 7150 60 0000 C CNN +F 3 "" H 4750 7150 60 0000 C CNN + 10 4750 7150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U24 +U 15 1 6845BA6A +P 11900 1850 +F 0 "U24" H 11950 1950 30 0000 C CNN +F 1 "PORT" H 11900 1850 30 0000 C CNN +F 2 "" H 11900 1850 60 0000 C CNN +F 3 "" H 11900 1850 60 0000 C CNN + 15 11900 1850 + -1 0 0 1 +$EndComp +$Comp +L PORT U24 +U 1 1 6845BABF +P 4750 3150 +F 0 "U24" H 4800 3250 30 0000 C CNN +F 1 "PORT" H 4750 3150 30 0000 C CNN +F 2 "" H 4750 3150 60 0000 C CNN +F 3 "" H 4750 3150 60 0000 C CNN + 1 4750 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U24 +U 6 1 6845BB3E +P 4750 5000 +F 0 "U24" H 4800 5100 30 0000 C CNN +F 1 "PORT" H 4750 5000 30 0000 C CNN +F 2 "" H 4750 5000 60 0000 C CNN +F 3 "" H 4750 5000 60 0000 C CNN + 6 4750 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U24 +U 11 1 6845BB97 +P 12450 6750 +F 0 "U24" H 12500 6850 30 0000 C CNN +F 1 "PORT" H 12450 6750 30 0000 C CNN +F 2 "" H 12450 6750 60 0000 C CNN +F 3 "" H 12450 6750 60 0000 C CNN + 11 12450 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U24 +U 16 1 6845BBF8 +P 7850 1950 +F 0 "U24" H 7900 2050 30 0000 C CNN +F 1 "PORT" H 7850 1950 30 0000 C CNN +F 2 "" H 7850 1950 60 0000 C CNN +F 3 "" H 7850 1950 60 0000 C CNN + 16 7850 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U24 +U 3 1 6845BC55 +P 4800 3650 +F 0 "U24" H 4850 3750 30 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/1 /2 net-_u24-pad3_ /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 net-_u24-pad15_ ? +* d:\fossee\esim\library\subcircuitlibrary\sn54l98\sn54l98.cir +.include SR_FF1.sub +* u3 /2 net-_u1-pad2_ net-_u12-pad1_ d_and +* u4 net-_u10-pad1_ /1 net-_u12-pad2_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor +* u5 net-_u24-pad3_ net-_u1-pad2_ net-_u13-pad1_ d_and +* u6 net-_u10-pad1_ /4 net-_u13-pad2_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor +* u7 /5 net-_u1-pad2_ net-_u14-pad1_ d_and +* u8 net-_u10-pad1_ /6 net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u9 /12 net-_u1-pad2_ net-_u15-pad1_ d_and +* u10 net-_u10-pad1_ /7 net-_u10-pad3_ d_and +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_nor +* u1 /9 net-_u1-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u10-pad1_ d_inverter +* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter +* u17 net-_u13-pad3_ net-_u17-pad2_ d_inverter +* u18 net-_u14-pad3_ net-_u18-pad2_ d_inverter +* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter +* u11 /10 net-_u11-pad2_ d_buffer +x1 net-_u16-pad2_ net-_u11-pad2_ net-_u12-pad3_ ? net-_u24-pad15_ SR_FF1 +x2 net-_u17-pad2_ net-_u11-pad2_ net-_u13-pad3_ ? /14 SR_FF1 +x3 net-_u18-pad2_ net-_u11-pad2_ net-_u14-pad3_ ? /13 SR_FF1 +x4 net-_u19-pad2_ net-_u11-pad2_ net-_u15-pad3_ ? /11 SR_FF1 +a1 [/2 net-_u1-pad2_ ] net-_u12-pad1_ u3 +a2 [net-_u10-pad1_ /1 ] net-_u12-pad2_ u4 +a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a4 [net-_u24-pad3_ net-_u1-pad2_ ] net-_u13-pad1_ u5 +a5 [net-_u10-pad1_ /4 ] net-_u13-pad2_ u6 +a6 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a7 [/5 net-_u1-pad2_ ] net-_u14-pad1_ u7 +a8 [net-_u10-pad1_ /6 ] net-_u14-pad2_ u8 +a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a10 [/12 net-_u1-pad2_ ] net-_u15-pad1_ u9 +a11 [net-_u10-pad1_ /7 ] net-_u10-pad3_ u10 +a12 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a13 /9 net-_u1-pad2_ u1 +a14 net-_u1-pad2_ net-_u10-pad1_ u2 +a15 net-_u12-pad3_ net-_u16-pad2_ u16 +a16 net-_u13-pad3_ net-_u17-pad2_ u17 +a17 net-_u14-pad3_ net-_u18-pad2_ u18 +a18 net-_u15-pad3_ net-_u19-pad2_ u19 +a19 /10 net-_u11-pad2_ u11 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54L98 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/SN54L98_Previous_Values.xml new file mode 100644 index 000000000..df78e8b71 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SN54L98_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_nord_andd_andd_nord_andd_andd_nord_andd_andd_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_srffd_srffd_srffd_srffd_bufferD:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1-cache.lib b/library/SubcircuitLibrary/SN54L98/SR_FF1-cache.lib new file mode 100644 index 000000000..ce6d8814c --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SR_FF1-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.cir b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir new file mode 100644 index 000000000..ba6a8f971 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir @@ -0,0 +1,15 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF\SR_FF.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 17:59:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U4 Net-_U2-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_nand +U5 Net-_U1-Pad5_ Net-_U3-Pad3_ Net-_U1-Pad4_ d_nand +U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.cir.out b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir.out new file mode 100644 index 000000000..33d1c4912 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir.out @@ -0,0 +1,28 @@ +* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand +* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4 +a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.pro b/library/SubcircuitLibrary/SN54L98/SR_FF1.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.sch b/library/SubcircuitLibrary/SN54L98/SR_FF1.sch new file mode 100644 index 000000000..58667c880 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.sch @@ -0,0 +1,198 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 686919A7 +P 4350 2800 +F 0 "U2" H 4350 2800 60 0000 C CNN +F 1 "d_nand" H 4400 2900 60 0000 C CNN +F 2 "" H 4350 2800 60 0000 C CNN +F 3 "" H 4350 2800 60 0000 C CNN + 1 4350 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 686919EC +P 5850 2800 +F 0 "U4" H 5850 2800 60 0000 C CNN +F 1 "d_nand" H 5900 2900 60 0000 C CNN +F 2 "" H 5850 2800 60 0000 C CNN +F 3 "" H 5850 2800 60 0000 C CNN + 1 5850 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68691A1F +P 5900 4000 +F 0 "U5" H 5900 4000 60 0000 C CNN +F 1 "d_nand" H 5950 4100 60 0000 C CNN +F 2 "" H 5900 4000 60 0000 C CNN +F 3 "" H 5900 4000 60 0000 C CNN + 1 5900 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 2750 6800 2750 +Wire Wire Line + 6350 3950 7000 3950 +Wire Wire Line + 6700 2750 6700 3300 +Wire Wire Line + 6700 3300 5200 3300 +Wire Wire Line + 5200 3300 5200 3900 +Wire Wire Line + 5200 3900 5450 3900 +Connection ~ 6700 2750 +Wire Wire Line + 6550 3950 6550 3050 +Wire Wire Line + 6550 3050 5250 3050 +Wire Wire Line + 5250 3050 5250 2800 +Wire Wire Line + 5250 2800 5400 2800 +Connection ~ 6550 3950 +$Comp +L d_nand U3 +U 1 1 68691A8B +P 4350 4050 +F 0 "U3" H 4350 4050 60 0000 C CNN +F 1 "d_nand" H 4400 4150 60 0000 C CNN +F 2 "" H 4350 4050 60 0000 C CNN +F 3 "" H 4350 4050 60 0000 C CNN + 1 4350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 2750 4900 2750 +Wire Wire Line + 4900 2750 4900 2700 +Wire Wire Line + 4900 2700 5400 2700 +Wire Wire Line + 4800 4000 5450 4000 +Wire Wire Line + 3900 2800 3600 2800 +Wire Wire Line + 3600 2800 3600 3950 +Wire Wire Line + 3600 3950 3900 3950 +Wire Wire Line + 3900 2700 3150 2700 +Wire Wire Line + 3900 4050 3150 4050 +Wire Wire Line + 3600 3350 2400 3350 +Connection ~ 3600 3350 +$Comp +L PORT U1 +U 4 1 68691B28 +P 7250 3950 +F 0 "U1" H 7300 4050 30 0000 C CNN +F 1 "PORT" H 7250 3950 30 0000 C CNN +F 2 "" H 7250 3950 60 0000 C CNN +F 3 "" H 7250 3950 60 0000 C CNN + 4 7250 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68691BB8 +P 7050 2750 +F 0 "U1" H 7100 2850 30 0000 C CNN +F 1 "PORT" H 7050 2750 30 0000 C CNN +F 2 "" H 7050 2750 60 0000 C CNN +F 3 "" H 7050 2750 60 0000 C CNN + 5 7050 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 68691BFB +P 2900 4050 +F 0 "U1" H 2950 4150 30 0000 C CNN +F 1 "PORT" H 2900 4050 30 0000 C CNN +F 2 "" H 2900 4050 60 0000 C CNN +F 3 "" H 2900 4050 60 0000 C CNN + 3 2900 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68691C28 +P 2150 3350 +F 0 "U1" H 2200 3450 30 0000 C CNN +F 1 "PORT" H 2150 3350 30 0000 C CNN +F 2 "" H 2150 3350 60 0000 C CNN +F 3 "" H 2150 3350 60 0000 C CNN + 2 2150 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68691C55 +P 2900 2700 +F 0 "U1" H 2950 2800 30 0000 C CNN +F 1 "PORT" H 2900 2700 30 0000 C CNN +F 2 "" H 2900 2700 60 0000 C CNN +F 3 "" H 2900 2700 60 0000 C CNN + 1 2900 2700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.sub b/library/SubcircuitLibrary/SN54L98/SR_FF1.sub new file mode 100644 index 000000000..97dd47178 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.sub @@ -0,0 +1,22 @@ +* Subcircuit SR_FF +.subckt SR_FF net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand +* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4 +a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SR_FF \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/SR_FF1_Previous_Values.xml new file mode 100644 index 000000000..d73809c15 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/SR_FF1_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_nandd_nand \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54L98/analysis b/library/SubcircuitLibrary/SN54L98/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN54L98/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74177/SN74177-cache.lib b/library/SubcircuitLibrary/SN74177/SN74177-cache.lib new file mode 100644 index 000000000..527395529 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177-cache.lib @@ -0,0 +1,110 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# tff_1 +# +DEF tff_1 X 0 40 Y Y 1 F N +F0 "X" -500 -600 60 H V C CNN +F1 "tff_1" -500 -500 60 H V C CNN +F2 "" -500 -600 60 H I C CNN +F3 "" -500 -600 60 H I C CNN +DRAW +S -250 200 200 -500 0 1 0 N +X T 1 -450 50 200 R 50 50 1 1 I +X CLK 2 -450 -200 200 R 50 50 1 1 I +X CLR 3 0 -700 200 U 50 50 1 1 I +X QBar 4 400 -200 200 L 50 50 1 1 O +X Q 5 400 50 200 L 50 50 1 1 O +X Set 6 0 400 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74177/SN74177-rescue.lib b/library/SubcircuitLibrary/SN74177/SN74177-rescue.lib new file mode 100644 index 000000000..c6c3ec84c --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# tff-RESCUE-SN74177 +# +DEF tff-RESCUE-SN74177 X 0 40 Y Y 1 F N +F0 "X" -300 -450 39 H V C CNN +F1 "tff-RESCUE-SN74177" -300 -400 39 H V C CNN +F2 "" -300 -450 60 H I C CNN +F3 "" -300 -450 60 H I C CNN +DRAW +S -150 100 150 -400 0 1 0 N +X T 1 -350 0 200 R 50 39 1 1 I +X CLK 2 -350 -200 200 R 50 33 1 1 I +X CLR 3 0 -600 200 U 50 33 1 1 I +X QBar 4 350 -200 200 L 50 33 1 1 O +X Preset 5 0 300 200 D 50 33 1 1 I +X Q 5 350 0 200 L 50 33 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74177/SN74177.cir b/library/SubcircuitLibrary/SN74177/SN74177.cir new file mode 100644 index 000000000..13f72a3ae --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177.cir @@ -0,0 +1,29 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74177\SN74177.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 09:20:10 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U16-Pad3_ Net-_U14-Pad2_ Net-_U6-Pad3_ d_nand +U7 Net-_U17-Pad3_ Net-_U14-Pad2_ Net-_U7-Pad3_ d_nand +U8 Net-_U19-Pad3_ Net-_U14-Pad2_ Net-_U8-Pad3_ d_nand +U9 Net-_U18-Pad3_ Net-_U14-Pad2_ Net-_U9-Pad3_ d_nand +U2 /13 Net-_U16-Pad2_ d_buffer +U3 /1 /13 Net-_U14-Pad2_ d_nand +U1 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? PORT +U4 /4 Net-_U14-Pad2_ Net-_U16-Pad1_ d_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nand +U5 /10 Net-_U14-Pad2_ Net-_U17-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_U16-Pad2_ Net-_U17-Pad3_ d_nand +U15 /3 Net-_U14-Pad2_ Net-_U15-Pad3_ d_and +U19 Net-_U15-Pad3_ Net-_U16-Pad2_ Net-_U19-Pad3_ d_nand +U14 /11 Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U18 Net-_U14-Pad3_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_nand +X1 ? /8 Net-_U6-Pad3_ ? /5 Net-_U16-Pad3_ tff_1 +X4 ? /2 Net-_U9-Pad3_ ? /12 Net-_U18-Pad3_ tff_1 +X3 ? /9 Net-_U8-Pad3_ ? /2 Net-_U19-Pad3_ tff_1 +X2 ? /6 Net-_U7-Pad3_ ? /9 Net-_U17-Pad3_ tff_1 + +.end diff --git a/library/SubcircuitLibrary/SN74177/SN74177.cir.out b/library/SubcircuitLibrary/SN74177/SN74177.cir.out new file mode 100644 index 000000000..a6231dae6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177.cir.out @@ -0,0 +1,73 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74177\sn74177.cir + +.include tff_1.sub +* u6 net-_u16-pad3_ net-_u14-pad2_ net-_u6-pad3_ d_nand +* u7 net-_u17-pad3_ net-_u14-pad2_ net-_u7-pad3_ d_nand +* u8 net-_u19-pad3_ net-_u14-pad2_ net-_u8-pad3_ d_nand +* u9 net-_u18-pad3_ net-_u14-pad2_ net-_u9-pad3_ d_nand +* u2 /13 net-_u16-pad2_ d_buffer +* u3 /1 /13 net-_u14-pad2_ d_nand +* u1 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? port +* u4 /4 net-_u14-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u5 /10 net-_u14-pad2_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u15 /3 net-_u14-pad2_ net-_u15-pad3_ d_and +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u14 /11 net-_u14-pad2_ net-_u14-pad3_ d_and +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +x1 ? /8 net-_u6-pad3_ ? /5 net-_u16-pad3_ tff_1 +x4 ? /2 net-_u9-pad3_ ? /12 net-_u18-pad3_ tff_1 +x3 ? /9 net-_u8-pad3_ ? /2 net-_u19-pad3_ tff_1 +x2 ? /6 net-_u7-pad3_ ? /9 net-_u17-pad3_ tff_1 +a1 [net-_u16-pad3_ net-_u14-pad2_ ] net-_u6-pad3_ u6 +a2 [net-_u17-pad3_ net-_u14-pad2_ ] net-_u7-pad3_ u7 +a3 [net-_u19-pad3_ net-_u14-pad2_ ] net-_u8-pad3_ u8 +a4 [net-_u18-pad3_ net-_u14-pad2_ ] net-_u9-pad3_ u9 +a5 /13 net-_u16-pad2_ u2 +a6 [/1 /13 ] net-_u14-pad2_ u3 +a7 [/4 net-_u14-pad2_ ] net-_u16-pad1_ u4 +a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [/10 net-_u14-pad2_ ] net-_u17-pad1_ u5 +a10 [net-_u17-pad1_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a11 [/3 net-_u14-pad2_ ] net-_u15-pad3_ u15 +a12 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a13 [/11 net-_u14-pad2_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74177/SN74177.pro b/library/SubcircuitLibrary/SN74177/SN74177.pro new file mode 100644 index 000000000..933444565 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177.pro @@ -0,0 +1,74 @@ +update=06/17/25 10:45:53 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=SN74177-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=eSim_Plot +LibName24=transistors +LibName25=conn +LibName26=eSim_User +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_Nghdl +LibName39=eSim_Ngveri +LibName40=eSim_SKY130 +LibName41=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74177/SN74177.sch b/library/SubcircuitLibrary/SN74177/SN74177.sch new file mode 100644 index 000000000..1d5c854c6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177.sch @@ -0,0 +1,716 @@ +EESchema Schematic File Version 2 +LIBS:SN74177-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74177-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U6 +U 1 1 6849445D +P 9050 2800 +F 0 "U6" H 9050 2800 60 0000 C CNN +F 1 "d_nand" H 9100 2900 60 0000 C CNN +F 2 "" H 9050 2800 60 0000 C CNN +F 3 "" H 9050 2800 60 0000 C CNN + 1 9050 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 6849452A +P 9050 4350 +F 0 "U7" H 9050 4350 60 0000 C CNN +F 1 "d_nand" H 9100 4450 60 0000 C CNN +F 2 "" H 9050 4350 60 0000 C CNN +F 3 "" H 9050 4350 60 0000 C CNN + 1 9050 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 68494579 +P 9100 5900 +F 0 "U8" H 9100 5900 60 0000 C CNN +F 1 "d_nand" H 9150 6000 60 0000 C CNN +F 2 "" H 9100 5900 60 0000 C CNN +F 3 "" H 9100 5900 60 0000 C CNN + 1 9100 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U9 +U 1 1 684945BE +P 9150 7600 +F 0 "U9" H 9150 7600 60 0000 C CNN +F 1 "d_nand" H 9200 7700 60 0000 C CNN +F 2 "" H 9150 7600 60 0000 C CNN +F 3 "" H 9150 7600 60 0000 C CNN + 1 9150 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U2 +U 1 1 6849849D +P 4150 2400 +F 0 "U2" H 4150 2350 60 0000 C CNN +F 1 "d_buffer" H 4150 2450 60 0000 C CNN +F 2 "" H 4150 2400 60 0000 C CNN +F 3 "" H 4150 2400 60 0000 C CNN + 1 4150 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 6849882C +P 4700 1750 +F 0 "U3" H 4700 1750 60 0000 C CNN +F 1 "d_nand" H 4750 1850 60 0000 C CNN +F 2 "" H 4700 1750 60 0000 C CNN +F 3 "" H 4700 1750 60 0000 C CNN + 1 4700 1750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 1700 10650 1700 +Wire Wire Line + 10650 1700 10650 1750 +Wire Wire Line + 7600 3150 10650 3150 +Wire Wire Line + 10650 3150 10650 3350 +Wire Wire Line + 7600 4550 10650 4550 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8650 5900 +Connection ~ 5950 5750 +Wire Wire Line + 8650 5800 8100 5800 +Wire Wire Line + 8100 5800 8100 4550 +Connection ~ 8100 4550 +Wire Wire Line + 5950 4250 8100 4250 +Wire Wire Line + 8100 4250 8100 4350 +Wire Wire Line + 8100 4350 8600 4350 +Connection ~ 5950 4250 +Wire Wire Line + 8600 4250 8250 4250 +Wire Wire Line + 8250 4250 8250 3150 +Connection ~ 8250 3150 +Wire Wire Line + 8600 2800 6900 2800 +Wire Wire Line + 6900 2800 6900 2550 +Wire Wire Line + 6900 2550 5950 2550 +Connection ~ 5950 2550 +Wire Wire Line + 6400 1850 5550 1850 +Wire Wire Line + 5550 1850 5550 6200 +Wire Wire Line + 5550 3300 6400 3300 +Wire Wire Line + 5550 4700 6450 4700 +Connection ~ 5550 3300 +Wire Wire Line + 5550 6200 6400 6200 +Connection ~ 5550 4700 +Wire Wire Line + 6400 1550 5650 1550 +Wire Wire Line + 5550 2400 4800 2400 +Connection ~ 5550 2400 +Wire Wire Line + 3450 2400 3650 2400 +Wire Wire Line + 3550 2400 3550 1750 +Wire Wire Line + 3550 1750 4250 1750 +Connection ~ 3550 2400 +Wire Wire Line + 4250 1650 3350 1650 +Wire Wire Line + 5150 1700 5150 2050 +Wire Wire Line + 5150 2050 5950 2050 +Connection ~ 5950 2050 +Wire Wire Line + 5300 3000 6500 3000 +Wire Wire Line + 5350 4400 6550 4400 +Wire Wire Line + 5400 5900 6500 5900 +Wire Wire Line + 10100 4150 10100 3700 +Wire Wire Line + 10100 3700 7750 3700 +Wire Wire Line + 11100 3500 11800 3500 +Wire Wire Line + 11050 2100 11850 2100 +Wire Wire Line + 11650 3500 11650 4500 +Wire Wire Line + 11650 4500 9750 4500 +Wire Wire Line + 9750 4500 9750 5550 +Wire Wire Line + 9750 5550 10100 5550 +Connection ~ 11650 3500 +Wire Wire Line + 11100 4900 11800 4900 +Wire Wire Line + 11650 4900 11650 6000 +Wire Wire Line + 11650 6000 9650 6000 +Wire Wire Line + 9650 6000 9650 7050 +Wire Wire Line + 9650 7050 10100 7050 +Connection ~ 11650 4900 +Wire Wire Line + 11050 6400 11950 6400 +Text Label 5650 1550 0 60 ~ 0 +4 +Text Label 3350 1650 0 60 ~ 0 +1 +Text Label 3450 2400 0 60 ~ 0 +13 +Text Label 7450 2150 0 60 ~ 0 +8 +Text Label 5300 3000 0 60 ~ 0 +10 +Text Label 7750 3700 0 60 ~ 0 +6 +Text Label 5350 4400 0 60 ~ 0 +3 +Text Label 5400 5900 0 60 ~ 0 +11 +Text Label 11850 2100 0 60 ~ 0 +5 +Text Label 11800 3500 0 60 ~ 0 +9 +Text Label 11800 4900 0 60 ~ 0 +2 +Text Label 11950 6400 0 60 ~ 0 +12 +NoConn ~ 11000 2250 +$Comp +L PORT U1 +U 3 1 6849FC73 +P 5100 4400 +F 0 "U1" H 5150 4500 30 0000 C CNN +F 1 "PORT" H 5100 4400 30 0000 C CNN +F 2 "" H 5100 4400 60 0000 C CNN +F 3 "" H 5100 4400 60 0000 C CNN + 3 5100 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6849FCA6 +P 3100 1650 +F 0 "U1" H 3150 1750 30 0000 C CNN +F 1 "PORT" H 3100 1650 30 0000 C CNN +F 2 "" H 3100 1650 60 0000 C CNN +F 3 "" H 3100 1650 60 0000 C CNN + 1 3100 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6849FCDB +P 12050 4900 +F 0 "U1" H 12100 5000 30 0000 C CNN +F 1 "PORT" H 12050 4900 30 0000 C CNN +F 2 "" H 12050 4900 60 0000 C CNN +F 3 "" H 12050 4900 60 0000 C CNN + 2 12050 4900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6849FD18 +P 5400 1550 +F 0 "U1" H 5450 1650 30 0000 C CNN +F 1 "PORT" H 5400 1550 30 0000 C CNN +F 2 "" H 5400 1550 60 0000 C CNN +F 3 "" H 5400 1550 60 0000 C CNN + 4 5400 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6849FD51 +P 12100 2100 +F 0 "U1" H 12150 2200 30 0000 C CNN +F 1 "PORT" H 12100 2100 30 0000 C CNN +F 2 "" H 12100 2100 60 0000 C CNN +F 3 "" H 12100 2100 60 0000 C CNN + 5 12100 2100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 6849FD94 +P 7500 3700 +F 0 "U1" H 7550 3800 30 0000 C CNN +F 1 "PORT" H 7500 3700 30 0000 C CNN +F 2 "" H 7500 3700 60 0000 C CNN +F 3 "" H 7500 3700 60 0000 C CNN + 6 7500 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6849FDD1 +P 3900 4200 +F 0 "U1" H 3950 4300 30 0000 C CNN +F 1 "PORT" H 3900 4200 30 0000 C CNN +F 2 "" H 3900 4200 60 0000 C CNN +F 3 "" H 3900 4200 60 0000 C CNN + 7 3900 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6849FE10 +P 7200 2150 +F 0 "U1" H 7250 2250 30 0000 C CNN +F 1 "PORT" H 7200 2150 30 0000 C CNN +F 2 "" H 7200 2150 60 0000 C CNN +F 3 "" H 7200 2150 60 0000 C CNN + 8 7200 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6849FE53 +P 12050 3500 +F 0 "U1" H 12100 3600 30 0000 C CNN +F 1 "PORT" H 12050 3500 30 0000 C CNN +F 2 "" H 12050 3500 60 0000 C CNN +F 3 "" H 12050 3500 60 0000 C CNN + 9 12050 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6849FE96 +P 5050 3000 +F 0 "U1" H 5100 3100 30 0000 C CNN +F 1 "PORT" H 5050 3000 30 0000 C CNN +F 2 "" H 5050 3000 60 0000 C CNN +F 3 "" H 5050 3000 60 0000 C CNN + 10 5050 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6849FEDB +P 5150 5900 +F 0 "U1" H 5200 6000 30 0000 C CNN +F 1 "PORT" H 5150 5900 30 0000 C CNN +F 2 "" H 5150 5900 60 0000 C CNN +F 3 "" H 5150 5900 60 0000 C CNN + 11 5150 5900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6849FF48 +P 12200 6400 +F 0 "U1" H 12250 6500 30 0000 C CNN +F 1 "PORT" H 12200 6400 30 0000 C CNN +F 2 "" H 12200 6400 60 0000 C CNN +F 3 "" H 12200 6400 60 0000 C CNN + 12 12200 6400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6849FF91 +P 3200 2400 +F 0 "U1" H 3250 2500 30 0000 C CNN +F 1 "PORT" H 3200 2400 30 0000 C CNN +F 2 "" H 3200 2400 60 0000 C CNN +F 3 "" H 3200 2400 60 0000 C CNN + 13 3200 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6849FFDC +P 3900 4450 +F 0 "U1" H 3950 4550 30 0000 C CNN +F 1 "PORT" H 3900 4450 30 0000 C CNN +F 2 "" H 3900 4450 60 0000 C CNN +F 3 "" H 3900 4450 60 0000 C CNN + 14 3900 4450 + 1 0 0 -1 +$EndComp +NoConn ~ 4150 4450 +NoConn ~ 4150 4200 +$Comp +L d_and U4 +U 1 1 684AB3EF +P 6850 1650 +F 0 "U4" H 6850 1650 60 0000 C CNN +F 1 "d_and" H 6900 1750 60 0000 C CNN +F 2 "" H 6850 1650 60 0000 C CNN +F 3 "" H 6850 1650 60 0000 C CNN + 1 6850 1650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 684AB4DB +P 7200 1950 +F 0 "U16" H 7200 1950 60 0000 C CNN +F 1 "d_nand" H 7250 2050 60 0000 C CNN +F 2 "" H 7200 1950 60 0000 C CNN +F 3 "" H 7200 1950 60 0000 C CNN + 1 7200 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 1600 7300 1750 +Wire Wire Line + 7300 1750 6600 1750 +Wire Wire Line + 6600 1750 6600 1850 +Wire Wire Line + 6600 1850 6750 1850 +Wire Wire Line + 6400 1850 6400 1950 +Wire Wire Line + 6400 1950 6750 1950 +Wire Wire Line + 7650 1900 7650 1800 +Wire Wire Line + 7650 1800 7500 1800 +Wire Wire Line + 7500 1800 7500 1700 +$Comp +L d_and U5 +U 1 1 684AC28B +P 6950 3100 +F 0 "U5" H 6950 3100 60 0000 C CNN +F 1 "d_and" H 7000 3200 60 0000 C CNN +F 2 "" H 6950 3100 60 0000 C CNN +F 3 "" H 6950 3100 60 0000 C CNN + 1 6950 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 3150 6150 3150 +Wire Wire Line + 6150 3150 6150 3100 +Wire Wire Line + 6150 3100 6500 3100 +$Comp +L d_nand U17 +U 1 1 684AC80D +P 7250 3450 +F 0 "U17" H 7250 3450 60 0000 C CNN +F 1 "d_nand" H 7300 3550 60 0000 C CNN +F 2 "" H 7250 3450 60 0000 C CNN +F 3 "" H 7250 3450 60 0000 C CNN + 1 7250 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6400 3300 6400 3450 +Wire Wire Line + 6400 3450 6800 3450 +Wire Wire Line + 7400 3050 7400 3250 +Wire Wire Line + 7400 3250 6600 3250 +Wire Wire Line + 6600 3250 6600 3350 +Wire Wire Line + 6600 3350 6800 3350 +Wire Wire Line + 7600 3150 7600 3300 +Wire Wire Line + 7600 3300 7700 3300 +Wire Wire Line + 7700 3300 7700 3400 +$Comp +L d_and U15 +U 1 1 684AD635 +P 7000 4500 +F 0 "U15" H 7000 4500 60 0000 C CNN +F 1 "d_and" H 7050 4600 60 0000 C CNN +F 2 "" H 7000 4500 60 0000 C CNN +F 3 "" H 7000 4500 60 0000 C CNN + 1 7000 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U19 +U 1 1 684AD63B +P 7300 4850 +F 0 "U19" H 7300 4850 60 0000 C CNN +F 1 "d_nand" H 7350 4950 60 0000 C CNN +F 2 "" H 7300 4850 60 0000 C CNN +F 3 "" H 7300 4850 60 0000 C CNN + 1 7300 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 4850 6850 4850 +Wire Wire Line + 7450 4650 6650 4650 +Wire Wire Line + 6650 4750 6850 4750 +Wire Wire Line + 6400 4550 6400 4500 +Wire Wire Line + 6400 4500 6550 4500 +Wire Wire Line + 7450 4450 7450 4650 +Wire Wire Line + 6650 4650 6650 4750 +Wire Wire Line + 6450 4700 6450 4850 +Wire Wire Line + 7600 4550 7600 4650 +Wire Wire Line + 7600 4650 7750 4650 +Wire Wire Line + 7750 4650 7750 4800 +$Comp +L d_and U14 +U 1 1 684AEDCD +P 6950 6000 +F 0 "U14" H 6950 6000 60 0000 C CNN +F 1 "d_and" H 7000 6100 60 0000 C CNN +F 2 "" H 6950 6000 60 0000 C CNN +F 3 "" H 6950 6000 60 0000 C CNN + 1 6950 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 684AEDD3 +P 7250 6350 +F 0 "U18" H 7250 6350 60 0000 C CNN +F 1 "d_nand" H 7300 6450 60 0000 C CNN +F 2 "" H 7250 6350 60 0000 C CNN +F 3 "" H 7250 6350 60 0000 C CNN + 1 7250 6350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7400 6150 6600 6150 +Wire Wire Line + 7400 5950 7400 6150 +Wire Wire Line + 6400 6050 6400 6000 +Wire Wire Line + 6400 6000 6500 6000 +Wire Wire Line + 6600 6150 6600 6250 +Wire Wire Line + 6600 6250 6800 6250 +Wire Wire Line + 6400 6200 6400 6350 +Wire Wire Line + 6400 6350 6800 6350 +Wire Wire Line + 7700 6300 7700 6150 +Wire Wire Line + 7700 6150 7600 6150 +Wire Wire Line + 7600 6150 7600 6050 +Wire Wire Line + 11100 3500 11100 3700 +Wire Wire Line + 10100 4150 10200 4150 +Wire Wire Line + 10200 4150 10200 3950 +Wire Wire Line + 10100 5550 10100 5300 +Wire Wire Line + 11100 4900 11100 5050 +Wire Wire Line + 10100 7050 10100 6850 +Wire Wire Line + 11050 6400 11050 6600 +$Comp +L tff_1 X? +U 1 1 687343EE +P 10650 2150 +F 0 "X?" H 10150 1550 60 0000 C CNN +F 1 "tff_1" H 10150 1650 60 0000 C CNN +F 2 "" H 10150 1550 60 0001 C CNN +F 3 "" H 10150 1550 60 0001 C CNN + 1 10650 2150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10650 3050 10650 2850 +NoConn ~ 10200 2100 +NoConn ~ 11050 2350 +Wire Wire Line + 7450 2150 9800 2150 +Wire Wire Line + 9800 2150 9800 2350 +Wire Wire Line + 9800 2350 10200 2350 +$Comp +L tff_1 X? +U 1 1 68735EDB +P 10650 6650 +F 0 "X?" H 10150 6050 60 0000 C CNN +F 1 "tff_1" H 10150 6150 60 0000 C CNN +F 2 "" H 10150 6050 60 0001 C CNN +F 3 "" H 10150 6050 60 0001 C CNN + 1 10650 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10100 6850 10200 6850 +NoConn ~ 11050 6850 +NoConn ~ 10200 6600 +$Comp +L tff_1 X? +U 1 1 6873690C +P 10650 5100 +F 0 "X?" H 10150 4500 60 0000 C CNN +F 1 "tff_1" H 10150 4600 60 0000 C CNN +F 2 "" H 10150 4500 60 0001 C CNN +F 3 "" H 10150 4500 60 0001 C CNN + 1 10650 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10650 5850 10650 5800 +Wire Wire Line + 11100 5050 11050 5050 +Wire Wire Line + 10100 5300 10200 5300 +NoConn ~ 11050 5300 +NoConn ~ 10200 5050 +$Comp +L tff_1 X? +U 1 1 687373FE +P 10650 3750 +F 0 "X?" H 10150 3150 60 0000 C CNN +F 1 "tff_1" H 10150 3250 60 0000 C CNN +F 2 "" H 10150 3150 60 0001 C CNN +F 3 "" H 10150 3150 60 0001 C CNN + 1 10650 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11100 3700 11050 3700 +NoConn ~ 11050 3950 +NoConn ~ 10200 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74177/SN74177.sub b/library/SubcircuitLibrary/SN74177/SN74177.sub new file mode 100644 index 000000000..a20eabc56 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177.sub @@ -0,0 +1,67 @@ +* Subcircuit SN74177 +.subckt SN74177 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? +* d:\fossee\esim\library\subcircuitlibrary\sn74177\sn74177.cir +.include tff_1.sub +* u6 net-_u16-pad3_ net-_u14-pad2_ net-_u6-pad3_ d_nand +* u7 net-_u17-pad3_ net-_u14-pad2_ net-_u7-pad3_ d_nand +* u8 net-_u19-pad3_ net-_u14-pad2_ net-_u8-pad3_ d_nand +* u9 net-_u18-pad3_ net-_u14-pad2_ net-_u9-pad3_ d_nand +* u2 /13 net-_u16-pad2_ d_buffer +* u3 /1 /13 net-_u14-pad2_ d_nand +* u4 /4 net-_u14-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u5 /10 net-_u14-pad2_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u15 /3 net-_u14-pad2_ net-_u15-pad3_ d_and +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u14 /11 net-_u14-pad2_ net-_u14-pad3_ d_and +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +x1 ? /8 net-_u6-pad3_ ? /5 net-_u16-pad3_ tff_1 +x4 ? /2 net-_u9-pad3_ ? /12 net-_u18-pad3_ tff_1 +x3 ? /9 net-_u8-pad3_ ? /2 net-_u19-pad3_ tff_1 +x2 ? /6 net-_u7-pad3_ ? /9 net-_u17-pad3_ tff_1 +a1 [net-_u16-pad3_ net-_u14-pad2_ ] net-_u6-pad3_ u6 +a2 [net-_u17-pad3_ net-_u14-pad2_ ] net-_u7-pad3_ u7 +a3 [net-_u19-pad3_ net-_u14-pad2_ ] net-_u8-pad3_ u8 +a4 [net-_u18-pad3_ net-_u14-pad2_ ] net-_u9-pad3_ u9 +a5 /13 net-_u16-pad2_ u2 +a6 [/1 /13 ] net-_u14-pad2_ u3 +a7 [/4 net-_u14-pad2_ ] net-_u16-pad1_ u4 +a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [/10 net-_u14-pad2_ ] net-_u17-pad1_ u5 +a10 [net-_u17-pad1_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a11 [/3 net-_u14-pad2_ ] net-_u15-pad3_ u15 +a12 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a13 [/11 net-_u14-pad2_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74177 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74177/SN74177_Previous_Values.xml b/library/SubcircuitLibrary/SN74177/SN74177_Previous_Values.xml new file mode 100644 index 000000000..3b8f93288 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/SN74177_Previous_Values.xml @@ -0,0 +1 @@ +d_tffd_tffd_tffd_tffd_nandd_nandd_nandd_nandd_bufferd_nandd_andd_nandd_andd_nandd_andd_nandd_andd_nandD:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74177/analysis b/library/SubcircuitLibrary/SN74177/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74177/tff-cache.lib b/library/SubcircuitLibrary/SN74177/tff-cache.lib new file mode 100644 index 000000000..c07ae5124 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74177/tff_1-cache.lib b/library/SubcircuitLibrary/SN74177/tff_1-cache.lib new file mode 100644 index 000000000..c07ae5124 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_1-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74177/tff_1.cir b/library/SubcircuitLibrary/SN74177/tff_1.cir new file mode 100644 index 000000000..5a146818a --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_1.cir @@ -0,0 +1,19 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1\tff_1.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 12:05:50 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and +U3 Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_and +U4 Net-_U1-Pad3_ Net-_U2-Pad4_ Net-_U4-Pad3_ d_nand +U5 Net-_U2-Pad5_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_nand +U6 Net-_U2-Pad6_ Net-_U4-Pad3_ Net-_U6-Pad3_ d_and +U7 Net-_U5-Pad3_ Net-_U2-Pad3_ Net-_U7-Pad3_ d_and +U8 Net-_U6-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ d_nand +U9 Net-_U2-Pad5_ Net-_U7-Pad3_ Net-_U2-Pad4_ d_nand +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74177/tff_1.cir.out b/library/SubcircuitLibrary/SN74177/tff_1.cir.out new file mode 100644 index 000000000..eb1d38f67 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_1.cir.out @@ -0,0 +1,44 @@ +* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and +* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and +* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand +* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4 +a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8 +a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74177/tff_1.pro b/library/SubcircuitLibrary/SN74177/tff_1.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74177/tff_1.sch b/library/SubcircuitLibrary/SN74177/tff_1.sch new file mode 100644 index 000000000..467a8221e --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_1.sch @@ -0,0 +1,299 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:tff_1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U1 +U 1 1 68510BDF +P 3350 2450 +F 0 "U1" H 3350 2450 60 0000 C CNN +F 1 "d_and" H 3400 2550 60 0000 C CNN +F 2 "" H 3350 2450 60 0000 C CNN +F 3 "" H 3350 2450 60 0000 C CNN + 1 3350 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 68510C68 +P 3400 3750 +F 0 "U3" H 3400 3750 60 0000 C CNN +F 1 "d_and" H 3450 3850 60 0000 C CNN +F 2 "" H 3400 3750 60 0000 C CNN +F 3 "" H 3400 3750 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68510CCF +P 5300 2450 +F 0 "U4" H 5300 2450 60 0000 C CNN +F 1 "d_nand" H 5350 2550 60 0000 C CNN +F 2 "" H 5300 2450 60 0000 C CNN +F 3 "" H 5300 2450 60 0000 C CNN + 1 5300 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68510D24 +P 5350 3700 +F 0 "U5" H 5350 3700 60 0000 C CNN +F 1 "d_nand" H 5400 3800 60 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 1 5350 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 2400 4600 2400 +Wire Wire Line + 4600 2400 4600 2350 +Wire Wire Line + 4600 2350 4850 2350 +Wire Wire Line + 3850 3700 4900 3700 +$Comp +L d_and U6 +U 1 1 685111F3 +P 6600 2400 +F 0 "U6" H 6600 2400 60 0000 C CNN +F 1 "d_and" H 6650 2500 60 0000 C CNN +F 2 "" H 6600 2400 60 0000 C CNN +F 3 "" H 6600 2400 60 0000 C CNN + 1 6600 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 685111F9 +P 6650 3700 +F 0 "U7" H 6650 3700 60 0000 C CNN +F 1 "d_and" H 6700 3800 60 0000 C CNN +F 2 "" H 6650 3700 60 0000 C CNN +F 3 "" H 6650 3700 60 0000 C CNN + 1 6650 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 685111FF +P 8550 2400 +F 0 "U8" H 8550 2400 60 0000 C CNN +F 1 "d_nand" H 8600 2500 60 0000 C CNN +F 2 "" H 8550 2400 60 0000 C CNN +F 3 "" H 8550 2400 60 0000 C CNN + 1 8550 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U9 +U 1 1 68511205 +P 8600 3650 +F 0 "U9" H 8600 3650 60 0000 C CNN +F 1 "d_nand" H 8650 3750 60 0000 C CNN +F 2 "" H 8600 3650 60 0000 C CNN +F 3 "" H 8600 3650 60 0000 C CNN + 1 8600 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7050 2350 7850 2350 +Wire Wire Line + 7850 2350 7850 2300 +Wire Wire Line + 7850 2300 8100 2300 +Wire Wire Line + 7100 3650 8150 3650 +Wire Wire Line + 5800 3650 5900 3650 +Wire Wire Line + 5900 3650 5900 3600 +Wire Wire Line + 5900 3600 6200 3600 +Wire Wire Line + 5750 2400 6150 2400 +Wire Wire Line + 6150 2300 5850 2300 +Wire Wire Line + 5850 2300 5850 1900 +Wire Wire Line + 6200 3700 6050 3700 +Wire Wire Line + 6050 3700 6050 4250 +Wire Wire Line + 9000 2350 9700 2350 +Wire Wire Line + 9050 3600 9900 3600 +Wire Wire Line + 9450 2350 9450 3050 +Wire Wire Line + 9450 3050 7750 3050 +Wire Wire Line + 7750 3050 7750 3550 +Wire Wire Line + 7750 3550 8150 3550 +Connection ~ 9450 2350 +Wire Wire Line + 9350 3600 9350 2700 +Wire Wire Line + 9350 2700 8000 2700 +Wire Wire Line + 8000 2700 8000 2400 +Wire Wire Line + 8000 2400 8100 2400 +Connection ~ 9350 3600 +Wire Wire Line + 7750 3200 4550 3200 +Wire Wire Line + 4550 3200 4550 3600 +Wire Wire Line + 4550 3600 4900 3600 +Connection ~ 7750 3200 +Wire Wire Line + 8000 2600 4700 2600 +Wire Wire Line + 4700 2600 4700 2450 +Wire Wire Line + 4700 2450 4850 2450 +Connection ~ 8000 2600 +Wire Wire Line + 2900 2450 2550 2450 +Wire Wire Line + 2550 2450 2550 3650 +Wire Wire Line + 2550 3650 2950 3650 +Wire Wire Line + 2550 3050 2050 3050 +Wire Wire Line + 2050 3050 2050 4200 +Connection ~ 2550 3050 +Wire Wire Line + 2900 2350 1800 2350 +Wire Wire Line + 1800 2350 1800 2300 +Wire Wire Line + 2150 2350 2150 3750 +Wire Wire Line + 2150 3750 2950 3750 +Connection ~ 2150 2350 +$Comp +L PORT U2 +U 1 1 68512107 +P 1550 2300 +F 0 "U2" H 1600 2400 30 0000 C CNN +F 1 "PORT" H 1550 2300 30 0000 C CNN +F 2 "" H 1550 2300 60 0000 C CNN +F 3 "" H 1550 2300 60 0000 C CNN + 1 1550 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 4 1 6851219B +P 9900 3850 +F 0 "U2" H 9950 3950 30 0000 C CNN +F 1 "PORT" H 9900 3850 30 0000 C CNN +F 2 "" H 9900 3850 60 0000 C CNN +F 3 "" H 9900 3850 60 0000 C CNN + 4 9900 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 5 1 685121CC +P 9700 2600 +F 0 "U2" H 9750 2700 30 0000 C CNN +F 1 "PORT" H 9700 2600 30 0000 C CNN +F 2 "" H 9700 2600 60 0000 C CNN +F 3 "" H 9700 2600 60 0000 C CNN + 5 9700 2600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 6 1 68512212 +P 5600 1900 +F 0 "U2" H 5650 2000 30 0000 C CNN +F 1 "PORT" H 5600 1900 30 0000 C CNN +F 2 "" H 5600 1900 60 0000 C CNN +F 3 "" H 5600 1900 60 0000 C CNN + 6 5600 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 2 1 68512275 +P 1800 4200 +F 0 "U2" H 1850 4300 30 0000 C CNN +F 1 "PORT" H 1800 4200 30 0000 C CNN +F 2 "" H 1800 4200 60 0000 C CNN +F 3 "" H 1800 4200 60 0000 C CNN + 2 1800 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 3 1 685122C6 +P 5800 4250 +F 0 "U2" H 5850 4350 30 0000 C CNN +F 1 "PORT" H 5800 4250 30 0000 C CNN +F 2 "" H 5800 4250 60 0000 C CNN +F 3 "" H 5800 4250 60 0000 C CNN + 3 5800 4250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74177/tff_1.sub b/library/SubcircuitLibrary/SN74177/tff_1.sub new file mode 100644 index 000000000..c7f567e0c --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_1.sub @@ -0,0 +1,38 @@ +* Subcircuit tff_1 +.subckt tff_1 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ +* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and +* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and +* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand +* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4 +a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8 +a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends tff_1 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74177/tff_1_Previous_Values.xml b/library/SubcircuitLibrary/SN74177/tff_1_Previous_Values.xml new file mode 100644 index 000000000..ab6605eb4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_1_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nandd_nandd_andd_andd_nandd_nand \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74177/tff_Previous_Values.xml b/library/SubcircuitLibrary/SN74177/tff_Previous_Values.xml new file mode 100644 index 000000000..f6a8820fd --- /dev/null +++ b/library/SubcircuitLibrary/SN74177/tff_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_andd_nandd_andd_nandd_andd_nandd_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74199/3_and-cache.lib b/library/SubcircuitLibrary/SN74199/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74199/3_and.cir b/library/SubcircuitLibrary/SN74199/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74199/3_and.cir.out b/library/SubcircuitLibrary/SN74199/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74199/3_and.pro b/library/SubcircuitLibrary/SN74199/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74199/3_and.sch b/library/SubcircuitLibrary/SN74199/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74199/3_and.sub b/library/SubcircuitLibrary/SN74199/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74199/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74199/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74199/SN74199-cache.lib b/library/SubcircuitLibrary/SN74199/SN74199-cache.lib new file mode 100644 index 000000000..51aa3e9b1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/SN74199-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_srff +# +DEF d_srff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74199/SN74199.cir b/library/SubcircuitLibrary/SN74199/SN74199.cir new file mode 100644 index 000000000..b022f897a --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/SN74199.cir @@ -0,0 +1,59 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74199\SN74199.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 22:57:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 /13 /11 Net-_U3-Pad3_ d_nor +U5 Net-_U1-Pad2_ /3 Net-_U5-Pad3_ d_and +U7 Net-_U6-Pad3_ Net-_U7-Pad2_ Net-_U36-Pad1_ d_nor +U6 Net-_U6-Pad1_ Net-_U5-Pad3_ Net-_U6-Pad3_ d_or +U2 Net-_U1-Pad2_ ? d_inverter +U1 /23 Net-_U1-Pad2_ d_inverter +X1 /1 Net-_U10-Pad2_ /4 Net-_U7-Pad2_ 3_and +U8 /4 Net-_U10-Pad2_ Net-_U22-Pad1_ d_and +U9 Net-_U1-Pad2_ /5 Net-_U22-Pad2_ d_and +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_nor +U10 /6 Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U1-Pad2_ /7 Net-_U11-Pad3_ d_and +U23 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U23-Pad3_ d_nor +U12 /8 Net-_U10-Pad2_ Net-_U12-Pad3_ d_and +U13 Net-_U1-Pad2_ /9 Net-_U13-Pad3_ d_and +U14 /10 Net-_U10-Pad2_ Net-_U14-Pad3_ d_and +U15 Net-_U1-Pad2_ /16 Net-_U15-Pad3_ d_and +U16 /15 Net-_U10-Pad2_ Net-_U16-Pad3_ d_and +U17 Net-_U1-Pad2_ /18 Net-_U17-Pad3_ d_and +U18 /17 Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U19 Net-_U1-Pad2_ /20 Net-_U19-Pad3_ d_and +U20 /19 Net-_U10-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U1-Pad2_ /22 Net-_U21-Pad3_ d_and +U24 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U24-Pad3_ d_nor +U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_nor +U26 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_nor +U27 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_nor +U28 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U28-Pad3_ d_nor +U29 Net-_U22-Pad3_ Net-_U29-Pad2_ d_inverter +U36 Net-_U36-Pad1_ ? d_inverter +U30 Net-_U23-Pad3_ Net-_U30-Pad2_ d_inverter +U31 Net-_U24-Pad3_ Net-_U31-Pad2_ d_inverter +U32 Net-_U25-Pad3_ Net-_U32-Pad2_ d_inverter +U33 Net-_U26-Pad3_ Net-_U33-Pad2_ d_inverter +U34 Net-_U27-Pad3_ Net-_U34-Pad2_ d_inverter +U42 ? Net-_U36-Pad1_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /4 Net-_U42-Pad7_ d_srff +U39 Net-_U29-Pad2_ Net-_U22-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /6 ? d_srff +U46 Net-_U30-Pad2_ Net-_U23-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /8 ? d_srff +U38 Net-_U31-Pad2_ Net-_U24-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /10 ? d_srff +U40 Net-_U33-Pad2_ Net-_U26-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /17 ? d_srff +U44 Net-_U32-Pad2_ Net-_U41-Pad2_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /15 ? d_srff +U37 Net-_U35-Pad2_ Net-_U28-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /21 ? d_srff +U35 Net-_U28-Pad3_ Net-_U35-Pad2_ d_inverter +X2 /2 Net-_U10-Pad2_ Net-_U42-Pad7_ Net-_U6-Pad1_ 3_and +U41 Net-_U32-Pad2_ Net-_U41-Pad2_ d_inverter +U45 Net-_U34-Pad2_ Net-_U43-Pad2_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /19 ? d_srff +U43 Net-_U34-Pad2_ Net-_U43-Pad2_ d_inverter +U47 /14 Net-_U37-Pad5_ d_inverter +U4 /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 ? /13 /14 /15 /16 /17 /18 /19 /20 /21 /22 /23 ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74199/SN74199.cir.out b/library/SubcircuitLibrary/SN74199/SN74199.cir.out new file mode 100644 index 000000000..0a11f23ea --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/SN74199.cir.out @@ -0,0 +1,199 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74198\sn74198.cir + +.include 3_and.sub +* u3 /13 /11 net-_u3-pad3_ d_nor +* u5 net-_u1-pad2_ /3 net-_u5-pad3_ d_and +* u7 net-_u6-pad3_ net-_u7-pad2_ net-_u36-pad1_ d_nor +* u6 net-_u6-pad1_ net-_u5-pad3_ net-_u6-pad3_ d_or +* u2 net-_u1-pad2_ ? d_inverter +* u1 /23 net-_u1-pad2_ d_inverter +x1 /1 net-_u10-pad2_ /4 net-_u7-pad2_ 3_and +* u8 /4 net-_u10-pad2_ net-_u22-pad1_ d_and +* u9 net-_u1-pad2_ /5 net-_u22-pad2_ d_and +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nor +* u10 /6 net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u1-pad2_ /7 net-_u11-pad3_ d_and +* u23 net-_u10-pad3_ net-_u11-pad3_ net-_u23-pad3_ d_nor +* u12 /8 net-_u10-pad2_ net-_u12-pad3_ d_and +* u13 net-_u1-pad2_ /9 net-_u13-pad3_ d_and +* u14 /10 net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u1-pad2_ /16 net-_u15-pad3_ d_and +* u16 /15 net-_u10-pad2_ net-_u16-pad3_ d_and +* u17 net-_u1-pad2_ /18 net-_u17-pad3_ d_and +* u18 /17 net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u1-pad2_ /20 net-_u19-pad3_ d_and +* u20 /19 net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u1-pad2_ /22 net-_u21-pad3_ d_and +* u24 net-_u12-pad3_ net-_u13-pad3_ net-_u24-pad3_ d_nor +* u25 net-_u14-pad3_ net-_u15-pad3_ net-_u25-pad3_ d_nor +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_nor +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_nor +* u28 net-_u20-pad3_ net-_u21-pad3_ net-_u28-pad3_ d_nor +* u29 net-_u22-pad3_ net-_u29-pad2_ d_inverter +* u36 net-_u36-pad1_ ? d_inverter +* u30 net-_u23-pad3_ net-_u30-pad2_ d_inverter +* u31 net-_u24-pad3_ net-_u31-pad2_ d_inverter +* u32 net-_u25-pad3_ net-_u32-pad2_ d_inverter +* u33 net-_u26-pad3_ net-_u33-pad2_ d_inverter +* u34 net-_u27-pad3_ net-_u34-pad2_ d_inverter +* u42 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ d_srff +* u39 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? d_srff +* u46 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? d_srff +* u38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? d_srff +* u40 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? d_srff +* u44 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? d_srff +* u37 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? d_srff +* u35 net-_u28-pad3_ net-_u35-pad2_ d_inverter +x2 /2 net-_u10-pad2_ net-_u42-pad7_ net-_u6-pad1_ 3_and +* u41 net-_u32-pad2_ net-_u41-pad2_ d_inverter +* u45 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? d_srff +* u43 net-_u34-pad2_ net-_u43-pad2_ d_inverter +* u47 /14 net-_u37-pad5_ d_inverter +* u4 /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 ? /13 /14 /15 /16 /17 /18 /19 /20 /21 /22 /23 ? port +a1 [/13 /11 ] net-_u3-pad3_ u3 +a2 [net-_u1-pad2_ /3 ] net-_u5-pad3_ u5 +a3 [net-_u6-pad3_ net-_u7-pad2_ ] net-_u36-pad1_ u7 +a4 [net-_u6-pad1_ net-_u5-pad3_ ] net-_u6-pad3_ u6 +a5 net-_u1-pad2_ ? u2 +a6 /23 net-_u1-pad2_ u1 +a7 [/4 net-_u10-pad2_ ] net-_u22-pad1_ u8 +a8 [net-_u1-pad2_ /5 ] net-_u22-pad2_ u9 +a9 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a10 [/6 net-_u10-pad2_ ] net-_u10-pad3_ u10 +a11 [net-_u1-pad2_ /7 ] net-_u11-pad3_ u11 +a12 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u23-pad3_ u23 +a13 [/8 net-_u10-pad2_ ] net-_u12-pad3_ u12 +a14 [net-_u1-pad2_ /9 ] net-_u13-pad3_ u13 +a15 [/10 net-_u10-pad2_ ] net-_u14-pad3_ u14 +a16 [net-_u1-pad2_ /16 ] net-_u15-pad3_ u15 +a17 [/15 net-_u10-pad2_ ] net-_u16-pad3_ u16 +a18 [net-_u1-pad2_ /18 ] net-_u17-pad3_ u17 +a19 [/17 net-_u10-pad2_ ] net-_u18-pad3_ u18 +a20 [net-_u1-pad2_ /20 ] net-_u19-pad3_ u19 +a21 [/19 net-_u10-pad2_ ] net-_u20-pad3_ u20 +a22 [net-_u1-pad2_ /22 ] net-_u21-pad3_ u21 +a23 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u24-pad3_ u24 +a24 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u25-pad3_ u25 +a25 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a26 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a27 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u28-pad3_ u28 +a28 net-_u22-pad3_ net-_u29-pad2_ u29 +a29 net-_u36-pad1_ ? u36 +a30 net-_u23-pad3_ net-_u30-pad2_ u30 +a31 net-_u24-pad3_ net-_u31-pad2_ u31 +a32 net-_u25-pad3_ net-_u32-pad2_ u32 +a33 net-_u26-pad3_ net-_u33-pad2_ u33 +a34 net-_u27-pad3_ net-_u34-pad2_ u34 +a35 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ u42 +a36 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? u39 +a37 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? u46 +a38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? u38 +a39 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? u40 +a40 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? u44 +a41 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? u37 +a42 net-_u28-pad3_ net-_u35-pad2_ u35 +a43 net-_u32-pad2_ net-_u41-pad2_ u41 +a44 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? u45 +a45 net-_u34-pad2_ net-_u43-pad2_ u43 +a46 /14 net-_u37-pad5_ u47 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u42 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u39 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u46 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u38 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u40 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u44 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u37 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u45 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74199/SN74199.pro b/library/SubcircuitLibrary/SN74199/SN74199.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/SN74199.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74199/SN74199.sch b/library/SubcircuitLibrary/SN74199/SN74199.sch new file mode 100644 index 000000000..e680b193d --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/SN74199.sch @@ -0,0 +1,1400 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74199-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr 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+ 10050 5850 10200 5850 +Connection ~ 10050 5600 +Wire Wire Line + 10800 5850 10800 5450 +Wire Wire Line + 10800 5450 10850 5450 +Wire Wire Line + 4050 6150 3900 6150 +Wire Wire Line + 3900 6150 3900 5950 +Wire Wire Line + 3900 5950 12650 5950 +Wire Wire Line + 12650 5950 12650 4600 +Wire Wire Line + 12450 4600 12850 4600 +Connection ~ 12650 4600 +Text Label 12850 4600 0 60 ~ 0 +15 +$Comp +L d_srff U45 +U 1 1 6839FD74 +P 11800 6500 +F 0 "U45" H 11800 6500 60 0000 C CNN +F 1 "d_srff" H 11850 6650 60 0000 C CNN +F 2 "" H 11800 6500 60 0000 C CNN +F 3 "" H 11800 6500 60 0000 C CNN + 1 11800 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6950 6350 7350 6350 +Wire Wire Line + 7350 6350 7350 5800 +Wire Wire Line + 7350 5800 7850 5800 +Wire Wire Line + 7850 6650 6300 6650 +Wire Wire Line + 6300 6650 6300 6350 +Connection ~ 6300 6350 +Wire Wire Line + 4050 6950 4050 6750 +Wire Wire Line + 4050 6750 9650 6750 +Wire Wire Line + 9650 6750 9650 5800 +Wire Wire Line + 9450 5800 9800 5800 +Connection ~ 9650 5800 +Text Label 9800 5800 0 60 ~ 0 +17 +Wire Wire Line + 6950 7150 6950 6900 +Wire Wire Line + 6950 6900 10100 6900 +Wire Wire Line + 10100 6100 10100 6950 +Wire Wire Line + 10100 6100 11000 6100 +$Comp +L d_inverter U43 +U 1 1 683A03BB +P 10550 6950 +F 0 "U43" H 10550 6850 60 0000 C CNN +F 1 "d_inverter" H 10550 7100 60 0000 C CNN +F 2 "" H 10600 6900 60 0000 C CNN +F 3 "" H 10600 6900 60 0000 C CNN + 1 10550 6950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10100 6950 10250 6950 +Connection ~ 10100 6900 +Wire Wire Line + 10850 6950 11000 6950 +Wire Wire Line + 4100 7700 4100 7450 +Wire Wire Line + 4100 7450 12850 7450 +Wire Wire Line + 12850 7450 12850 6100 +Wire Wire Line + 12600 6100 12950 6100 +Connection ~ 12850 6100 +Wire Wire Line + 6950 7900 6950 7200 +Wire Wire Line + 6950 7200 7150 7200 +Wire Wire Line + 6300 7900 6300 8050 +Wire Wire Line + 6300 8050 7150 8050 +Connection ~ 6300 7900 +Wire Wire Line + 8750 7200 8900 7200 +Text Label 8900 7200 0 60 ~ 0 +21 +NoConn ~ 11800 5750 +Wire Wire Line + 9950 5000 9950 6500 +Wire Wire Line + 9950 6500 11000 6500 +Connection ~ 9950 5000 +Text Label 12950 6100 0 60 ~ 0 +19 +Wire Wire Line + 9700 2900 11300 2900 +Wire Wire Line + 11300 2900 11300 2650 +Wire Wire Line + 11300 2650 11900 2650 +Wire Wire Line + 11900 2650 11900 2150 +Wire Wire Line + 11900 2150 12550 2150 +Wire Wire Line + 8650 4050 9700 4050 +Wire Wire Line + 9700 2900 9700 5550 +Connection ~ 10550 2900 +Wire Wire Line + 12000 4200 12900 4200 +Wire Wire Line + 12900 2450 12900 7300 +Wire Wire Line + 12900 2450 12350 2450 +Wire Wire Line + 12350 2450 12350 2150 +Connection ~ 12350 2150 +Wire Wire Line + 9700 5500 8500 5500 +Connection ~ 9700 4050 +Wire Wire Line + 12900 5800 11650 5800 +Connection ~ 12900 4200 +Wire Wire Line + 8650 7000 9750 7000 +Wire Wire Line + 9750 5550 9750 8400 +Wire Wire Line + 9700 5550 9750 5550 +Connection ~ 9700 5500 +Wire Wire Line + 12900 7300 11800 7300 +Connection ~ 12900 5800 +Wire Wire Line + 9750 8400 7950 8400 +Connection ~ 9750 7000 +$Comp +L d_inverter U47 +U 1 1 683BD72A +P 12550 1850 +F 0 "U47" H 12550 1750 60 0000 C CNN +F 1 "d_inverter" H 12550 2000 60 0000 C CNN +F 2 "" H 12600 1800 60 0000 C CNN +F 3 "" H 12600 1800 60 0000 C CNN + 1 12550 1850 + 0 1 1 0 +$EndComp +Wire Wire Line + 12550 1550 12550 1450 +Wire Wire Line + 12550 1450 12700 1450 +Text Label 12700 1450 0 60 ~ 0 +14 +Text Label 2850 1400 0 60 ~ 0 +13 +Text Label 2850 1500 0 60 ~ 0 +11 +Text Label 2850 1700 0 60 ~ 0 +2 +Text Label 2850 1800 0 60 ~ 0 +1 +Text Label 2500 2100 0 60 ~ 0 +23 +Text Label 2700 2450 0 60 ~ 0 +3 +Text Label 2700 3650 0 60 ~ 0 +5 +Text Label 2700 4400 0 60 ~ 0 +7 +Text Label 2700 5100 0 60 ~ 0 +9 +Text Label 2700 5800 0 60 ~ 0 +16 +Text Label 2700 6550 0 60 ~ 0 +18 +Text Label 2700 7350 0 60 ~ 0 +20 +Text Label 2700 8100 0 60 ~ 0 +22 +$Comp +L PORT U4 +U 1 1 683C1ED9 +P 2600 1800 +F 0 "U4" H 2650 1900 30 0000 C CNN +F 1 "PORT" H 2600 1800 30 0000 C CNN +F 2 "" H 2600 1800 60 0000 C CNN +F 3 "" H 2600 1800 60 0000 C CNN + 1 2600 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U4 +U 3 1 683C39FE +P 2700 2700 +F 0 "U4" H 2750 2800 30 0000 C CNN +F 1 "PORT" H 2700 2700 30 0000 C CNN +F 2 "" H 2700 2700 60 0000 C CNN +F 3 "" H 2700 2700 60 0000 C CNN + 3 2700 2700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 5 1 683C3A97 +P 2700 3400 +F 0 "U4" H 2750 3500 30 0000 C CNN +F 1 "PORT" H 2700 3400 30 0000 C CNN +F 2 "" H 2700 3400 60 0000 C CNN +F 3 "" H 2700 3400 60 0000 C CNN + 5 2700 3400 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 7 1 683C3B1E +P 2700 4150 +F 0 "U4" H 2750 4250 30 0000 C CNN +F 1 "PORT" H 2700 4150 30 0000 C CNN +F 2 "" H 2700 4150 60 0000 C CNN +F 3 "" H 2700 4150 60 0000 C CNN + 7 2700 4150 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 9 1 683C3BB7 +P 2700 4850 +F 0 "U4" H 2750 4950 30 0000 C CNN +F 1 "PORT" H 2700 4850 30 0000 C CNN +F 2 "" H 2700 4850 60 0000 C CNN +F 3 "" H 2700 4850 60 0000 C CNN + 9 2700 4850 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 11 1 683C3C46 +P 2600 1500 +F 0 "U4" H 2650 1600 30 0000 C CNN +F 1 "PORT" H 2600 1500 30 0000 C CNN +F 2 "" H 2600 1500 60 0000 C CNN +F 3 "" H 2600 1500 60 0000 C CNN + 11 2600 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U4 +U 13 1 683C3CC7 +P 2600 1400 +F 0 "U4" H 2650 1500 30 0000 C CNN +F 1 "PORT" H 2600 1400 30 0000 C CNN +F 2 "" H 2600 1400 60 0000 C CNN +F 3 "" H 2600 1400 60 0000 C CNN + 13 2600 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U4 +U 15 1 683C3D8E +P 12850 4850 +F 0 "U4" H 12900 4950 30 0000 C CNN +F 1 "PORT" H 12850 4850 30 0000 C CNN +F 2 "" H 12850 4850 60 0000 C CNN +F 3 "" H 12850 4850 60 0000 C CNN + 15 12850 4850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 17 1 683C3E29 +P 9800 6050 +F 0 "U4" H 9850 6150 30 0000 C CNN +F 1 "PORT" H 9800 6050 30 0000 C CNN +F 2 "" H 9800 6050 60 0000 C CNN +F 3 "" H 9800 6050 60 0000 C CNN + 17 9800 6050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 19 1 683C3EB8 +P 12950 6350 +F 0 "U4" H 13000 6450 30 0000 C CNN +F 1 "PORT" H 12950 6350 30 0000 C CNN +F 2 "" H 12950 6350 60 0000 C CNN +F 3 "" H 12950 6350 60 0000 C CNN + 19 12950 6350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 2 1 683C3F41 +P 2600 1700 +F 0 "U4" H 2650 1800 30 0000 C CNN +F 1 "PORT" H 2600 1700 30 0000 C CNN +F 2 "" H 2600 1700 60 0000 C CNN +F 3 "" H 2600 1700 60 0000 C CNN + 2 2600 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U4 +U 4 1 683C3FEA +P 11950 1450 +F 0 "U4" H 12000 1550 30 0000 C CNN +F 1 "PORT" H 11950 1450 30 0000 C CNN +F 2 "" H 11950 1450 60 0000 C CNN +F 3 "" H 11950 1450 60 0000 C CNN + 4 11950 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 6 1 683C7571 +P 9950 3100 +F 0 "U4" H 10000 3200 30 0000 C CNN +F 1 "PORT" H 9950 3100 30 0000 C CNN +F 2 "" H 9950 3100 60 0000 C CNN +F 3 "" H 9950 3100 60 0000 C CNN + 6 9950 3100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 8 1 683C7614 +P 13050 2500 +F 0 "U4" H 13100 2600 30 0000 C CNN +F 1 "PORT" H 13050 2500 30 0000 C CNN +F 2 "" H 13050 2500 60 0000 C CNN +F 3 "" H 13050 2500 60 0000 C CNN + 8 13050 2500 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 10 1 683C76B3 +P 9550 4550 +F 0 "U4" H 9600 4650 30 0000 C CNN +F 1 "PORT" H 9550 4550 30 0000 C CNN +F 2 "" H 9550 4550 60 0000 C CNN +F 3 "" H 9550 4550 60 0000 C CNN + 10 9550 4550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 12 1 683C7748 +P 11950 1950 +F 0 "U4" H 12000 2050 30 0000 C CNN +F 1 "PORT" H 11950 1950 30 0000 C CNN +F 2 "" H 11950 1950 60 0000 C CNN +F 3 "" H 11950 1950 60 0000 C CNN + 12 11950 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U4 +U 14 1 683C821F +P 12950 1450 +F 0 "U4" H 13000 1550 30 0000 C CNN +F 1 "PORT" H 12950 1450 30 0000 C CNN +F 2 "" H 12950 1450 60 0000 C CNN +F 3 "" H 12950 1450 60 0000 C CNN + 14 12950 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 16 1 683C82B6 +P 2700 5550 +F 0 "U4" H 2750 5650 30 0000 C CNN +F 1 "PORT" H 2700 5550 30 0000 C CNN +F 2 "" H 2700 5550 60 0000 C CNN +F 3 "" H 2700 5550 60 0000 C CNN + 16 2700 5550 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 18 1 683C834F +P 2700 6300 +F 0 "U4" H 2750 6400 30 0000 C CNN +F 1 "PORT" H 2700 6300 30 0000 C CNN +F 2 "" H 2700 6300 60 0000 C CNN +F 3 "" H 2700 6300 60 0000 C CNN + 18 2700 6300 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 20 1 683C83EA +P 2700 7100 +F 0 "U4" H 2750 7200 30 0000 C CNN +F 1 "PORT" H 2700 7100 30 0000 C CNN +F 2 "" H 2700 7100 60 0000 C CNN +F 3 "" H 2700 7100 60 0000 C CNN + 20 2700 7100 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 22 1 683C848B +P 2700 7850 +F 0 "U4" H 2750 7950 30 0000 C CNN +F 1 "PORT" H 2700 7850 30 0000 C CNN +F 2 "" H 2700 7850 60 0000 C CNN +F 3 "" H 2700 7850 60 0000 C CNN + 22 2700 7850 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 23 1 683C8536 +P 2500 2350 +F 0 "U4" H 2550 2450 30 0000 C CNN +F 1 "PORT" H 2500 2350 30 0000 C CNN +F 2 "" H 2500 2350 60 0000 C CNN +F 3 "" H 2500 2350 60 0000 C CNN + 23 2500 2350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 21 1 683C8623 +P 9150 7200 +F 0 "U4" H 9200 7300 30 0000 C CNN +F 1 "PORT" H 9150 7200 30 0000 C CNN +F 2 "" H 9150 7200 60 0000 C CNN +F 3 "" H 9150 7200 60 0000 C CNN + 21 9150 7200 + -1 0 0 1 +$EndComp +NoConn ~ 12200 1950 +$Comp +L PORT U4 +U 24 1 6834EAAC +P 12550 2250 +F 0 "U4" H 12600 2350 30 0000 C CNN +F 1 "PORT" H 12550 2250 30 0000 C CNN +F 2 "" H 12550 2250 60 0000 C CNN +F 3 "" H 12550 2250 60 0000 C CNN + 24 12550 2250 + 1 0 0 -1 +$EndComp +NoConn ~ 12800 2250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74199/SN74199.sub b/library/SubcircuitLibrary/SN74199/SN74199.sub new file mode 100644 index 000000000..ae511c800 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/SN74199.sub @@ -0,0 +1,193 @@ +* Subcircuit SN74198 +.subckt SN74198 /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 ? /13 /14 /15 /16 /17 /18 /19 /20 /21 /22 /23 ? +* d:\fossee\esim\library\subcircuitlibrary\sn74198\sn74198.cir +.include 3_and.sub +* u3 /13 /11 net-_u3-pad3_ d_nor +* u5 net-_u1-pad2_ /3 net-_u5-pad3_ d_and +* u7 net-_u6-pad3_ net-_u7-pad2_ net-_u36-pad1_ d_nor +* u6 net-_u6-pad1_ net-_u5-pad3_ net-_u6-pad3_ d_or +* u2 net-_u1-pad2_ ? d_inverter +* u1 /23 net-_u1-pad2_ d_inverter +x1 /1 net-_u10-pad2_ /4 net-_u7-pad2_ 3_and +* u8 /4 net-_u10-pad2_ net-_u22-pad1_ d_and +* u9 net-_u1-pad2_ /5 net-_u22-pad2_ d_and +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nor +* u10 /6 net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u1-pad2_ /7 net-_u11-pad3_ d_and +* u23 net-_u10-pad3_ net-_u11-pad3_ net-_u23-pad3_ d_nor +* u12 /8 net-_u10-pad2_ net-_u12-pad3_ d_and +* u13 net-_u1-pad2_ /9 net-_u13-pad3_ d_and +* u14 /10 net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u1-pad2_ /16 net-_u15-pad3_ d_and +* u16 /15 net-_u10-pad2_ net-_u16-pad3_ d_and +* u17 net-_u1-pad2_ /18 net-_u17-pad3_ d_and +* u18 /17 net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u1-pad2_ /20 net-_u19-pad3_ d_and +* u20 /19 net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u1-pad2_ /22 net-_u21-pad3_ d_and +* u24 net-_u12-pad3_ net-_u13-pad3_ net-_u24-pad3_ d_nor +* u25 net-_u14-pad3_ net-_u15-pad3_ net-_u25-pad3_ d_nor +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_nor +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_nor +* u28 net-_u20-pad3_ net-_u21-pad3_ net-_u28-pad3_ d_nor +* u29 net-_u22-pad3_ net-_u29-pad2_ d_inverter +* u36 net-_u36-pad1_ ? d_inverter +* u30 net-_u23-pad3_ net-_u30-pad2_ d_inverter +* u31 net-_u24-pad3_ net-_u31-pad2_ d_inverter +* u32 net-_u25-pad3_ net-_u32-pad2_ d_inverter +* u33 net-_u26-pad3_ net-_u33-pad2_ d_inverter +* u34 net-_u27-pad3_ net-_u34-pad2_ d_inverter +* u42 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ d_srff +* u39 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? d_srff +* u46 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? d_srff +* u38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? d_srff +* u40 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? d_srff +* u44 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? d_srff +* u37 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? d_srff +* u35 net-_u28-pad3_ net-_u35-pad2_ d_inverter +x2 /2 net-_u10-pad2_ net-_u42-pad7_ net-_u6-pad1_ 3_and +* u41 net-_u32-pad2_ net-_u41-pad2_ d_inverter +* u45 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? d_srff +* u43 net-_u34-pad2_ net-_u43-pad2_ d_inverter +* u47 /14 net-_u37-pad5_ d_inverter +a1 [/13 /11 ] net-_u3-pad3_ u3 +a2 [net-_u1-pad2_ /3 ] net-_u5-pad3_ u5 +a3 [net-_u6-pad3_ net-_u7-pad2_ ] net-_u36-pad1_ u7 +a4 [net-_u6-pad1_ net-_u5-pad3_ ] net-_u6-pad3_ u6 +a5 net-_u1-pad2_ ? u2 +a6 /23 net-_u1-pad2_ u1 +a7 [/4 net-_u10-pad2_ ] net-_u22-pad1_ u8 +a8 [net-_u1-pad2_ /5 ] net-_u22-pad2_ u9 +a9 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a10 [/6 net-_u10-pad2_ ] net-_u10-pad3_ u10 +a11 [net-_u1-pad2_ /7 ] net-_u11-pad3_ u11 +a12 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u23-pad3_ u23 +a13 [/8 net-_u10-pad2_ ] net-_u12-pad3_ u12 +a14 [net-_u1-pad2_ /9 ] net-_u13-pad3_ u13 +a15 [/10 net-_u10-pad2_ ] net-_u14-pad3_ u14 +a16 [net-_u1-pad2_ /16 ] net-_u15-pad3_ u15 +a17 [/15 net-_u10-pad2_ ] net-_u16-pad3_ u16 +a18 [net-_u1-pad2_ /18 ] net-_u17-pad3_ u17 +a19 [/17 net-_u10-pad2_ ] net-_u18-pad3_ u18 +a20 [net-_u1-pad2_ /20 ] net-_u19-pad3_ u19 +a21 [/19 net-_u10-pad2_ ] net-_u20-pad3_ u20 +a22 [net-_u1-pad2_ /22 ] net-_u21-pad3_ u21 +a23 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u24-pad3_ u24 +a24 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u25-pad3_ u25 +a25 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a26 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a27 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u28-pad3_ u28 +a28 net-_u22-pad3_ net-_u29-pad2_ u29 +a29 net-_u36-pad1_ ? u36 +a30 net-_u23-pad3_ net-_u30-pad2_ u30 +a31 net-_u24-pad3_ net-_u31-pad2_ u31 +a32 net-_u25-pad3_ net-_u32-pad2_ u32 +a33 net-_u26-pad3_ net-_u33-pad2_ u33 +a34 net-_u27-pad3_ net-_u34-pad2_ u34 +a35 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ u42 +a36 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? u39 +a37 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? u46 +a38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? u38 +a39 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? u40 +a40 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? u44 +a41 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? u37 +a42 net-_u28-pad3_ net-_u35-pad2_ u35 +a43 net-_u32-pad2_ net-_u41-pad2_ u41 +a44 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? u45 +a45 net-_u34-pad2_ net-_u43-pad2_ u43 +a46 /14 net-_u37-pad5_ u47 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u42 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u39 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u46 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u38 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u40 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u44 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u37 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u45 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74198 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74199/SN74199_Previous_Values.xml b/library/SubcircuitLibrary/SN74199/SN74199_Previous_Values.xml new file mode 100644 index 000000000..24ef83e14 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/SN74199_Previous_Values.xml @@ -0,0 +1 @@ +d_nord_andd_nord_ord_inverterd_inverterd_andd_andd_nord_andd_andd_nord_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_nord_nord_nord_nord_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_srffd_srffd_srffd_srffd_srffd_srffd_srffd_inverterd_inverterd_srffd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74199/analysis b/library/SubcircuitLibrary/SN74199/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74199/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1-cache.lib b/library/SubcircuitLibrary/SN74278_1/SN74278_1-cache.lib new file mode 100644 index 000000000..3e8d471c7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir new file mode 100644 index 000000000..eae044b5f --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir @@ -0,0 +1,45 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74278_1\SN74278_1.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 08:52:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ /1 Net-_U3-Pad3_ d_and +U9 /3 /1 Net-_U8-Pad1_ d_and +U13 Net-_U13-Pad1_ /1 Net-_U13-Pad3_ d_and +U18 /2 /1 Net-_U17-Pad1_ d_and +U22 Net-_U22-Pad1_ /1 Net-_U22-Pad3_ d_and +U28 /13 /1 Net-_U26-Pad1_ d_and +U29 Net-_U29-Pad1_ /1 Net-_U29-Pad3_ d_and +U34 /12 /1 Net-_U33-Pad1_ d_and +U7 /3 Net-_U3-Pad1_ d_inverter +U16 /2 Net-_U13-Pad1_ d_inverter +U31 /12 Net-_U29-Pad1_ d_inverter +U25 /13 Net-_U22-Pad1_ d_inverter +U5 Net-_U11-Pad2_ Net-_U3-Pad3_ Net-_U2-Pad2_ d_nor +U8 Net-_U8-Pad1_ Net-_U2-Pad2_ Net-_U11-Pad2_ d_nor +U15 Net-_U15-Pad1_ Net-_U13-Pad3_ Net-_U11-Pad1_ d_nor +U17 Net-_U17-Pad1_ Net-_U11-Pad1_ Net-_U15-Pad1_ d_nor +U24 Net-_U24-Pad1_ Net-_U22-Pad3_ Net-_U14-Pad2_ d_nor +U26 Net-_U26-Pad1_ Net-_U14-Pad2_ Net-_U24-Pad1_ d_nor +U30 Net-_U30-Pad1_ Net-_U29-Pad3_ Net-_U14-Pad1_ d_nor +U33 Net-_U33-Pad1_ Net-_U14-Pad1_ Net-_U30-Pad1_ d_nor +U32 Net-_U30-Pad1_ /4 /10 d_nor +U12 Net-_U12-Pad1_ Net-_U11-Pad3_ Net-_U10-Pad1_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U12-Pad1_ d_or +U4 Net-_U4-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad1_ d_or +U2 Net-_U11-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_or +U6 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U4-Pad1_ d_or +U1 Net-_U1-Pad1_ /4 /5 d_or +U10 Net-_U10-Pad1_ /4 /6 d_nor +U20 Net-_U20-Pad1_ Net-_U19-Pad3_ /8 d_nor +U19 Net-_U15-Pad1_ /4 Net-_U19-Pad3_ d_or +U21 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U20-Pad1_ d_or +U23 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 ? /12 /13 ? PORT +U35 Net-_U14-Pad1_ Net-_U24-Pad1_ Net-_U27-Pad1_ d_or +U27 Net-_U27-Pad1_ /4 /9 d_nor + +.end diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir.out b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir.out new file mode 100644 index 000000000..372b6a953 --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir.out @@ -0,0 +1,148 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74278_1\sn74278_1.cir + +* u3 net-_u3-pad1_ /1 net-_u3-pad3_ d_and +* u9 /3 /1 net-_u8-pad1_ d_and +* u13 net-_u13-pad1_ /1 net-_u13-pad3_ d_and +* u18 /2 /1 net-_u17-pad1_ d_and +* u22 net-_u22-pad1_ /1 net-_u22-pad3_ d_and +* u28 /13 /1 net-_u26-pad1_ d_and +* u29 net-_u29-pad1_ /1 net-_u29-pad3_ d_and +* u34 /12 /1 net-_u33-pad1_ d_and +* u7 /3 net-_u3-pad1_ d_inverter +* u16 /2 net-_u13-pad1_ d_inverter +* u31 /12 net-_u29-pad1_ d_inverter +* u25 /13 net-_u22-pad1_ d_inverter +* u5 net-_u11-pad2_ net-_u3-pad3_ net-_u2-pad2_ d_nor +* u8 net-_u8-pad1_ net-_u2-pad2_ net-_u11-pad2_ d_nor +* u15 net-_u15-pad1_ net-_u13-pad3_ net-_u11-pad1_ d_nor +* u17 net-_u17-pad1_ net-_u11-pad1_ net-_u15-pad1_ d_nor +* u24 net-_u24-pad1_ net-_u22-pad3_ net-_u14-pad2_ d_nor +* u26 net-_u26-pad1_ net-_u14-pad2_ net-_u24-pad1_ d_nor +* u30 net-_u30-pad1_ net-_u29-pad3_ net-_u14-pad1_ d_nor +* u33 net-_u33-pad1_ net-_u14-pad1_ net-_u30-pad1_ d_nor +* u32 net-_u30-pad1_ /4 /10 d_nor +* u12 net-_u12-pad1_ net-_u11-pad3_ net-_u10-pad1_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u12-pad1_ d_or +* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad1_ d_or +* u2 net-_u11-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +* u6 net-_u14-pad1_ net-_u14-pad2_ net-_u4-pad1_ d_or +* u1 net-_u1-pad1_ /4 /5 d_or +* u10 net-_u10-pad1_ /4 /6 d_nor +* u20 net-_u20-pad1_ net-_u19-pad3_ /8 d_nor +* u19 net-_u15-pad1_ /4 net-_u19-pad3_ d_or +* u21 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad1_ d_or +* u23 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 ? /12 /13 ? port +* u35 net-_u14-pad1_ net-_u24-pad1_ net-_u27-pad1_ d_or +* u27 net-_u27-pad1_ /4 /9 d_nor +a1 [net-_u3-pad1_ /1 ] net-_u3-pad3_ u3 +a2 [/3 /1 ] net-_u8-pad1_ u9 +a3 [net-_u13-pad1_ /1 ] net-_u13-pad3_ u13 +a4 [/2 /1 ] net-_u17-pad1_ u18 +a5 [net-_u22-pad1_ /1 ] net-_u22-pad3_ u22 +a6 [/13 /1 ] net-_u26-pad1_ u28 +a7 [net-_u29-pad1_ /1 ] net-_u29-pad3_ u29 +a8 [/12 /1 ] net-_u33-pad1_ u34 +a9 /3 net-_u3-pad1_ u7 +a10 /2 net-_u13-pad1_ u16 +a11 /12 net-_u29-pad1_ u31 +a12 /13 net-_u22-pad1_ u25 +a13 [net-_u11-pad2_ net-_u3-pad3_ ] net-_u2-pad2_ u5 +a14 [net-_u8-pad1_ net-_u2-pad2_ ] net-_u11-pad2_ u8 +a15 [net-_u15-pad1_ net-_u13-pad3_ ] net-_u11-pad1_ u15 +a16 [net-_u17-pad1_ net-_u11-pad1_ ] net-_u15-pad1_ u17 +a17 [net-_u24-pad1_ net-_u22-pad3_ ] net-_u14-pad2_ u24 +a18 [net-_u26-pad1_ net-_u14-pad2_ ] net-_u24-pad1_ u26 +a19 [net-_u30-pad1_ net-_u29-pad3_ ] net-_u14-pad1_ u30 +a20 [net-_u33-pad1_ net-_u14-pad1_ ] net-_u30-pad1_ u33 +a21 [net-_u30-pad1_ /4 ] /10 u32 +a22 [net-_u12-pad1_ net-_u11-pad3_ ] net-_u10-pad1_ u12 +a23 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a24 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u12-pad1_ u14 +a25 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad1_ u4 +a26 [net-_u11-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u4-pad1_ u6 +a28 [net-_u1-pad1_ /4 ] /5 u1 +a29 [net-_u10-pad1_ /4 ] /6 u10 +a30 [net-_u20-pad1_ net-_u19-pad3_ ] /8 u20 +a31 [net-_u15-pad1_ /4 ] net-_u19-pad3_ u19 +a32 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad1_ u21 +a33 [net-_u14-pad1_ net-_u24-pad1_ ] net-_u27-pad1_ u35 +a34 [net-_u27-pad1_ /4 ] /9 u27 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u1 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.pro b/library/SubcircuitLibrary/SN74278_1/SN74278_1.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.sch b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sch new file mode 100644 index 000000000..ee1081b74 --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sch @@ -0,0 +1,909 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74278_1-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U3 +U 1 1 6832A9C3 +P 3750 2750 +F 0 "U3" H 3750 2750 60 0000 C CNN +F 1 "d_and" H 3800 2850 60 0000 C CNN +F 2 "" H 3750 2750 60 0000 C CNN +F 3 "" H 3750 2750 60 0000 C CNN + 1 3750 2750 + 0 1 1 0 +$EndComp +$Comp +L d_and U9 +U 1 1 6832AA54 +P 5200 2750 +F 0 "U9" H 5200 2750 60 0000 C CNN +F 1 "d_and" H 5250 2850 60 0000 C CNN +F 2 "" H 5200 2750 60 0000 C CNN +F 3 "" H 5200 2750 60 0000 C CNN + 1 5200 2750 + 0 1 1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 6832AB57 +P 6250 2750 +F 0 "U13" H 6250 2750 60 0000 C CNN +F 1 "d_and" H 6300 2850 60 0000 C CNN +F 2 "" H 6250 2750 60 0000 C CNN +F 3 "" H 6250 2750 60 0000 C CNN + 1 6250 2750 + 0 1 1 0 +$EndComp +$Comp +L d_and U18 +U 1 1 6832AB5D +P 7700 2750 +F 0 "U18" H 7700 2750 60 0000 C CNN +F 1 "d_and" H 7750 2850 60 0000 C CNN +F 2 "" H 7700 2750 60 0000 C CNN +F 3 "" H 7700 2750 60 0000 C CNN + 1 7700 2750 + 0 1 1 0 +$EndComp +$Comp +L d_and U22 +U 1 1 6832AC9F +P 8950 2750 +F 0 "U22" H 8950 2750 60 0000 C CNN +F 1 "d_and" H 9000 2850 60 0000 C CNN +F 2 "" H 8950 2750 60 0000 C CNN +F 3 "" H 8950 2750 60 0000 C CNN + 1 8950 2750 + 0 1 1 0 +$EndComp +$Comp +L d_and U28 +U 1 1 6832ACA5 +P 10400 2750 +F 0 "U28" H 10400 2750 60 0000 C CNN +F 1 "d_and" H 10450 2850 60 0000 C CNN +F 2 "" H 10400 2750 60 0000 C CNN +F 3 "" H 10400 2750 60 0000 C CNN + 1 10400 2750 + 0 1 1 0 +$EndComp +$Comp +L d_and U29 +U 1 1 6832ACAB +P 11450 2750 +F 0 "U29" H 11450 2750 60 0000 C CNN +F 1 "d_and" H 11500 2850 60 0000 C CNN +F 2 "" H 11450 2750 60 0000 C CNN +F 3 "" H 11450 2750 60 0000 C CNN + 1 11450 2750 + 0 1 1 0 +$EndComp +$Comp +L d_and U34 +U 1 1 6832ACB1 +P 12900 2750 +F 0 "U34" H 12900 2750 60 0000 C CNN +F 1 "d_and" H 12950 2850 60 0000 C CNN +F 2 "" H 12900 2750 60 0000 C CNN +F 3 "" H 12900 2750 60 0000 C CNN + 1 12900 2750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6832B0FA +P 4450 2250 +F 0 "U7" H 4450 2150 60 0000 C CNN +F 1 "d_inverter" H 4450 2400 60 0000 C CNN +F 2 "" H 4500 2200 60 0000 C CNN +F 3 "" H 4500 2200 60 0000 C CNN + 1 4450 2250 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6832BED3 +P 6850 2150 +F 0 "U16" H 6850 2050 60 0000 C CNN +F 1 "d_inverter" H 6850 2300 60 0000 C CNN +F 2 "" H 6900 2100 60 0000 C CNN +F 3 "" H 6900 2100 60 0000 C CNN + 1 6850 2150 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U31 +U 1 1 6832BF42 +P 12150 2200 +F 0 "U31" H 12150 2100 60 0000 C CNN +F 1 "d_inverter" H 12150 2350 60 0000 C CNN +F 2 "" H 12200 2150 60 0000 C CNN +F 3 "" H 12200 2150 60 0000 C CNN + 1 12150 2200 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 6832C475 +P 9700 2150 +F 0 "U25" H 9700 2050 60 0000 C CNN +F 1 "d_inverter" H 9700 2300 60 0000 C CNN +F 2 "" H 9750 2100 60 0000 C CNN +F 3 "" H 9750 2100 60 0000 C CNN + 1 9700 2150 + -1 0 0 1 +$EndComp +$Comp +L d_nor U5 +U 1 1 6832C8C3 +P 4150 3800 +F 0 "U5" H 4150 3800 60 0000 C CNN +F 1 "d_nor" H 4200 3900 60 0000 C CNN +F 2 "" H 4150 3800 60 0000 C CNN +F 3 "" H 4150 3800 60 0000 C CNN + 1 4150 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U8 +U 1 1 6832C9B0 +P 4700 3800 +F 0 "U8" H 4700 3800 60 0000 C CNN +F 1 "d_nor" H 4750 3900 60 0000 C CNN +F 2 "" H 4700 3800 60 0000 C CNN +F 3 "" H 4700 3800 60 0000 C CNN + 1 4700 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U15 +U 1 1 6832CA6C +P 6700 3800 +F 0 "U15" H 6700 3800 60 0000 C CNN +F 1 "d_nor" H 6750 3900 60 0000 C CNN +F 2 "" H 6700 3800 60 0000 C CNN +F 3 "" H 6700 3800 60 0000 C CNN + 1 6700 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U17 +U 1 1 6832CA72 +P 7250 3800 +F 0 "U17" H 7250 3800 60 0000 C CNN +F 1 "d_nor" H 7300 3900 60 0000 C CNN +F 2 "" H 7250 3800 60 0000 C CNN +F 3 "" H 7250 3800 60 0000 C CNN + 1 7250 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U24 +U 1 1 6832CB06 +P 9450 3800 +F 0 "U24" H 9450 3800 60 0000 C CNN +F 1 "d_nor" H 9500 3900 60 0000 C CNN +F 2 "" H 9450 3800 60 0000 C CNN +F 3 "" H 9450 3800 60 0000 C CNN + 1 9450 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U26 +U 1 1 6832CB0C +P 10000 3800 +F 0 "U26" H 10000 3800 60 0000 C CNN +F 1 "d_nor" H 10050 3900 60 0000 C CNN +F 2 "" H 10000 3800 60 0000 C CNN +F 3 "" H 10000 3800 60 0000 C CNN + 1 10000 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U30 +U 1 1 6832CB94 +P 11900 3800 +F 0 "U30" H 11900 3800 60 0000 C CNN +F 1 "d_nor" H 11950 3900 60 0000 C CNN +F 2 "" H 11900 3800 60 0000 C CNN +F 3 "" H 11900 3800 60 0000 C CNN + 1 11900 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U33 +U 1 1 6832CB9A +P 12450 3800 +F 0 "U33" H 12450 3800 60 0000 C CNN +F 1 "d_nor" H 12500 3900 60 0000 C CNN +F 2 "" H 12450 3800 60 0000 C CNN +F 3 "" H 12450 3800 60 0000 C CNN + 1 12450 3800 + 0 1 1 0 +$EndComp +$Comp +L d_nor U32 +U 1 1 6832D913 +P 12400 5750 +F 0 "U32" H 12400 5750 60 0000 C CNN +F 1 "d_nor" H 12450 5850 60 0000 C CNN +F 2 "" H 12400 5750 60 0000 C CNN +F 3 "" H 12400 5750 60 0000 C CNN + 1 12400 5750 + 0 1 1 0 +$EndComp +$Comp +L d_or U12 +U 1 1 68332BBE +P 6100 7000 +F 0 "U12" H 6100 7000 60 0000 C CNN +F 1 "d_or" H 6100 7100 60 0000 C CNN +F 2 "" H 6100 7000 60 0000 C CNN +F 3 "" H 6100 7000 60 0000 C CNN + 1 6100 7000 + 0 1 1 0 +$EndComp +$Comp +L d_or U11 +U 1 1 68332CD2 +P 5700 5800 +F 0 "U11" H 5700 5800 60 0000 C CNN +F 1 "d_or" H 5700 5900 60 0000 C CNN +F 2 "" H 5700 5800 60 0000 C CNN +F 3 "" H 5700 5800 60 0000 C CNN + 1 5700 5800 + 0 1 1 0 +$EndComp +$Comp +L d_or U14 +U 1 1 68332D3D +P 6350 5800 +F 0 "U14" H 6350 5800 60 0000 C CNN +F 1 "d_or" H 6350 5900 60 0000 C CNN +F 2 "" H 6350 5800 60 0000 C CNN +F 3 "" H 6350 5800 60 0000 C CNN + 1 6350 5800 + 0 1 1 0 +$EndComp +$Comp +L d_or U4 +U 1 1 683362DD +P 4050 6950 +F 0 "U4" H 4050 6950 60 0000 C CNN +F 1 "d_or" H 4050 7050 60 0000 C CNN +F 2 "" H 4050 6950 60 0000 C CNN +F 3 "" H 4050 6950 60 0000 C CNN + 1 4050 6950 + 0 1 1 0 +$EndComp +$Comp +L d_or U2 +U 1 1 683362E3 +P 3650 5750 +F 0 "U2" H 3650 5750 60 0000 C CNN +F 1 "d_or" H 3650 5850 60 0000 C CNN +F 2 "" H 3650 5750 60 0000 C CNN +F 3 "" H 3650 5750 60 0000 C CNN + 1 3650 5750 + 0 1 1 0 +$EndComp +$Comp +L d_or U6 +U 1 1 683362E9 +P 4300 5750 +F 0 "U6" H 4300 5750 60 0000 C CNN +F 1 "d_or" H 4300 5850 60 0000 C CNN +F 2 "" H 4300 5750 60 0000 C CNN +F 3 "" H 4300 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CNN +F 2 "" H 9200 6950 60 0000 C CNN +F 3 "" H 9200 6950 60 0000 C CNN + 9 9200 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 10 1 68353952 +P 12450 6650 +F 0 "U23" H 12500 6750 30 0000 C CNN +F 1 "PORT" H 12450 6650 30 0000 C CNN +F 2 "" H 12450 6650 60 0000 C CNN +F 3 "" H 12450 6650 60 0000 C CNN + 10 12450 6650 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U23 +U 11 1 683539B7 +P 12000 1250 +F 0 "U23" H 12050 1350 30 0000 C CNN +F 1 "PORT" H 12000 1250 30 0000 C CNN +F 2 "" H 12000 1250 60 0000 C CNN +F 3 "" H 12000 1250 60 0000 C CNN + 11 12000 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 12 1 68353A1A +P 12750 1350 +F 0 "U23" H 12800 1450 30 0000 C CNN +F 1 "PORT" H 12750 1350 30 0000 C CNN +F 2 "" H 12750 1350 60 0000 C CNN +F 3 "" H 12750 1350 60 0000 C CNN + 12 12750 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 13 1 68353A83 +P 10250 1350 +F 0 "U23" H 10300 1450 30 0000 C CNN +F 1 "PORT" H 10250 1350 30 0000 C CNN +F 2 "" H 10250 1350 60 0000 C CNN +F 3 "" H 10250 1350 60 0000 C CNN + 13 10250 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 1 1 68353AEC +P 4300 1550 +F 0 "U23" H 4350 1650 30 0000 C CNN +F 1 "PORT" H 4300 1550 30 0000 C CNN +F 2 "" H 4300 1550 60 0000 C CNN +F 3 "" H 4300 1550 60 0000 C CNN + 1 4300 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 2 1 68353B71 +P 7550 1350 +F 0 "U23" H 7600 1450 30 0000 C CNN +F 1 "PORT" H 7550 1350 30 0000 C CNN +F 2 "" H 7550 1350 60 0000 C CNN +F 3 "" H 7550 1350 60 0000 C CNN + 2 7550 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 3 1 68353BDC +P 5050 1350 +F 0 "U23" H 5100 1450 30 0000 C CNN +F 1 "PORT" H 5050 1350 30 0000 C CNN +F 2 "" H 5050 1350 60 0000 C CNN +F 3 "" H 5050 1350 60 0000 C CNN + 3 5050 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 4 1 68353C4F +P 3150 1900 +F 0 "U23" H 3200 2000 30 0000 C CNN +F 1 "PORT" H 3150 1900 30 0000 C CNN +F 2 "" H 3150 1900 60 0000 C CNN +F 3 "" H 3150 1900 60 0000 C CNN + 4 3150 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U23 +U 5 1 68353CC6 +P 3900 8300 +F 0 "U23" H 3950 8400 30 0000 C CNN +F 1 "PORT" H 3900 8300 30 0000 C CNN +F 2 "" H 3900 8300 60 0000 C CNN +F 3 "" H 3900 8300 60 0000 C CNN + 5 3900 8300 + -1 0 0 1 +$EndComp +NoConn ~ 12250 1250 +NoConn ~ 11650 1250 +$Comp +L d_or U35 +U 1 1 6837FE79 +P 10100 5900 +F 0 "U35" H 10100 5900 60 0000 C CNN +F 1 "d_or" H 10100 6000 60 0000 C CNN +F 2 "" H 10100 5900 60 0000 C CNN +F 3 "" H 10100 5900 60 0000 C CNN + 1 10100 5900 + 0 1 1 0 +$EndComp +Wire Wire Line + 10050 5450 10100 5450 +$Comp +L d_nor U27 +U 1 1 68380747 +P 9550 6500 +F 0 "U27" H 9550 6500 60 0000 C CNN +F 1 "d_nor" H 9600 6600 60 0000 C CNN +F 2 "" H 9550 6500 60 0000 C CNN +F 3 "" H 9550 6500 60 0000 C CNN + 1 9550 6500 + 0 1 1 0 +$EndComp +Wire Wire Line + 10150 6350 9850 6350 +Wire Wire Line + 9850 6350 9850 6050 +Wire Wire Line + 9850 6050 9650 6050 +Wire Wire Line + 9900 5300 9900 5800 +Wire Wire Line + 9900 5800 9550 5800 +Wire Wire Line + 9550 5800 9550 6050 +$Comp +L PORT U23 +U 14 1 6838B657 +P 11850 1500 +F 0 "U23" H 11900 1600 30 0000 C CNN +F 1 "PORT" H 11850 1500 30 0000 C CNN +F 2 "" H 11850 1500 60 0000 C CNN +F 3 "" H 11850 1500 60 0000 C CNN + 14 11850 1500 + 1 0 0 -1 +$EndComp +NoConn ~ 12100 1500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.sub b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sub new file mode 100644 index 000000000..fcbcbc279 --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sub @@ -0,0 +1,142 @@ +* Subcircuit SN74278_1 +.subckt SN74278_1 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 ? /12 /13 ? +* d:\fossee\esim\library\subcircuitlibrary\sn74278_1\sn74278_1.cir +* u3 net-_u3-pad1_ /1 net-_u3-pad3_ d_and +* u9 /3 /1 net-_u8-pad1_ d_and +* u13 net-_u13-pad1_ /1 net-_u13-pad3_ d_and +* u18 /2 /1 net-_u17-pad1_ d_and +* u22 net-_u22-pad1_ /1 net-_u22-pad3_ d_and +* u28 /13 /1 net-_u26-pad1_ d_and +* u29 net-_u29-pad1_ /1 net-_u29-pad3_ d_and +* u34 /12 /1 net-_u33-pad1_ d_and +* u7 /3 net-_u3-pad1_ d_inverter +* u16 /2 net-_u13-pad1_ d_inverter +* u31 /12 net-_u29-pad1_ d_inverter +* u25 /13 net-_u22-pad1_ d_inverter +* u5 net-_u11-pad2_ net-_u3-pad3_ net-_u2-pad2_ d_nor +* u8 net-_u8-pad1_ net-_u2-pad2_ net-_u11-pad2_ d_nor +* u15 net-_u15-pad1_ net-_u13-pad3_ net-_u11-pad1_ d_nor +* u17 net-_u17-pad1_ net-_u11-pad1_ net-_u15-pad1_ d_nor +* u24 net-_u24-pad1_ net-_u22-pad3_ net-_u14-pad2_ d_nor +* u26 net-_u26-pad1_ net-_u14-pad2_ net-_u24-pad1_ d_nor +* u30 net-_u30-pad1_ net-_u29-pad3_ net-_u14-pad1_ d_nor +* u33 net-_u33-pad1_ net-_u14-pad1_ net-_u30-pad1_ d_nor +* u32 net-_u30-pad1_ /4 /10 d_nor +* u12 net-_u12-pad1_ net-_u11-pad3_ net-_u10-pad1_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u12-pad1_ d_or +* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad1_ d_or +* u2 net-_u11-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +* u6 net-_u14-pad1_ net-_u14-pad2_ net-_u4-pad1_ d_or +* u1 net-_u1-pad1_ /4 /5 d_or +* u10 net-_u10-pad1_ /4 /6 d_nor +* u20 net-_u20-pad1_ net-_u19-pad3_ /8 d_nor +* u19 net-_u15-pad1_ /4 net-_u19-pad3_ d_or +* u21 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad1_ d_or +* u35 net-_u14-pad1_ net-_u24-pad1_ net-_u27-pad1_ d_or +* u27 net-_u27-pad1_ /4 /9 d_nor +a1 [net-_u3-pad1_ /1 ] net-_u3-pad3_ u3 +a2 [/3 /1 ] net-_u8-pad1_ u9 +a3 [net-_u13-pad1_ /1 ] net-_u13-pad3_ u13 +a4 [/2 /1 ] net-_u17-pad1_ u18 +a5 [net-_u22-pad1_ /1 ] net-_u22-pad3_ u22 +a6 [/13 /1 ] net-_u26-pad1_ u28 +a7 [net-_u29-pad1_ /1 ] net-_u29-pad3_ u29 +a8 [/12 /1 ] net-_u33-pad1_ u34 +a9 /3 net-_u3-pad1_ u7 +a10 /2 net-_u13-pad1_ u16 +a11 /12 net-_u29-pad1_ u31 +a12 /13 net-_u22-pad1_ u25 +a13 [net-_u11-pad2_ net-_u3-pad3_ ] net-_u2-pad2_ u5 +a14 [net-_u8-pad1_ net-_u2-pad2_ ] net-_u11-pad2_ u8 +a15 [net-_u15-pad1_ net-_u13-pad3_ ] net-_u11-pad1_ u15 +a16 [net-_u17-pad1_ net-_u11-pad1_ ] net-_u15-pad1_ u17 +a17 [net-_u24-pad1_ net-_u22-pad3_ ] net-_u14-pad2_ u24 +a18 [net-_u26-pad1_ net-_u14-pad2_ ] net-_u24-pad1_ u26 +a19 [net-_u30-pad1_ net-_u29-pad3_ ] net-_u14-pad1_ u30 +a20 [net-_u33-pad1_ net-_u14-pad1_ ] net-_u30-pad1_ u33 +a21 [net-_u30-pad1_ /4 ] /10 u32 +a22 [net-_u12-pad1_ net-_u11-pad3_ ] net-_u10-pad1_ u12 +a23 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a24 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u12-pad1_ u14 +a25 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad1_ u4 +a26 [net-_u11-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u4-pad1_ u6 +a28 [net-_u1-pad1_ /4 ] /5 u1 +a29 [net-_u10-pad1_ /4 ] /6 u10 +a30 [net-_u20-pad1_ net-_u19-pad3_ ] /8 u20 +a31 [net-_u15-pad1_ /4 ] net-_u19-pad3_ u19 +a32 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad1_ u21 +a33 [net-_u14-pad1_ net-_u24-pad1_ ] net-_u27-pad1_ u35 +a34 [net-_u27-pad1_ /4 ] /9 u27 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u1 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74278_1 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1_Previous_Values.xml b/library/SubcircuitLibrary/SN74278_1/SN74278_1_Previous_Values.xml new file mode 100644 index 000000000..d169382b6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_andd_andd_andd_andd_andd_inverterd_inverterd_inverterd_inverterd_nord_nord_nord_nord_nord_nord_nord_nord_nord_ord_ord_ord_ord_ord_ord_ord_nord_nord_ord_ord_ord_nortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74278_1/analysis b/library/SubcircuitLibrary/SN74278_1/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74278_1/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7482/3_and-cache.lib b/library/SubcircuitLibrary/SN7482/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7482/3_and.cir b/library/SubcircuitLibrary/SN7482/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN7482/3_and.cir.out b/library/SubcircuitLibrary/SN7482/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7482/3_and.pro b/library/SubcircuitLibrary/SN7482/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN7482/3_and.sch b/library/SubcircuitLibrary/SN7482/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7482/3_and.sub b/library/SubcircuitLibrary/SN7482/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7482/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7482/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7482/SN7482-cache.lib b/library/SubcircuitLibrary/SN7482/SN7482-cache.lib new file mode 100644 index 000000000..339f033c7 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/SN7482-cache.lib @@ -0,0 +1,131 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7482/SN7482.cir b/library/SubcircuitLibrary/SN7482/SN7482.cir new file mode 100644 index 000000000..8aaed7063 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/SN7482.cir @@ -0,0 +1,38 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN7482\SN7482.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 08:56:10 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 /5 Net-_U12-Pad1_ Net-_U19-Pad1_ d_and +U4 /2 Net-_U12-Pad1_ Net-_U19-Pad2_ d_and +U5 /3 Net-_U12-Pad1_ Net-_U20-Pad1_ d_and +X1 /5 /2 /3 Net-_U20-Pad2_ 3_and +U6 /5 /2 Net-_U15-Pad1_ d_and +U7 /5 /3 Net-_U15-Pad2_ d_and +U8 /3 /2 Net-_U22-Pad2_ d_and +U9 Net-_U12-Pad1_ /10 Net-_U16-Pad1_ d_and +U10 Net-_U1-Pad2_ /10 Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ /10 Net-_U11-Pad3_ d_and +X2 Net-_U12-Pad1_ Net-_U1-Pad2_ Net-_U11-Pad1_ Net-_U17-Pad2_ 3_and +U12 Net-_U12-Pad1_ Net-_U1-Pad2_ Net-_U12-Pad3_ d_and +U13 Net-_U12-Pad1_ Net-_U11-Pad1_ Net-_U13-Pad3_ d_and +U14 Net-_U1-Pad2_ Net-_U11-Pad1_ Net-_U14-Pad3_ d_and +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_or +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_or +U24 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U24-Pad3_ d_nor +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or +U22 Net-_U15-Pad3_ Net-_U22-Pad2_ Net-_U12-Pad1_ d_nor +U16 Net-_U16-Pad1_ Net-_U10-Pad3_ Net-_U16-Pad3_ d_or +U17 Net-_U11-Pad3_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_or +U21 Net-_U16-Pad3_ Net-_U17-Pad3_ /12 d_nor +U18 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U18-Pad3_ d_or +U23 Net-_U18-Pad3_ Net-_U14-Pad3_ /10 d_nor +U25 Net-_U24-Pad3_ /1 d_inverter +U2 /13 Net-_U11-Pad1_ d_inverter +U1 /14 Net-_U1-Pad2_ d_inverter +U26 /1 /2 /3 ? /5 ? ? ? ? /10 ? /12 /13 /14 PORT + +.end diff --git a/library/SubcircuitLibrary/SN7482/SN7482.cir.out b/library/SubcircuitLibrary/SN7482/SN7482.cir.out new file mode 100644 index 000000000..a677d1c7c --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/SN7482.cir.out @@ -0,0 +1,115 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn7482\sn7482.cir + +.include 3_and.sub +* u3 /5 net-_u12-pad1_ net-_u19-pad1_ d_and +* u4 /2 net-_u12-pad1_ net-_u19-pad2_ d_and +* u5 /3 net-_u12-pad1_ net-_u20-pad1_ d_and +x1 /5 /2 /3 net-_u20-pad2_ 3_and +* u6 /5 /2 net-_u15-pad1_ d_and +* u7 /5 /3 net-_u15-pad2_ d_and +* u8 /3 /2 net-_u22-pad2_ d_and +* u9 net-_u12-pad1_ /10 net-_u16-pad1_ d_and +* u10 net-_u1-pad2_ /10 net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ /10 net-_u11-pad3_ d_and +x2 net-_u12-pad1_ net-_u1-pad2_ net-_u11-pad1_ net-_u17-pad2_ 3_and +* u12 net-_u12-pad1_ net-_u1-pad2_ net-_u12-pad3_ d_and +* u13 net-_u12-pad1_ net-_u11-pad1_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u11-pad1_ net-_u14-pad3_ d_and +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u24 net-_u19-pad3_ net-_u20-pad3_ net-_u24-pad3_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or +* u22 net-_u15-pad3_ net-_u22-pad2_ net-_u12-pad1_ d_nor +* u16 net-_u16-pad1_ net-_u10-pad3_ net-_u16-pad3_ d_or +* u17 net-_u11-pad3_ net-_u17-pad2_ net-_u17-pad3_ d_or +* u21 net-_u16-pad3_ net-_u17-pad3_ /12 d_nor +* u18 net-_u12-pad3_ net-_u13-pad3_ net-_u18-pad3_ d_or +* u23 net-_u18-pad3_ net-_u14-pad3_ /10 d_nor +* u25 net-_u24-pad3_ /1 d_inverter +* u2 /13 net-_u11-pad1_ d_inverter +* u1 /14 net-_u1-pad2_ d_inverter +* u26 /1 /2 /3 ? /5 ? ? ? ? /10 ? /12 /13 /14 port +a1 [/5 net-_u12-pad1_ ] net-_u19-pad1_ u3 +a2 [/2 net-_u12-pad1_ ] net-_u19-pad2_ u4 +a3 [/3 net-_u12-pad1_ ] net-_u20-pad1_ u5 +a4 [/5 /2 ] net-_u15-pad1_ u6 +a5 [/5 /3 ] net-_u15-pad2_ u7 +a6 [/3 /2 ] net-_u22-pad2_ u8 +a7 [net-_u12-pad1_ /10 ] net-_u16-pad1_ u9 +a8 [net-_u1-pad2_ /10 ] net-_u10-pad3_ u10 +a9 [net-_u11-pad1_ /10 ] net-_u11-pad3_ u11 +a10 [net-_u12-pad1_ net-_u1-pad2_ ] net-_u12-pad3_ u12 +a11 [net-_u12-pad1_ net-_u11-pad1_ ] net-_u13-pad3_ u13 +a12 [net-_u1-pad2_ net-_u11-pad1_ ] net-_u14-pad3_ u14 +a13 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a14 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a15 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u24-pad3_ u24 +a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u22-pad2_ ] net-_u12-pad1_ u22 +a18 [net-_u16-pad1_ net-_u10-pad3_ ] net-_u16-pad3_ u16 +a19 [net-_u11-pad3_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a20 [net-_u16-pad3_ net-_u17-pad3_ ] /12 u21 +a21 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u18-pad3_ u18 +a22 [net-_u18-pad3_ net-_u14-pad3_ ] /10 u23 +a23 net-_u24-pad3_ /1 u25 +a24 /13 net-_u11-pad1_ u2 +a25 /14 net-_u1-pad2_ u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7482/SN7482.pro b/library/SubcircuitLibrary/SN7482/SN7482.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/SN7482.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7482/SN7482.sch b/library/SubcircuitLibrary/SN7482/SN7482.sch new file mode 100644 index 000000000..14f55b344 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/SN7482.sch @@ -0,0 +1,754 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U3 +U 1 1 68430FAC +P 5050 1050 +F 0 "U3" H 5050 1050 60 0000 C CNN +F 1 "d_and" H 5100 1150 60 0000 C CNN +F 2 "" H 5050 1050 60 0000 C CNN +F 3 "" H 5050 1050 60 0000 C CNN + 1 5050 1050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 684310EA +P 5050 1350 +F 0 "U4" H 5050 1350 60 0000 C CNN +F 1 "d_and" H 5100 1450 60 0000 C CNN +F 2 "" H 5050 1350 60 0000 C CNN +F 3 "" H 5050 1350 60 0000 C CNN + 1 5050 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68431109 +P 5050 1650 +F 0 "U5" H 5050 1650 60 0000 C CNN +F 1 "d_and" H 5100 1750 60 0000 C CNN +F 2 "" H 5050 1650 60 0000 C CNN +F 3 "" H 5050 1650 60 0000 C CNN + 1 5050 1650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 68431114 +P 4950 2050 +F 0 "X1" H 5050 2000 60 0000 C CNN +F 1 "3_and" H 5100 2200 60 0000 C CNN +F 2 "" H 4950 2050 60 0000 C CNN +F 3 "" H 4950 2050 60 0000 C CNN + 1 4950 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 684311E6 +P 5050 2650 +F 0 "U6" H 5050 2650 60 0000 C CNN +F 1 "d_and" H 5100 2750 60 0000 C CNN +F 2 "" H 5050 2650 60 0000 C CNN +F 3 "" H 5050 2650 60 0000 C CNN + 1 5050 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 684311EC +P 5050 2950 +F 0 "U7" H 5050 2950 60 0000 C CNN +F 1 "d_and" H 5100 3050 60 0000 C CNN +F 2 "" H 5050 2950 60 0000 C CNN +F 3 "" H 5050 2950 60 0000 C CNN + 1 5050 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 684311F2 +P 5050 3250 +F 0 "U8" H 5050 3250 60 0000 C CNN +F 1 "d_and" H 5100 3350 60 0000 C CNN +F 2 "" H 5050 3250 60 0000 C CNN +F 3 "" H 5050 3250 60 0000 C CNN + 1 5050 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 68431293 +P 5050 3850 +F 0 "U9" H 5050 3850 60 0000 C CNN +F 1 "d_and" H 5100 3950 60 0000 C CNN +F 2 "" H 5050 3850 60 0000 C CNN +F 3 "" H 5050 3850 60 0000 C CNN + 1 5050 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 68431299 +P 5050 4150 +F 0 "U10" H 5050 4150 60 0000 C CNN +F 1 "d_and" H 5100 4250 60 0000 C CNN +F 2 "" H 5050 4150 60 0000 C CNN +F 3 "" H 5050 4150 60 0000 C CNN + 1 5050 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 6843129F +P 5050 4450 +F 0 "U11" H 5050 4450 60 0000 C CNN +F 1 "d_and" H 5100 4550 60 0000 C CNN +F 2 "" H 5050 4450 60 0000 C CNN +F 3 "" H 5050 4450 60 0000 C CNN + 1 5050 4450 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68431324 +P 4950 4850 +F 0 "X2" H 5050 4800 60 0000 C CNN +F 1 "3_and" H 5100 5000 60 0000 C CNN +F 2 "" H 4950 4850 60 0000 C CNN +F 3 "" H 4950 4850 60 0000 C CNN + 1 4950 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 684313DF +P 5050 5600 +F 0 "U12" H 5050 5600 60 0000 C CNN +F 1 "d_and" H 5100 5700 60 0000 C CNN +F 2 "" H 5050 5600 60 0000 C CNN +F 3 "" H 5050 5600 60 0000 C CNN + 1 5050 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 684313E5 +P 5050 5900 +F 0 "U13" H 5050 5900 60 0000 C CNN +F 1 "d_and" H 5100 6000 60 0000 C CNN +F 2 "" H 5050 5900 60 0000 C CNN +F 3 "" H 5050 5900 60 0000 C CNN + 1 5050 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 684313EB +P 5050 6200 +F 0 "U14" H 5050 6200 60 0000 C CNN +F 1 "d_and" H 5100 6300 60 0000 C CNN +F 2 "" H 5050 6200 60 0000 C CNN +F 3 "" H 5050 6200 60 0000 C CNN + 1 5050 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 6843300B +P 6450 1200 +F 0 "U19" H 6450 1200 60 0000 C CNN +F 1 "d_or" H 6450 1300 60 0000 C CNN +F 2 "" H 6450 1200 60 0000 C CNN +F 3 "" H 6450 1200 60 0000 C CNN + 1 6450 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 684330D8 +P 6450 1850 +F 0 "U20" H 6450 1850 60 0000 C CNN +F 1 "d_or" H 6450 1950 60 0000 C CNN +F 2 "" H 6450 1850 60 0000 C CNN +F 3 "" H 6450 1850 60 0000 C CNN + 1 6450 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U24 +U 1 1 684330F0 +P 7750 1450 +F 0 "U24" H 7750 1450 60 0000 C CNN +F 1 "d_nor" H 7800 1550 60 0000 C CNN +F 2 "" H 7750 1450 60 0000 C CNN +F 3 "" H 7750 1450 60 0000 C CNN + 1 7750 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 68433CA7 +P 6350 2800 +F 0 "U15" H 6350 2800 60 0000 C CNN +F 1 "d_or" H 6350 2900 60 0000 C CNN +F 2 "" H 6350 2800 60 0000 C CNN +F 3 "" H 6350 2800 60 0000 C CNN + 1 6350 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U22 +U 1 1 68433D40 +P 7550 2850 +F 0 "U22" H 7550 2850 60 0000 C CNN +F 1 "d_nor" H 7600 2950 60 0000 C CNN +F 2 "" H 7550 2850 60 0000 C CNN +F 3 "" H 7550 2850 60 0000 C CNN + 1 7550 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U16 +U 1 1 68434EA1 +P 6350 4000 +F 0 "U16" H 6350 4000 60 0000 C CNN +F 1 "d_or" H 6350 4100 60 0000 C CNN +F 2 "" H 6350 4000 60 0000 C CNN +F 3 "" H 6350 4000 60 0000 C CNN + 1 6350 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_or U17 +U 1 1 68435248 +P 6350 4650 +F 0 "U17" H 6350 4650 60 0000 C CNN +F 1 "d_or" H 6350 4750 60 0000 C CNN +F 2 "" H 6350 4650 60 0000 C CNN +F 3 "" H 6350 4650 60 0000 C CNN + 1 6350 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U21 +U 1 1 68435A61 +P 7500 4300 +F 0 "U21" H 7500 4300 60 0000 C CNN +F 1 "d_nor" H 7550 4400 60 0000 C CNN +F 2 "" H 7500 4300 60 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 68436162 +P 6400 5700 +F 0 "U18" H 6400 5700 60 0000 C CNN +F 1 "d_or" H 6400 5800 60 0000 C CNN +F 2 "" H 6400 5700 60 0000 C CNN +F 3 "" H 6400 5700 60 0000 C CNN + 1 6400 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U23 +U 1 1 68436248 +P 7550 5900 +F 0 "U23" H 7550 5900 60 0000 C CNN +F 1 "d_nor" H 7600 6000 60 0000 C CNN +F 2 "" H 7550 5900 60 0000 C CNN +F 3 "" H 7550 5900 60 0000 C CNN + 1 7550 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 68437AE2 +P 8750 1400 +F 0 "U25" H 8750 1300 60 0000 C CNN +F 1 "d_inverter" H 8750 1550 60 0000 C CNN +F 2 "" H 8800 1350 60 0000 C CNN +F 3 "" H 8800 1350 60 0000 C CNN + 1 8750 1400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 1000 5800 1000 +Wire Wire Line + 5800 1000 5800 1100 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+Wire Wire Line + 3550 2950 4600 2950 +Connection ~ 3550 2100 +Wire Wire Line + 4100 3250 4600 3250 +Connection ~ 4100 2650 +Wire Wire Line + 3550 3150 4600 3150 +Connection ~ 3550 2950 +Wire Wire Line + 4000 3750 4600 3750 +Connection ~ 4000 3600 +Wire Wire Line + 4600 3850 4300 3850 +Wire Wire Line + 4300 3850 4300 5100 +Wire Wire Line + 4300 5100 8200 5100 +Wire Wire Line + 8200 5100 8200 5850 +Connection ~ 8200 5850 +Wire Wire Line + 4600 4050 4150 4050 +Wire Wire Line + 4150 4050 4150 6100 +Wire Wire Line + 4150 6100 4600 6100 +Wire Wire Line + 4600 4150 4300 4150 +Connection ~ 4300 4150 +Wire Wire Line + 3300 4350 4600 4350 +Wire Wire Line + 4600 4450 4300 4450 +Connection ~ 4300 4450 +Wire Wire Line + 4000 4700 4600 4700 +Connection ~ 4000 3750 +Wire Wire Line + 3150 4800 4600 4800 +Connection ~ 4150 4800 +Wire Wire Line + 3800 4350 3800 6200 +Wire Wire Line + 3800 6200 4600 6200 +Connection ~ 3800 4350 +Wire Wire Line + 4600 4900 3800 4900 +Connection ~ 3800 4900 +Wire Wire Line + 4600 5600 4150 5600 +Connection ~ 4150 5600 +Wire Wire Line + 4000 5800 4600 5800 +Connection ~ 4000 4700 +Wire Wire Line + 4600 5900 3800 5900 +Connection ~ 3800 5900 +Wire Wire Line + 4600 5500 4000 5500 +Connection ~ 4000 5500 +$Comp +L d_inverter U2 +U 1 1 68440F50 +P 3000 4350 +F 0 "U2" H 3000 4250 60 0000 C CNN +F 1 "d_inverter" H 3000 4500 60 0000 C CNN +F 2 "" H 3050 4300 60 0000 C CNN +F 3 "" H 3050 4300 60 0000 C CNN + 1 3000 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2400 4350 2700 4350 +$Comp +L d_inverter U1 +U 1 1 684410EB +P 2850 4800 +F 0 "U1" H 2850 4700 60 0000 C CNN +F 1 "d_inverter" H 2850 4950 60 0000 C CNN +F 2 "" H 2900 4750 60 0000 C CNN +F 3 "" H 2900 4750 60 0000 C CNN + 1 2850 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2400 4800 2550 4800 +Text Label 2400 4800 0 60 ~ 0 +14 +Text Label 2400 4350 0 60 ~ 0 +13 +Text Label 3200 1550 0 60 ~ 0 +3 +Text Label 3200 1250 0 60 ~ 0 +2 +Text Label 3200 950 0 60 ~ 0 +5 +Text Label 9300 1400 0 60 ~ 0 +1 +Text Label 8750 4250 0 60 ~ 0 +12 +Text Label 8500 5850 0 60 ~ 0 +10 +$Comp +L PORT U26 +U 3 1 6844A2B5 +P 2950 1550 +F 0 "U26" H 3000 1650 30 0000 C CNN +F 1 "PORT" H 2950 1550 30 0000 C CNN +F 2 "" H 2950 1550 60 0000 C CNN +F 3 "" H 2950 1550 60 0000 C CNN + 3 2950 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 6 1 6844A352 +P 1850 2300 +F 0 "U26" H 1900 2400 30 0000 C CNN +F 1 "PORT" H 1850 2300 30 0000 C CNN +F 2 "" H 1850 2300 60 0000 C CNN +F 3 "" H 1850 2300 60 0000 C CNN + 6 1850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 10 1 6844A3A3 +P 8750 5850 +F 0 "U26" H 8800 5950 30 0000 C CNN +F 1 "PORT" H 8750 5850 30 0000 C CNN +F 2 "" H 8750 5850 60 0000 C CNN +F 3 "" H 8750 5850 60 0000 C CNN + 10 8750 5850 + -1 0 0 1 +$EndComp +$Comp +L PORT U26 +U 14 1 6844A41A +P 2150 4800 +F 0 "U26" H 2200 4900 30 0000 C CNN +F 1 "PORT" H 2150 4800 30 0000 C CNN +F 2 "" H 2150 4800 60 0000 C CNN +F 3 "" H 2150 4800 60 0000 C CNN + 14 2150 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 1 1 6844A493 +P 9550 1400 +F 0 "U26" H 9600 1500 30 0000 C CNN +F 1 "PORT" H 9550 1400 30 0000 C CNN +F 2 "" H 9550 1400 60 0000 C CNN +F 3 "" H 9550 1400 60 0000 C CNN + 1 9550 1400 + -1 0 0 1 +$EndComp +$Comp +L PORT U26 +U 7 1 6844A4F0 +P 1850 2550 +F 0 "U26" H 1900 2650 30 0000 C CNN +F 1 "PORT" H 1850 2550 30 0000 C CNN +F 2 "" H 1850 2550 60 0000 C CNN +F 3 "" H 1850 2550 60 0000 C CNN + 7 1850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 11 1 6844A54D +P 2350 2550 +F 0 "U26" H 2400 2650 30 0000 C CNN +F 1 "PORT" H 2350 2550 30 0000 C CNN +F 2 "" H 2350 2550 60 0000 C CNN +F 3 "" H 2350 2550 60 0000 C CNN + 11 2350 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 12 1 6844A5A6 +P 9000 4250 +F 0 "U26" H 9050 4350 30 0000 C CNN +F 1 "PORT" H 9000 4250 30 0000 C CNN +F 2 "" H 9000 4250 60 0000 C CNN +F 3 "" H 9000 4250 60 0000 C CNN + 12 9000 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U26 +U 2 1 6844A601 +P 2950 1250 +F 0 "U26" H 3000 1350 30 0000 C CNN +F 1 "PORT" H 2950 1250 30 0000 C CNN +F 2 "" H 2950 1250 60 0000 C CNN +F 3 "" H 2950 1250 60 0000 C CNN + 2 2950 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 5 1 6844A674 +P 2950 950 +F 0 "U26" H 3000 1050 30 0000 C CNN +F 1 "PORT" H 2950 950 30 0000 C CNN +F 2 "" H 2950 950 60 0000 C CNN +F 3 "" H 2950 950 60 0000 C CNN + 5 2950 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 9 1 6844A6D3 +P 2200 2850 +F 0 "U26" H 2250 2950 30 0000 C CNN +F 1 "PORT" H 2200 2850 30 0000 C CNN +F 2 "" H 2200 2850 60 0000 C CNN +F 3 "" H 2200 2850 60 0000 C CNN + 9 2200 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 13 1 6844A734 +P 2150 4350 +F 0 "U26" H 2200 4450 30 0000 C CNN +F 1 "PORT" H 2150 4350 30 0000 C CNN +F 2 "" H 2150 4350 60 0000 C CNN +F 3 "" H 2150 4350 60 0000 C CNN + 13 2150 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 4 1 6844A797 +P 1450 3050 +F 0 "U26" H 1500 3150 30 0000 C CNN +F 1 "PORT" H 1450 3050 30 0000 C CNN +F 2 "" H 1450 3050 60 0000 C CNN +F 3 "" H 1450 3050 60 0000 C CNN + 4 1450 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U26 +U 8 1 6844A80A +P 2000 3100 +F 0 "U26" H 2050 3200 30 0000 C CNN +F 1 "PORT" H 2000 3100 30 0000 C CNN +F 2 "" H 2000 3100 60 0000 C CNN +F 3 "" H 2000 3100 60 0000 C CNN + 8 2000 3100 + 1 0 0 -1 +$EndComp +NoConn ~ 1700 3050 +NoConn ~ 2250 3100 +NoConn ~ 2450 2850 +NoConn ~ 2600 2550 +NoConn ~ 2100 2550 +NoConn ~ 2100 2300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7482/SN7482.sub b/library/SubcircuitLibrary/SN7482/SN7482.sub new file mode 100644 index 000000000..9668175ef --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/SN7482.sub @@ -0,0 +1,109 @@ +* Subcircuit SN7482 +.subckt SN7482 /1 /2 /3 ? /5 ? ? ? ? /10 ? /12 /13 /14 +* d:\fossee\esim\library\subcircuitlibrary\sn7482\sn7482.cir +.include 3_and.sub +* u3 /5 net-_u12-pad1_ net-_u19-pad1_ d_and +* u4 /2 net-_u12-pad1_ net-_u19-pad2_ d_and +* u5 /3 net-_u12-pad1_ net-_u20-pad1_ d_and +x1 /5 /2 /3 net-_u20-pad2_ 3_and +* u6 /5 /2 net-_u15-pad1_ d_and +* u7 /5 /3 net-_u15-pad2_ d_and +* u8 /3 /2 net-_u22-pad2_ d_and +* u9 net-_u12-pad1_ /10 net-_u16-pad1_ d_and +* u10 net-_u1-pad2_ /10 net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ /10 net-_u11-pad3_ d_and +x2 net-_u12-pad1_ net-_u1-pad2_ net-_u11-pad1_ net-_u17-pad2_ 3_and +* u12 net-_u12-pad1_ net-_u1-pad2_ net-_u12-pad3_ d_and +* u13 net-_u12-pad1_ net-_u11-pad1_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u11-pad1_ net-_u14-pad3_ d_and +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u24 net-_u19-pad3_ net-_u20-pad3_ net-_u24-pad3_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or +* u22 net-_u15-pad3_ net-_u22-pad2_ net-_u12-pad1_ d_nor +* u16 net-_u16-pad1_ net-_u10-pad3_ net-_u16-pad3_ d_or +* u17 net-_u11-pad3_ net-_u17-pad2_ net-_u17-pad3_ d_or +* u21 net-_u16-pad3_ net-_u17-pad3_ /12 d_nor +* u18 net-_u12-pad3_ net-_u13-pad3_ net-_u18-pad3_ d_or +* u23 net-_u18-pad3_ net-_u14-pad3_ /10 d_nor +* u25 net-_u24-pad3_ /1 d_inverter +* u2 /13 net-_u11-pad1_ d_inverter +* u1 /14 net-_u1-pad2_ d_inverter +a1 [/5 net-_u12-pad1_ ] net-_u19-pad1_ u3 +a2 [/2 net-_u12-pad1_ ] net-_u19-pad2_ u4 +a3 [/3 net-_u12-pad1_ ] net-_u20-pad1_ u5 +a4 [/5 /2 ] net-_u15-pad1_ u6 +a5 [/5 /3 ] net-_u15-pad2_ u7 +a6 [/3 /2 ] net-_u22-pad2_ u8 +a7 [net-_u12-pad1_ /10 ] net-_u16-pad1_ u9 +a8 [net-_u1-pad2_ /10 ] net-_u10-pad3_ u10 +a9 [net-_u11-pad1_ /10 ] net-_u11-pad3_ u11 +a10 [net-_u12-pad1_ net-_u1-pad2_ ] net-_u12-pad3_ u12 +a11 [net-_u12-pad1_ net-_u11-pad1_ ] net-_u13-pad3_ u13 +a12 [net-_u1-pad2_ net-_u11-pad1_ ] net-_u14-pad3_ u14 +a13 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a14 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a15 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u24-pad3_ u24 +a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u22-pad2_ ] net-_u12-pad1_ u22 +a18 [net-_u16-pad1_ net-_u10-pad3_ ] net-_u16-pad3_ u16 +a19 [net-_u11-pad3_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a20 [net-_u16-pad3_ net-_u17-pad3_ ] /12 u21 +a21 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u18-pad3_ u18 +a22 [net-_u18-pad3_ net-_u14-pad3_ ] /10 u23 +a23 net-_u24-pad3_ /1 u25 +a24 /13 net-_u11-pad1_ u2 +a25 /14 net-_u1-pad2_ u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN7482 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7482/SN7482_Previous_Values.xml b/library/SubcircuitLibrary/SN7482/SN7482_Previous_Values.xml new file mode 100644 index 000000000..3da4f386e --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/SN7482_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_nord_ord_nord_ord_ord_nord_ord_nord_inverterd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7482/analysis b/library/SubcircuitLibrary/SN7482/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN7482/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396-cache.lib b/library/SubcircuitLibrary/SN74LS396/SN74LS396-cache.lib new file mode 100644 index 000000000..5ce2c6d86 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir new file mode 100644 index 000000000..1d2fc1cfa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir @@ -0,0 +1,29 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS396\SN74LS396.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/25 14:56:18 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 /3 Net-_U1-Pad2_ ? ? Net-_U3-Pad5_ Net-_U11-Pad1_ d_dff +U7 Net-_U3-Pad5_ Net-_U1-Pad2_ ? ? ? Net-_U12-Pad2_ d_dff +U4 /6 Net-_U1-Pad2_ ? ? Net-_U4-Pad5_ Net-_U13-Pad1_ d_dff +U8 Net-_U4-Pad5_ Net-_U1-Pad2_ ? ? ? Net-_U14-Pad2_ d_dff +U5 /9 Net-_U1-Pad2_ ? ? Net-_U5-Pad5_ Net-_U15-Pad1_ d_dff +U9 Net-_U5-Pad5_ Net-_U1-Pad2_ ? ? ? Net-_U16-Pad2_ d_dff +U6 /12 Net-_U1-Pad2_ ? ? Net-_U10-Pad1_ Net-_U17-Pad1_ d_dff +U10 Net-_U10-Pad1_ Net-_U1-Pad2_ ? ? ? Net-_U10-Pad6_ d_dff +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ /5 d_nor +U14 Net-_U11-Pad2_ Net-_U14-Pad2_ /4 d_nor +U15 Net-_U15-Pad1_ Net-_U11-Pad2_ /10 d_nor +U16 Net-_U11-Pad2_ Net-_U16-Pad2_ /11 d_nor +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ /2 d_nor +U12 Net-_U11-Pad2_ Net-_U12-Pad2_ /1 d_nor +U17 Net-_U17-Pad1_ Net-_U11-Pad2_ /13 d_nor +U18 Net-_U11-Pad2_ Net-_U10-Pad6_ /14 d_nor +U2 /15 Net-_U11-Pad2_ d_buffer +U1 /7 Net-_U1-Pad2_ d_inverter +U19 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir.out b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir.out new file mode 100644 index 000000000..70c4b5306 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir.out @@ -0,0 +1,84 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls396\sn74ls396.cir + +* u3 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ d_dff +* u7 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ d_dff +* u4 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ d_dff +* u8 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ d_dff +* u5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ d_dff +* u9 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ d_dff +* u6 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ d_dff +* u10 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ d_dff +* u13 net-_u13-pad1_ net-_u11-pad2_ /5 d_nor +* u14 net-_u11-pad2_ net-_u14-pad2_ /4 d_nor +* u15 net-_u15-pad1_ net-_u11-pad2_ /10 d_nor +* u16 net-_u11-pad2_ net-_u16-pad2_ /11 d_nor +* u11 net-_u11-pad1_ net-_u11-pad2_ /2 d_nor +* u12 net-_u11-pad2_ net-_u12-pad2_ /1 d_nor +* u17 net-_u17-pad1_ net-_u11-pad2_ /13 d_nor +* u18 net-_u11-pad2_ net-_u10-pad6_ /14 d_nor +* u2 /15 net-_u11-pad2_ d_buffer +* u1 /7 net-_u1-pad2_ d_inverter +* u19 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? port +a1 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ u3 +a2 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ u7 +a3 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ u4 +a4 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ u8 +a5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ u5 +a6 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ u9 +a7 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ u6 +a8 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ u10 +a9 [net-_u13-pad1_ net-_u11-pad2_ ] /5 u13 +a10 [net-_u11-pad2_ net-_u14-pad2_ ] /4 u14 +a11 [net-_u15-pad1_ net-_u11-pad2_ ] /10 u15 +a12 [net-_u11-pad2_ net-_u16-pad2_ ] /11 u16 +a13 [net-_u11-pad1_ net-_u11-pad2_ ] /2 u11 +a14 [net-_u11-pad2_ net-_u12-pad2_ ] /1 u12 +a15 [net-_u17-pad1_ net-_u11-pad2_ ] /13 u17 +a16 [net-_u11-pad2_ net-_u10-pad6_ ] /14 u18 +a17 /15 net-_u11-pad2_ u2 +a18 /7 net-_u1-pad2_ u1 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.pro b/library/SubcircuitLibrary/SN74LS396/SN74LS396.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.sch b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sch new file mode 100644 index 000000000..e57cf239c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sch @@ -0,0 +1,629 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS396-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U3 +U 1 1 684A98AA +P 5150 2550 +F 0 "U3" H 5150 2550 60 0000 C CNN +F 1 "d_dff" H 5150 2700 60 0000 C CNN +F 2 "" H 5150 2550 60 0000 C CNN +F 3 "" H 5150 2550 60 0000 C CNN + 1 5150 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U7 +U 1 1 684A99B9 +P 6950 2550 +F 0 "U7" H 6950 2550 60 0000 C CNN +F 1 "d_dff" H 6950 2700 60 0000 C CNN +F 2 "" H 6950 2550 60 0000 C CNN +F 3 "" H 6950 2550 60 0000 C CNN + 1 6950 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U4 +U 1 1 684A9B41 +P 5150 4200 +F 0 "U4" H 5150 4200 60 0000 C CNN +F 1 "d_dff" H 5150 4350 60 0000 C CNN +F 2 "" H 5150 4200 60 0000 C CNN +F 3 "" H 5150 4200 60 0000 C CNN + 1 5150 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U8 +U 1 1 684A9B47 +P 6950 4200 +F 0 "U8" H 6950 4200 60 0000 C CNN +F 1 "d_dff" H 6950 4350 60 0000 C CNN +F 2 "" H 6950 4200 60 0000 C CNN +F 3 "" H 6950 4200 60 0000 C CNN + 1 6950 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U5 +U 1 1 684A9BF1 +P 5150 5850 +F 0 "U5" H 5150 5850 60 0000 C CNN +F 1 "d_dff" H 5150 6000 60 0000 C CNN +F 2 "" H 5150 5850 60 0000 C CNN +F 3 "" H 5150 5850 60 0000 C CNN + 1 5150 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U9 +U 1 1 684A9BF7 +P 6950 5850 +F 0 "U9" H 6950 5850 60 0000 C CNN +F 1 "d_dff" H 6950 6000 60 0000 C CNN +F 2 "" H 6950 5850 60 0000 C CNN +F 3 "" H 6950 5850 60 0000 C CNN + 1 6950 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U6 +U 1 1 684A9BFD +P 5150 7500 +F 0 "U6" H 5150 7500 60 0000 C CNN +F 1 "d_dff" H 5150 7650 60 0000 C CNN +F 2 "" H 5150 7500 60 0000 C CNN +F 3 "" H 5150 7500 60 0000 C CNN + 1 5150 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U10 +U 1 1 684A9C03 +P 6950 7500 +F 0 "U10" H 6950 7500 60 0000 C CNN +F 1 "d_dff" H 6950 7650 60 0000 C CNN +F 2 "" H 6950 7500 60 0000 C CNN +F 3 "" H 6950 7500 60 0000 C CNN + 1 6950 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U13 +U 1 1 684AAC31 +P 8750 3900 +F 0 "U13" H 8750 3900 60 0000 C CNN +F 1 "d_nor" H 8800 4000 60 0000 C CNN +F 2 "" H 8750 3900 60 0000 C CNN +F 3 "" H 8750 3900 60 0000 C CNN + 1 8750 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 684AACB6 +P 8750 4450 +F 0 "U14" H 8750 4450 60 0000 C CNN +F 1 "d_nor" H 8800 4550 60 0000 C CNN +F 2 "" H 8750 4450 60 0000 C CNN +F 3 "" H 8750 4450 60 0000 C CNN + 1 8750 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 684AAD2A +P 8750 5600 +F 0 "U15" H 8750 5600 60 0000 C CNN +F 1 "d_nor" H 8800 5700 60 0000 C CNN +F 2 "" H 8750 5600 60 0000 C CNN +F 3 "" H 8750 5600 60 0000 C CNN + 1 8750 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U16 +U 1 1 684AAD30 +P 8750 6150 +F 0 "U16" H 8750 6150 60 0000 C CNN +F 1 "d_nor" H 8800 6250 60 0000 C CNN +F 2 "" H 8750 6150 60 0000 C CNN +F 3 "" H 8750 6150 60 0000 C CNN + 1 8750 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U11 +U 1 1 684AB218 +P 8700 2350 +F 0 "U11" H 8700 2350 60 0000 C CNN +F 1 "d_nor" H 8750 2450 60 0000 C CNN +F 2 "" H 8700 2350 60 0000 C CNN +F 3 "" H 8700 2350 60 0000 C CNN + 1 8700 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 684AB21E +P 8700 2900 +F 0 "U12" H 8700 2900 60 0000 C CNN +F 1 "d_nor" H 8750 3000 60 0000 C CNN +F 2 "" H 8700 2900 60 0000 C CNN +F 3 "" H 8700 2900 60 0000 C CNN + 1 8700 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U17 +U 1 1 684AC196 +P 8750 7250 +F 0 "U17" H 8750 7250 60 0000 C CNN +F 1 "d_nor" H 8800 7350 60 0000 C CNN +F 2 "" H 8750 7250 60 0000 C CNN +F 3 "" H 8750 7250 60 0000 C CNN + 1 8750 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U18 +U 1 1 684AC19C +P 8750 7800 +F 0 "U18" H 8750 7800 60 0000 C CNN +F 1 "d_nor" H 8800 7900 60 0000 C CNN +F 2 "" H 8750 7800 60 0000 C CNN +F 3 "" H 8750 7800 60 0000 C CNN + 1 8750 7800 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U2 +U 1 1 684AE615 +P 5050 8500 +F 0 "U2" H 5050 8450 60 0000 C CNN +F 1 "d_buffer" H 5050 8550 60 0000 C CNN +F 2 "" H 5050 8500 60 0000 C CNN +F 3 "" H 5050 8500 60 0000 C CNN + 1 5050 8500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 684B1ED3 +P 4000 1800 +F 0 "U1" H 4000 1700 60 0000 C CNN +F 1 "d_inverter" H 4000 1950 60 0000 C CNN +F 2 "" H 4050 1750 60 0000 C CNN +F 3 "" H 4050 1750 60 0000 C CNN + 1 4000 1800 + 1 0 0 -1 +$EndComp +NoConn ~ 5150 1900 +NoConn ~ 5150 3150 +NoConn ~ 5150 3550 +NoConn ~ 5150 4800 +NoConn ~ 5150 5200 +NoConn ~ 5150 6450 +NoConn ~ 5150 6850 +NoConn ~ 5150 8100 +NoConn ~ 6950 8100 +NoConn ~ 6950 6850 +NoConn ~ 6950 6450 +NoConn ~ 6950 5200 +NoConn ~ 6950 4800 +NoConn ~ 6950 3550 +NoConn ~ 6950 1900 +NoConn ~ 6950 3150 +Text Label 3600 1800 0 60 ~ 0 +7 +Text Label 3950 2200 0 60 ~ 0 +3 +Text Label 4100 3850 0 60 ~ 0 +6 +Text Label 4150 5500 0 60 ~ 0 +9 +Text Label 4200 7150 0 60 ~ 0 +12 +Text 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"" H 3700 2200 60 0000 C CNN +F 3 "" H 3700 2200 60 0000 C CNN + 3 3700 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 9 1 684C2B03 +P 3900 5500 +F 0 "U19" H 3950 5600 30 0000 C CNN +F 1 "PORT" H 3900 5500 30 0000 C CNN +F 2 "" H 3900 5500 60 0000 C CNN +F 3 "" H 3900 5500 60 0000 C CNN + 9 3900 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 13 1 684C2B46 +P 9800 7200 +F 0 "U19" H 9850 7300 30 0000 C CNN +F 1 "PORT" H 9800 7200 30 0000 C CNN +F 2 "" H 9800 7200 60 0000 C CNN +F 3 "" H 9800 7200 60 0000 C CNN + 13 9800 7200 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 1 1 684C2B8B +P 9950 2850 +F 0 "U19" H 10000 2950 30 0000 C CNN +F 1 "PORT" H 9950 2850 30 0000 C CNN +F 2 "" H 9950 2850 60 0000 C CNN +F 3 "" H 9950 2850 60 0000 C CNN + 1 9950 2850 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 7 1 684C2BD2 +P 3350 1800 +F 0 "U19" H 3400 1900 30 0000 C CNN +F 1 "PORT" H 3350 1800 30 0000 C CNN +F 2 "" H 3350 1800 60 0000 C CNN +F 3 "" H 3350 1800 60 0000 C CNN + 7 3350 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 14 1 684C2C1B +P 9850 7750 +F 0 "U19" H 9900 7850 30 0000 C CNN +F 1 "PORT" H 9850 7750 30 0000 C CNN +F 2 "" H 9850 7750 60 0000 C CNN +F 3 "" H 9850 7750 60 0000 C CNN + 14 9850 7750 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 5 1 684C2C66 +P 9850 3850 +F 0 "U19" H 9900 3950 30 0000 C CNN +F 1 "PORT" H 9850 3850 30 0000 C CNN +F 2 "" H 9850 3850 60 0000 C CNN +F 3 "" H 9850 3850 60 0000 C CNN + 5 9850 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 11 1 684C2CB3 +P 9800 6100 +F 0 "U19" H 9850 6200 30 0000 C CNN +F 1 "PORT" H 9800 6100 30 0000 C CNN +F 2 "" H 9800 6100 60 0000 C CNN +F 3 "" H 9800 6100 60 0000 C CNN + 11 9800 6100 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 16 1 684C2D1A +P 3650 4850 +F 0 "U19" H 3700 4950 30 0000 C CNN +F 1 "PORT" H 3650 4850 30 0000 C CNN +F 2 "" H 3650 4850 60 0000 C CNN +F 3 "" H 3650 4850 60 0000 C CNN + 16 3650 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 4 1 684C2D6D +P 9900 4400 +F 0 "U19" H 9950 4500 30 0000 C CNN +F 1 "PORT" H 9900 4400 30 0000 C CNN +F 2 "" H 9900 4400 60 0000 C CNN +F 3 "" H 9900 4400 60 0000 C CNN + 4 9900 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 10 1 684C2DC0 +P 9800 5550 +F 0 "U19" H 9850 5650 30 0000 C CNN +F 1 "PORT" H 9800 5550 30 0000 C CNN +F 2 "" H 9800 5550 60 0000 C CNN +F 3 "" H 9800 5550 60 0000 C CNN + 10 9800 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U19 +U 12 1 684C2E15 +P 3950 7150 +F 0 "U19" H 4000 7250 30 0000 C CNN +F 1 "PORT" H 3950 7150 30 0000 C CNN +F 2 "" H 3950 7150 60 0000 C CNN +F 3 "" H 3950 7150 60 0000 C CNN + 12 3950 7150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U19 +U 6 1 684C2E6C +P 3850 3850 +F 0 "U19" H 3900 3950 30 0000 C CNN +F 1 "PORT" H 3850 3850 30 0000 C CNN +F 2 "" H 3850 3850 60 0000 C CNN +F 3 "" H 3850 3850 60 0000 C CNN + 6 3850 3850 + 1 0 0 -1 +$EndComp +NoConn ~ 3900 4850 +NoConn ~ 3900 4600 +NoConn ~ 7500 5500 +NoConn ~ 7500 7150 +NoConn ~ 7500 3850 +NoConn ~ 7500 2200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.sub b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sub new file mode 100644 index 000000000..e779a1b26 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sub @@ -0,0 +1,78 @@ +* Subcircuit SN74LS396 +.subckt SN74LS396 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? +* d:\fossee\esim\library\subcircuitlibrary\sn74ls396\sn74ls396.cir +* u3 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ d_dff +* u7 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ d_dff +* u4 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ d_dff +* u8 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ d_dff +* u5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ d_dff +* u9 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ d_dff +* u6 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ d_dff +* u10 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ d_dff +* u13 net-_u13-pad1_ net-_u11-pad2_ /5 d_nor +* u14 net-_u11-pad2_ net-_u14-pad2_ /4 d_nor +* u15 net-_u15-pad1_ net-_u11-pad2_ /10 d_nor +* u16 net-_u11-pad2_ net-_u16-pad2_ /11 d_nor +* u11 net-_u11-pad1_ net-_u11-pad2_ /2 d_nor +* u12 net-_u11-pad2_ net-_u12-pad2_ /1 d_nor +* u17 net-_u17-pad1_ net-_u11-pad2_ /13 d_nor +* u18 net-_u11-pad2_ net-_u10-pad6_ /14 d_nor +* u2 /15 net-_u11-pad2_ d_buffer +* u1 /7 net-_u1-pad2_ d_inverter +a1 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ u3 +a2 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ u7 +a3 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ u4 +a4 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ u8 +a5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ u5 +a6 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ u9 +a7 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ u6 +a8 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ u10 +a9 [net-_u13-pad1_ net-_u11-pad2_ ] /5 u13 +a10 [net-_u11-pad2_ net-_u14-pad2_ ] /4 u14 +a11 [net-_u15-pad1_ net-_u11-pad2_ ] /10 u15 +a12 [net-_u11-pad2_ net-_u16-pad2_ ] /11 u16 +a13 [net-_u11-pad1_ net-_u11-pad2_ ] /2 u11 +a14 [net-_u11-pad2_ net-_u12-pad2_ ] /1 u12 +a15 [net-_u17-pad1_ net-_u11-pad2_ ] /13 u17 +a16 [net-_u11-pad2_ net-_u10-pad6_ ] /14 u18 +a17 /15 net-_u11-pad2_ u2 +a18 /7 net-_u1-pad2_ u1 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS396 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS396/SN74LS396_Previous_Values.xml new file mode 100644 index 000000000..15ef74423 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_nord_nord_nord_nord_nord_nord_nord_nord_bufferd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS396/analysis b/library/SubcircuitLibrary/SN74LS396/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS396/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350-cache.lib b/library/SubcircuitLibrary/SN74S350/SN74S350-cache.lib new file mode 100644 index 000000000..9398642bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/SN74S350-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.cir b/library/SubcircuitLibrary/SN74S350/SN74S350.cir new file mode 100644 index 000000000..91569f214 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/SN74S350.cir @@ -0,0 +1,68 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74S350\SN74S350.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 16:22:32 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U45 Net-_U35-Pad3_ Net-_U36-Pad3_ Net-_U45-Pad3_ d_or +U50 Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U50-Pad3_ d_nor +U54 Net-_U50-Pad3_ Net-_U54-Pad2_ d_inverter +U58 Net-_U54-Pad2_ Net-_U55-Pad2_ /11 d_tristate +U6 /13 Net-_U55-Pad2_ d_inverter +U3 /10 Net-_U11-Pad1_ d_inverter +U4 Net-_U11-Pad1_ Net-_U10-Pad1_ d_inverter +U35 Net-_U19-Pad3_ /7 Net-_U35-Pad3_ d_and +U19 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U19-Pad3_ d_and +U46 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U46-Pad3_ d_or +U36 Net-_U20-Pad3_ /6 Net-_U36-Pad3_ d_and +U20 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U20-Pad3_ d_and +U37 Net-_U21-Pad3_ /5 Net-_U37-Pad3_ d_and +U21 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_and +U38 Net-_U22-Pad3_ /4 Net-_U38-Pad3_ d_and +U22 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and +U41 Net-_U27-Pad3_ Net-_U28-Pad3_ Net-_U41-Pad3_ d_or +U48 Net-_U41-Pad3_ Net-_U42-Pad3_ Net-_U48-Pad3_ d_nor +U52 Net-_U48-Pad3_ Net-_U52-Pad2_ d_inverter +U56 Net-_U52-Pad2_ Net-_U55-Pad2_ /12 d_tristate +U27 Net-_U11-Pad3_ /6 Net-_U27-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U42 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U42-Pad3_ d_or +U28 Net-_U12-Pad3_ /5 Net-_U28-Pad3_ d_and +U12 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad3_ d_and +U29 Net-_U13-Pad3_ /4 Net-_U29-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U13-Pad3_ d_and +U30 Net-_U14-Pad3_ /3 Net-_U30-Pad3_ d_and +U14 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_and +U43 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U43-Pad3_ d_or +U49 Net-_U43-Pad3_ Net-_U44-Pad3_ Net-_U49-Pad3_ d_nor +U53 Net-_U49-Pad3_ Net-_U53-Pad2_ d_inverter +U57 Net-_U53-Pad2_ Net-_U55-Pad2_ /14 d_tristate +U31 Net-_U15-Pad3_ /5 Net-_U31-Pad3_ d_and +U15 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and +U44 Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U44-Pad3_ d_or +U32 Net-_U16-Pad3_ /4 Net-_U32-Pad3_ d_and +U16 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U16-Pad3_ d_and +U33 Net-_U17-Pad3_ /3 Net-_U33-Pad3_ d_and +U17 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_and +U34 Net-_U18-Pad3_ /2 Net-_U34-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U39 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U39-Pad3_ d_or +U47 Net-_U39-Pad3_ Net-_U40-Pad3_ Net-_U47-Pad3_ d_nor +U51 Net-_U47-Pad3_ Net-_U51-Pad2_ d_inverter +U55 Net-_U51-Pad2_ Net-_U55-Pad2_ /15 d_tristate +U23 Net-_U23-Pad1_ /4 Net-_U23-Pad3_ d_and +U7 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U23-Pad1_ d_and +U40 Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U40-Pad3_ d_or +U24 Net-_U24-Pad1_ /3 Net-_U24-Pad3_ d_and +U8 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U24-Pad1_ d_and +U25 Net-_U25-Pad1_ /2 Net-_U25-Pad3_ d_and +U9 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U25-Pad1_ d_and +U26 Net-_U10-Pad3_ /1 Net-_U26-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U2 /9 Net-_U11-Pad2_ d_inverter +U5 Net-_U11-Pad2_ Net-_U10-Pad2_ d_inverter +U1 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.cir.out b/library/SubcircuitLibrary/SN74S350/SN74S350.cir.out new file mode 100644 index 000000000..83620a0ae --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/SN74S350.cir.out @@ -0,0 +1,240 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74s350\sn74s350.cir + +* u45 net-_u35-pad3_ net-_u36-pad3_ net-_u45-pad3_ d_or +* u50 net-_u45-pad3_ net-_u46-pad3_ net-_u50-pad3_ d_nor +* u54 net-_u50-pad3_ net-_u54-pad2_ d_inverter +* u58 net-_u54-pad2_ net-_u55-pad2_ /11 d_tristate +* u6 /13 net-_u55-pad2_ d_inverter +* u3 /10 net-_u11-pad1_ d_inverter +* u4 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u35 net-_u19-pad3_ /7 net-_u35-pad3_ d_and +* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and +* u46 net-_u37-pad3_ net-_u38-pad3_ net-_u46-pad3_ d_or +* u36 net-_u20-pad3_ /6 net-_u36-pad3_ d_and +* u20 net-_u10-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_and +* u37 net-_u21-pad3_ /5 net-_u37-pad3_ d_and +* u21 net-_u11-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u38 net-_u22-pad3_ /4 net-_u38-pad3_ d_and +* u22 net-_u10-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u41 net-_u27-pad3_ net-_u28-pad3_ net-_u41-pad3_ d_or +* u48 net-_u41-pad3_ net-_u42-pad3_ net-_u48-pad3_ d_nor +* u52 net-_u48-pad3_ net-_u52-pad2_ d_inverter +* u56 net-_u52-pad2_ net-_u55-pad2_ /12 d_tristate +* u27 net-_u11-pad3_ /6 net-_u27-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u42 net-_u29-pad3_ net-_u30-pad3_ net-_u42-pad3_ d_or +* u28 net-_u12-pad3_ /5 net-_u28-pad3_ d_and +* u12 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_and +* u29 net-_u13-pad3_ /4 net-_u29-pad3_ d_and +* u13 net-_u11-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and +* u30 net-_u14-pad3_ /3 net-_u30-pad3_ d_and +* u14 net-_u10-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_or +* u49 net-_u43-pad3_ net-_u44-pad3_ net-_u49-pad3_ d_nor +* u53 net-_u49-pad3_ net-_u53-pad2_ d_inverter +* u57 net-_u53-pad2_ net-_u55-pad2_ /14 d_tristate +* u31 net-_u15-pad3_ /5 net-_u31-pad3_ d_and +* u15 net-_u11-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u44 net-_u33-pad3_ net-_u34-pad3_ net-_u44-pad3_ d_or +* u32 net-_u16-pad3_ /4 net-_u32-pad3_ d_and +* u16 net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_and +* u33 net-_u17-pad3_ /3 net-_u33-pad3_ d_and +* u17 net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u34 net-_u18-pad3_ /2 net-_u34-pad3_ d_and +* u18 net-_u10-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u39 net-_u23-pad3_ net-_u24-pad3_ net-_u39-pad3_ d_or +* u47 net-_u39-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor +* u51 net-_u47-pad3_ net-_u51-pad2_ d_inverter +* u55 net-_u51-pad2_ net-_u55-pad2_ /15 d_tristate +* u23 net-_u23-pad1_ /4 net-_u23-pad3_ d_and +* u7 net-_u11-pad1_ net-_u11-pad2_ net-_u23-pad1_ d_and +* u40 net-_u25-pad3_ net-_u26-pad3_ net-_u40-pad3_ d_or +* u24 net-_u24-pad1_ /3 net-_u24-pad3_ d_and +* u8 net-_u10-pad1_ net-_u11-pad2_ net-_u24-pad1_ d_and +* u25 net-_u25-pad1_ /2 net-_u25-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad2_ net-_u25-pad1_ d_and +* u26 net-_u10-pad3_ /1 net-_u26-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u2 /9 net-_u11-pad2_ d_inverter +* u5 net-_u11-pad2_ net-_u10-pad2_ d_inverter +* u1 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? port +a1 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u45-pad3_ u45 +a2 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u50-pad3_ u50 +a3 net-_u50-pad3_ net-_u54-pad2_ u54 +a4 net-_u54-pad2_ net-_u55-pad2_ /11 u58 +a5 /13 net-_u55-pad2_ u6 +a6 /10 net-_u11-pad1_ u3 +a7 net-_u11-pad1_ net-_u10-pad1_ u4 +a8 [net-_u19-pad3_ /7 ] net-_u35-pad3_ u35 +a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a10 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u46-pad3_ u46 +a11 [net-_u20-pad3_ /6 ] net-_u36-pad3_ u36 +a12 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u20-pad3_ u20 +a13 [net-_u21-pad3_ /5 ] net-_u37-pad3_ u37 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u22-pad3_ /4 ] net-_u38-pad3_ u38 +a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a17 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u41-pad3_ u41 +a18 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u48-pad3_ u48 +a19 net-_u48-pad3_ net-_u52-pad2_ u52 +a20 net-_u52-pad2_ net-_u55-pad2_ /12 u56 +a21 [net-_u11-pad3_ /6 ] net-_u27-pad3_ u27 +a22 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u42-pad3_ u42 +a24 [net-_u12-pad3_ /5 ] net-_u28-pad3_ u28 +a25 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12 +a26 [net-_u13-pad3_ /4 ] net-_u29-pad3_ u29 +a27 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a28 [net-_u14-pad3_ /3 ] net-_u30-pad3_ u30 +a29 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a30 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43 +a31 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u49-pad3_ u49 +a32 net-_u49-pad3_ net-_u53-pad2_ u53 +a33 net-_u53-pad2_ net-_u55-pad2_ /14 u57 +a34 [net-_u15-pad3_ /5 ] net-_u31-pad3_ u31 +a35 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a36 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u44-pad3_ u44 +a37 [net-_u16-pad3_ /4 ] net-_u32-pad3_ u32 +a38 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16 +a39 [net-_u17-pad3_ /3 ] net-_u33-pad3_ u33 +a40 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a41 [net-_u18-pad3_ /2 ] net-_u34-pad3_ u34 +a42 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a43 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u39-pad3_ u39 +a44 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47 +a45 net-_u47-pad3_ net-_u51-pad2_ u51 +a46 net-_u51-pad2_ net-_u55-pad2_ /15 u55 +a47 [net-_u23-pad1_ /4 ] net-_u23-pad3_ u23 +a48 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u23-pad1_ u7 +a49 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u40-pad3_ u40 +a50 [net-_u24-pad1_ /3 ] net-_u24-pad3_ u24 +a51 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u24-pad1_ u8 +a52 [net-_u25-pad1_ /2 ] net-_u25-pad3_ u25 +a53 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u25-pad1_ u9 +a54 [net-_u10-pad3_ /1 ] net-_u26-pad3_ u26 +a55 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a56 /9 net-_u11-pad2_ u2 +a57 net-_u11-pad2_ net-_u10-pad2_ u5 +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u58 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u46 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u56 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u57 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u55 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.pro b/library/SubcircuitLibrary/SN74S350/SN74S350.pro new file mode 100644 index 000000000..c6df329cf --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/SN74S350.pro @@ -0,0 +1,83 @@ +update=07/06/25 15:31:31 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.sch b/library/SubcircuitLibrary/SN74S350/SN74S350.sch new file mode 100644 index 000000000..da2d9082d --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/SN74S350.sch @@ -0,0 +1,1333 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U45 +U 1 1 686A5F02 +P 10950 3850 +F 0 "U45" H 10950 3850 60 0000 C CNN +F 1 "d_or" H 10950 3950 60 0000 C CNN +F 2 "" H 10950 3850 60 0000 C CNN +F 3 "" H 10950 3850 60 0000 C CNN + 1 10950 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U50 +U 1 1 686A5F0E +P 12450 4300 +F 0 "U50" H 12450 4300 60 0000 C CNN +F 1 "d_nor" H 12500 4400 60 0000 C CNN +F 2 "" H 12450 4300 60 0000 C CNN +F 3 "" H 12450 4300 60 0000 C CNN + 1 12450 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U54 +U 1 1 686A5F14 +P 13600 4250 +F 0 "U54" H 13600 4150 60 0000 C CNN +F 1 "d_inverter" H 13600 4400 60 0000 C CNN +F 2 "" H 13650 4200 60 0000 C CNN +F 3 "" H 13650 4200 60 0000 C CNN + 1 13600 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U58 +U 1 1 686A5F1A +P 14800 4600 +F 0 "U58" H 14550 4850 60 0000 C CNN +F 1 "d_tristate" H 14600 5050 60 0000 C CNN +F 2 "" H 14700 4950 60 0000 C CNN +F 3 "" H 14700 4950 60 0000 C CNN + 1 14800 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 686AC3D5 +P 8300 1750 +F 0 "U6" H 8300 1650 60 0000 C CNN +F 1 "d_inverter" H 8300 1900 60 0000 C CNN +F 2 "" H 8350 1700 60 0000 C CNN +F 3 "" H 8350 1700 60 0000 C CNN + 1 8300 1750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 686B27E9 +P 5900 2100 +F 0 "U3" H 5900 2000 60 0000 C CNN +F 1 "d_inverter" H 5900 2250 60 0000 C CNN +F 2 "" H 5950 2050 60 0000 C CNN +F 3 "" H 5950 2050 60 0000 C CNN + 1 5900 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 686B2866 +P 6700 2100 +F 0 "U4" H 6700 2000 60 0000 C CNN +F 1 "d_inverter" H 6700 2250 60 0000 C CNN +F 2 "" H 6750 2050 60 0000 C CNN +F 3 "" H 6750 2050 60 0000 C CNN + 1 6700 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U35 +U 1 1 686B5D69 +P 9650 3450 +F 0 "U35" H 9650 3450 60 0000 C CNN +F 1 "d_and" H 9700 3550 60 0000 C CNN +F 2 "" H 9650 3450 60 0000 C CNN +F 3 "" H 9650 3450 60 0000 C CNN + 1 9650 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 686B5ED7 +P 8500 3400 +F 0 "U19" H 8500 3400 60 0000 C CNN +F 1 "d_and" H 8550 3500 60 0000 C CNN +F 2 "" H 8500 3400 60 0000 C CNN +F 3 "" H 8500 3400 60 0000 C CNN + 1 8500 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U46 +U 1 1 686A5F08 +P 10950 4750 +F 0 "U46" H 10950 4750 60 0000 C CNN +F 1 "d_or" H 10950 4850 60 0000 C CNN +F 2 "" H 10950 4750 60 0000 C CNN +F 3 "" H 10950 4750 60 0000 C CNN + 1 10950 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U36 +U 1 1 686B774E +P 9650 4100 +F 0 "U36" H 9650 4100 60 0000 C CNN +F 1 "d_and" H 9700 4200 60 0000 C CNN +F 2 "" H 9650 4100 60 0000 C CNN +F 3 "" H 9650 4100 60 0000 C CNN + 1 9650 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 686B7754 +P 8500 4050 +F 0 "U20" H 8500 4050 60 0000 C CNN +F 1 "d_and" H 8550 4150 60 0000 C CNN +F 2 "" H 8500 4050 60 0000 C CNN +F 3 "" H 8500 4050 60 0000 C CNN + 1 8500 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U37 +U 1 1 686B7922 +P 9650 4500 +F 0 "U37" H 9650 4500 60 0000 C CNN +F 1 "d_and" H 9700 4600 60 0000 C CNN +F 2 "" H 9650 4500 60 0000 C CNN +F 3 "" H 9650 4500 60 0000 C CNN + 1 9650 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 686B7928 +P 8500 4450 +F 0 "U21" H 8500 4450 60 0000 C CNN +F 1 "d_and" H 8550 4550 60 0000 C CNN +F 2 "" H 8500 4450 60 0000 C CNN +F 3 "" H 8500 4450 60 0000 C CNN + 1 8500 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U38 +U 1 1 686B7C4F +P 9650 4950 +F 0 "U38" H 9650 4950 60 0000 C CNN +F 1 "d_and" H 9700 5050 60 0000 C CNN +F 2 "" H 9650 4950 60 0000 C CNN +F 3 "" H 9650 4950 60 0000 C CNN + 1 9650 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 686B7C55 +P 8500 4900 +F 0 "U22" H 8500 4900 60 0000 C CNN +F 1 "d_and" H 8550 5000 60 0000 C CNN +F 2 "" H 8500 4900 60 0000 C CNN +F 3 "" H 8500 4900 60 0000 C CNN + 1 8500 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U41 +U 1 1 686B838C +P 10900 6150 +F 0 "U41" H 10900 6150 60 0000 C CNN +F 1 "d_or" H 10900 6250 60 0000 C CNN +F 2 "" H 10900 6150 60 0000 C CNN +F 3 "" H 10900 6150 60 0000 C CNN + 1 10900 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U48 +U 1 1 686B8392 +P 12400 6600 +F 0 "U48" H 12400 6600 60 0000 C CNN +F 1 "d_nor" H 12450 6700 60 0000 C CNN +F 2 "" H 12400 6600 60 0000 C CNN +F 3 "" H 12400 6600 60 0000 C CNN + 1 12400 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U52 +U 1 1 686B8398 +P 13550 6550 +F 0 "U52" H 13550 6450 60 0000 C CNN +F 1 "d_inverter" H 13550 6700 60 0000 C CNN +F 2 "" H 13600 6500 60 0000 C CNN +F 3 "" H 13600 6500 60 0000 C CNN + 1 13550 6550 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U56 +U 1 1 686B839E +P 14750 6900 +F 0 "U56" H 14500 7150 60 0000 C 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C CNN +F 2 "" H 16250 6550 60 0000 C CNN +F 3 "" H 16250 6550 60 0000 C CNN + 12 16250 6550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 687209A1 +P 4450 11700 +F 0 "U1" H 4500 11800 30 0000 C CNN +F 1 "PORT" H 4450 11700 30 0000 C CNN +F 2 "" H 4450 11700 60 0000 C CNN +F 3 "" H 4450 11700 60 0000 C CNN + 1 4450 11700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68720A3C +P 5000 4650 +F 0 "U1" H 5050 4750 30 0000 C CNN +F 1 "PORT" H 5000 4650 30 0000 C CNN +F 2 "" H 5000 4650 60 0000 C CNN +F 3 "" H 5000 4650 60 0000 C CNN + 5 5000 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68720AD5 +P 17200 8700 +F 0 "U1" H 17250 8800 30 0000 C CNN +F 1 "PORT" H 17200 8700 30 0000 C CNN +F 2 "" H 17200 8700 60 0000 C CNN +F 3 "" H 17200 8700 60 0000 C CNN + 8 17200 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 68720B6A +P 4900 1750 +F 0 "U1" H 4950 1850 30 0000 C CNN +F 1 "PORT" H 4900 1750 30 0000 C CNN +F 2 "" H 4900 1750 60 0000 C CNN +F 3 "" H 4900 1750 60 0000 C CNN + 13 4900 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68720C03 +P 4450 7400 +F 0 "U1" H 4500 7500 30 0000 C CNN +F 1 "PORT" H 4450 7400 30 0000 C CNN +F 2 "" H 4450 7400 60 0000 C CNN +F 3 "" H 4450 7400 60 0000 C CNN + 3 4450 7400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68720CB4 +P 4950 3600 +F 0 "U1" H 5000 3700 30 0000 C CNN +F 1 "PORT" H 4950 3600 30 0000 C CNN +F 2 "" H 4950 3600 60 0000 C CNN +F 3 "" H 4950 3600 60 0000 C CNN + 7 4950 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 68720D51 +P 16300 4250 +F 0 "U1" H 16350 4350 30 0000 C CNN +F 1 "PORT" H 16300 4250 30 0000 C CNN +F 2 "" H 16300 4250 60 0000 C CNN +F 3 "" H 16300 4250 60 0000 C CNN + 11 16300 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 68720DF4 +P 16200 10850 +F 0 "U1" H 16250 10950 30 0000 C CNN +F 1 "PORT" H 16200 10850 30 0000 C CNN +F 2 "" H 16200 10850 60 0000 C CNN +F 3 "" H 16200 10850 60 0000 C CNN + 15 16200 10850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 68720E95 +P 5000 5100 +F 0 "U1" H 5050 5200 30 0000 C CNN +F 1 "PORT" H 5000 5100 30 0000 C CNN +F 2 "" H 5000 5100 60 0000 C CNN +F 3 "" H 5000 5100 60 0000 C CNN + 4 5000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68720F5C +P 4650 2550 +F 0 "U1" H 4700 2650 30 0000 C CNN +F 1 "PORT" H 4650 2550 30 0000 C CNN +F 2 "" H 4650 2550 60 0000 C CNN +F 3 "" H 4650 2550 60 0000 C CNN + 9 4650 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68721001 +P 16250 8550 +F 0 "U1" H 16300 8650 30 0000 C CNN +F 1 "PORT" H 16250 8550 30 0000 C CNN +F 2 "" H 16250 8550 60 0000 C CNN +F 3 "" H 16250 8550 60 0000 C CNN + 14 16250 8550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 687210AA +P 17200 8900 +F 0 "U1" H 17250 9000 30 0000 C CNN +F 1 "PORT" H 17200 8900 30 0000 C CNN +F 2 "" H 17200 8900 60 0000 C CNN +F 3 "" H 17200 8900 60 0000 C CNN + 16 17200 8900 + 1 0 0 -1 +$EndComp +NoConn ~ 17450 8700 +NoConn ~ 17450 8900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.sub b/library/SubcircuitLibrary/SN74S350/SN74S350.sub new file mode 100644 index 000000000..1dbde6d5e --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/SN74S350.sub @@ -0,0 +1,234 @@ +* Subcircuit SN74S350 +.subckt SN74S350 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? +* d:\fossee\esim\library\subcircuitlibrary\sn74s350\sn74s350.cir +* u45 net-_u35-pad3_ net-_u36-pad3_ net-_u45-pad3_ d_or +* u50 net-_u45-pad3_ net-_u46-pad3_ net-_u50-pad3_ d_nor +* u54 net-_u50-pad3_ net-_u54-pad2_ d_inverter +* u58 net-_u54-pad2_ net-_u55-pad2_ /11 d_tristate +* u6 /13 net-_u55-pad2_ d_inverter +* u3 /10 net-_u11-pad1_ d_inverter +* u4 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u35 net-_u19-pad3_ /7 net-_u35-pad3_ d_and +* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and +* u46 net-_u37-pad3_ net-_u38-pad3_ net-_u46-pad3_ d_or +* u36 net-_u20-pad3_ /6 net-_u36-pad3_ d_and +* u20 net-_u10-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_and +* u37 net-_u21-pad3_ /5 net-_u37-pad3_ d_and +* u21 net-_u11-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u38 net-_u22-pad3_ /4 net-_u38-pad3_ d_and +* u22 net-_u10-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u41 net-_u27-pad3_ net-_u28-pad3_ net-_u41-pad3_ d_or +* u48 net-_u41-pad3_ net-_u42-pad3_ net-_u48-pad3_ d_nor +* u52 net-_u48-pad3_ net-_u52-pad2_ d_inverter +* u56 net-_u52-pad2_ net-_u55-pad2_ /12 d_tristate +* u27 net-_u11-pad3_ /6 net-_u27-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u42 net-_u29-pad3_ net-_u30-pad3_ net-_u42-pad3_ d_or +* u28 net-_u12-pad3_ /5 net-_u28-pad3_ d_and +* u12 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_and +* u29 net-_u13-pad3_ /4 net-_u29-pad3_ d_and +* u13 net-_u11-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and +* u30 net-_u14-pad3_ /3 net-_u30-pad3_ d_and +* u14 net-_u10-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_or +* u49 net-_u43-pad3_ net-_u44-pad3_ net-_u49-pad3_ d_nor +* u53 net-_u49-pad3_ net-_u53-pad2_ d_inverter +* u57 net-_u53-pad2_ net-_u55-pad2_ /14 d_tristate +* u31 net-_u15-pad3_ /5 net-_u31-pad3_ d_and +* u15 net-_u11-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u44 net-_u33-pad3_ net-_u34-pad3_ net-_u44-pad3_ d_or +* u32 net-_u16-pad3_ /4 net-_u32-pad3_ d_and +* u16 net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_and +* u33 net-_u17-pad3_ /3 net-_u33-pad3_ d_and +* u17 net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u34 net-_u18-pad3_ /2 net-_u34-pad3_ d_and +* u18 net-_u10-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u39 net-_u23-pad3_ net-_u24-pad3_ net-_u39-pad3_ d_or +* u47 net-_u39-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor +* u51 net-_u47-pad3_ net-_u51-pad2_ d_inverter +* u55 net-_u51-pad2_ net-_u55-pad2_ /15 d_tristate +* u23 net-_u23-pad1_ /4 net-_u23-pad3_ d_and +* u7 net-_u11-pad1_ net-_u11-pad2_ net-_u23-pad1_ d_and +* u40 net-_u25-pad3_ net-_u26-pad3_ net-_u40-pad3_ d_or +* u24 net-_u24-pad1_ /3 net-_u24-pad3_ d_and +* u8 net-_u10-pad1_ net-_u11-pad2_ net-_u24-pad1_ d_and +* u25 net-_u25-pad1_ /2 net-_u25-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad2_ net-_u25-pad1_ d_and +* u26 net-_u10-pad3_ /1 net-_u26-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u2 /9 net-_u11-pad2_ d_inverter +* u5 net-_u11-pad2_ net-_u10-pad2_ d_inverter +a1 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u45-pad3_ u45 +a2 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u50-pad3_ u50 +a3 net-_u50-pad3_ net-_u54-pad2_ u54 +a4 net-_u54-pad2_ net-_u55-pad2_ /11 u58 +a5 /13 net-_u55-pad2_ u6 +a6 /10 net-_u11-pad1_ u3 +a7 net-_u11-pad1_ net-_u10-pad1_ u4 +a8 [net-_u19-pad3_ /7 ] net-_u35-pad3_ u35 +a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a10 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u46-pad3_ u46 +a11 [net-_u20-pad3_ /6 ] net-_u36-pad3_ u36 +a12 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u20-pad3_ u20 +a13 [net-_u21-pad3_ /5 ] net-_u37-pad3_ u37 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u22-pad3_ /4 ] net-_u38-pad3_ u38 +a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a17 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u41-pad3_ u41 +a18 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u48-pad3_ u48 +a19 net-_u48-pad3_ net-_u52-pad2_ u52 +a20 net-_u52-pad2_ net-_u55-pad2_ /12 u56 +a21 [net-_u11-pad3_ /6 ] net-_u27-pad3_ u27 +a22 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u42-pad3_ u42 +a24 [net-_u12-pad3_ /5 ] net-_u28-pad3_ u28 +a25 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12 +a26 [net-_u13-pad3_ /4 ] net-_u29-pad3_ u29 +a27 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a28 [net-_u14-pad3_ /3 ] net-_u30-pad3_ u30 +a29 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a30 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43 +a31 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u49-pad3_ u49 +a32 net-_u49-pad3_ net-_u53-pad2_ u53 +a33 net-_u53-pad2_ net-_u55-pad2_ /14 u57 +a34 [net-_u15-pad3_ /5 ] net-_u31-pad3_ u31 +a35 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a36 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u44-pad3_ u44 +a37 [net-_u16-pad3_ /4 ] net-_u32-pad3_ u32 +a38 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16 +a39 [net-_u17-pad3_ /3 ] net-_u33-pad3_ u33 +a40 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a41 [net-_u18-pad3_ /2 ] net-_u34-pad3_ u34 +a42 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a43 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u39-pad3_ u39 +a44 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47 +a45 net-_u47-pad3_ net-_u51-pad2_ u51 +a46 net-_u51-pad2_ net-_u55-pad2_ /15 u55 +a47 [net-_u23-pad1_ /4 ] net-_u23-pad3_ u23 +a48 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u23-pad1_ u7 +a49 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u40-pad3_ u40 +a50 [net-_u24-pad1_ /3 ] net-_u24-pad3_ u24 +a51 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u24-pad1_ u8 +a52 [net-_u25-pad1_ /2 ] net-_u25-pad3_ u25 +a53 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u25-pad1_ u9 +a54 [net-_u10-pad3_ /1 ] net-_u26-pad3_ u26 +a55 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a56 /9 net-_u11-pad2_ u2 +a57 net-_u11-pad2_ net-_u10-pad2_ u5 +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u58 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u46 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u56 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u57 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u55 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74S350 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350_Previous_Values.xml b/library/SubcircuitLibrary/SN74S350/SN74S350_Previous_Values.xml new file mode 100644 index 000000000..2aa4f4922 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/SN74S350_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_ord_nord_inverterd_tristated_inverterd_inverterd_inverterd_andd_andd_ord_andd_andd_andd_andd_andd_andd_ord_nord_inverterd_tristated_andd_andd_ord_andd_andd_andd_andd_andd_andd_ord_nord_inverterd_tristated_andd_andd_ord_andd_andd_andd_andd_andd_andd_ord_nord_inverterd_tristated_andd_andd_ord_andd_andd_andd_andd_andd_andd_inverterd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S350/analysis b/library/SubcircuitLibrary/SN74S350/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S350/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1-cache.lib b/library/SubcircuitLibrary/SR_FF1/SR_FF1-cache.lib new file mode 100644 index 000000000..ce6d8814c --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir new file mode 100644 index 000000000..ba6a8f971 --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir @@ -0,0 +1,15 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF\SR_FF.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 17:59:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U4 Net-_U2-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_nand +U5 Net-_U1-Pad5_ Net-_U3-Pad3_ Net-_U1-Pad4_ d_nand +U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir.out b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir.out new file mode 100644 index 000000000..33d1c4912 --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir.out @@ -0,0 +1,28 @@ +* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand +* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4 +a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.pro b/library/SubcircuitLibrary/SR_FF1/SR_FF1.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.sch b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sch new file mode 100644 index 000000000..58667c880 --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sch @@ -0,0 +1,198 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 686919A7 +P 4350 2800 +F 0 "U2" H 4350 2800 60 0000 C CNN +F 1 "d_nand" H 4400 2900 60 0000 C CNN +F 2 "" H 4350 2800 60 0000 C CNN +F 3 "" H 4350 2800 60 0000 C CNN + 1 4350 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 686919EC +P 5850 2800 +F 0 "U4" H 5850 2800 60 0000 C CNN +F 1 "d_nand" H 5900 2900 60 0000 C CNN +F 2 "" H 5850 2800 60 0000 C CNN +F 3 "" H 5850 2800 60 0000 C CNN + 1 5850 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68691A1F +P 5900 4000 +F 0 "U5" H 5900 4000 60 0000 C CNN +F 1 "d_nand" H 5950 4100 60 0000 C CNN +F 2 "" H 5900 4000 60 0000 C CNN +F 3 "" H 5900 4000 60 0000 C CNN + 1 5900 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6300 2750 6800 2750 +Wire Wire Line + 6350 3950 7000 3950 +Wire Wire Line + 6700 2750 6700 3300 +Wire Wire Line + 6700 3300 5200 3300 +Wire Wire Line + 5200 3300 5200 3900 +Wire Wire Line + 5200 3900 5450 3900 +Connection ~ 6700 2750 +Wire Wire Line + 6550 3950 6550 3050 +Wire Wire Line + 6550 3050 5250 3050 +Wire Wire Line + 5250 3050 5250 2800 +Wire Wire Line + 5250 2800 5400 2800 +Connection ~ 6550 3950 +$Comp +L d_nand U3 +U 1 1 68691A8B +P 4350 4050 +F 0 "U3" H 4350 4050 60 0000 C CNN +F 1 "d_nand" H 4400 4150 60 0000 C CNN +F 2 "" H 4350 4050 60 0000 C CNN +F 3 "" H 4350 4050 60 0000 C CNN + 1 4350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 2750 4900 2750 +Wire Wire Line + 4900 2750 4900 2700 +Wire Wire Line + 4900 2700 5400 2700 +Wire Wire Line + 4800 4000 5450 4000 +Wire Wire Line + 3900 2800 3600 2800 +Wire Wire Line + 3600 2800 3600 3950 +Wire Wire Line + 3600 3950 3900 3950 +Wire Wire Line + 3900 2700 3150 2700 +Wire Wire Line + 3900 4050 3150 4050 +Wire Wire Line + 3600 3350 2400 3350 +Connection ~ 3600 3350 +$Comp +L PORT U1 +U 4 1 68691B28 +P 7250 3950 +F 0 "U1" H 7300 4050 30 0000 C CNN +F 1 "PORT" H 7250 3950 30 0000 C CNN +F 2 "" H 7250 3950 60 0000 C CNN +F 3 "" H 7250 3950 60 0000 C CNN + 4 7250 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68691BB8 +P 7050 2750 +F 0 "U1" H 7100 2850 30 0000 C CNN +F 1 "PORT" H 7050 2750 30 0000 C CNN +F 2 "" H 7050 2750 60 0000 C CNN +F 3 "" H 7050 2750 60 0000 C CNN + 5 7050 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 68691BFB +P 2900 4050 +F 0 "U1" H 2950 4150 30 0000 C CNN +F 1 "PORT" H 2900 4050 30 0000 C CNN +F 2 "" H 2900 4050 60 0000 C CNN +F 3 "" H 2900 4050 60 0000 C CNN + 3 2900 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68691C28 +P 2150 3350 +F 0 "U1" H 2200 3450 30 0000 C CNN +F 1 "PORT" H 2150 3350 30 0000 C CNN +F 2 "" H 2150 3350 60 0000 C CNN +F 3 "" H 2150 3350 60 0000 C CNN + 2 2150 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68691C55 +P 2900 2700 +F 0 "U1" H 2950 2800 30 0000 C CNN +F 1 "PORT" H 2900 2700 30 0000 C CNN +F 2 "" H 2900 2700 60 0000 C CNN +F 3 "" H 2900 2700 60 0000 C CNN + 1 2900 2700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.sub b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sub new file mode 100644 index 000000000..97dd47178 --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sub @@ -0,0 +1,22 @@ +* Subcircuit SR_FF +.subckt SR_FF net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand +* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4 +a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SR_FF \ No newline at end of file diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1_Previous_Values.xml b/library/SubcircuitLibrary/SR_FF1/SR_FF1_Previous_Values.xml new file mode 100644 index 000000000..d73809c15 --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_nandd_nand \ No newline at end of file diff --git a/library/SubcircuitLibrary/SR_FF1/analysis b/library/SubcircuitLibrary/SR_FF1/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SR_FF1/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/dff/analysis b/library/SubcircuitLibrary/dff/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/dff/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/dff/dff-cache.lib b/library/SubcircuitLibrary/dff/dff-cache.lib new file mode 100644 index 000000000..440552005 --- /dev/null +++ b/library/SubcircuitLibrary/dff/dff-cache.lib @@ -0,0 +1,92 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/dff/dff.cir b/library/SubcircuitLibrary/dff/dff.cir new file mode 100644 index 000000000..883325a5e --- /dev/null +++ b/library/SubcircuitLibrary/dff/dff.cir @@ -0,0 +1,18 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\dff\dff.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 11:41:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U2-Pad6_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_and +U6 Net-_U4-Pad3_ Net-_U2-Pad3_ Net-_U6-Pad3_ d_and +U7 Net-_U2-Pad4_ Net-_U5-Pad3_ Net-_U2-Pad5_ d_nand +U8 Net-_U2-Pad5_ Net-_U6-Pad3_ Net-_U2-Pad4_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/dff/dff.cir.out b/library/SubcircuitLibrary/dff/dff.cir.out new file mode 100644 index 000000000..849212938 --- /dev/null +++ b/library/SubcircuitLibrary/dff/dff.cir.out @@ -0,0 +1,40 @@ +* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir + +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and +* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand +* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7 +a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8 +a7 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/dff/dff.pro b/library/SubcircuitLibrary/dff/dff.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/dff/dff.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/dff/dff.sch b/library/SubcircuitLibrary/dff/dff.sch new file mode 100644 index 000000000..675737646 --- /dev/null +++ b/library/SubcircuitLibrary/dff/dff.sch @@ -0,0 +1,273 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 6851060F +P 3700 2300 +F 0 "U3" H 3700 2300 60 0000 C CNN +F 1 "d_nand" H 3750 2400 60 0000 C CNN +F 2 "" H 3700 2300 60 0000 C CNN +F 3 "" H 3700 2300 60 0000 C CNN + 1 3700 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68510656 +P 3700 3300 +F 0 "U4" H 3700 3300 60 0000 C CNN +F 1 "d_nand" H 3750 3400 60 0000 C CNN +F 2 "" H 3700 3300 60 0000 C CNN +F 3 "" H 3700 3300 60 0000 C CNN + 1 3700 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68510666 +P 5400 2300 +F 0 "U5" H 5400 2300 60 0000 C CNN +F 1 "d_and" H 5450 2400 60 0000 C CNN +F 2 "" H 5400 2300 60 0000 C CNN +F 3 "" H 5400 2300 60 0000 C CNN + 1 5400 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 685106C5 +P 5400 3300 +F 0 "U6" H 5400 3300 60 0000 C CNN +F 1 "d_and" H 5450 3400 60 0000 C CNN +F 2 "" H 5400 3300 60 0000 C CNN +F 3 "" H 5400 3300 60 0000 C CNN + 1 5400 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 685106D1 +P 7100 2300 +F 0 "U7" H 7100 2300 60 0000 C CNN +F 1 "d_nand" H 7150 2400 60 0000 C CNN +F 2 "" H 7100 2300 60 0000 C CNN +F 3 "" H 7100 2300 60 0000 C CNN + 1 7100 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 68510816 +P 7150 3300 +F 0 "U8" H 7150 3300 60 0000 C CNN +F 1 "d_nand" H 7200 3400 60 0000 C CNN +F 2 "" H 7150 3300 60 0000 C CNN +F 3 "" H 7150 3300 60 0000 C CNN + 1 7150 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 3250 6150 3250 +Wire Wire Line + 6150 3250 6150 3300 +Wire Wire Line + 6150 3300 6700 3300 +Wire Wire Line + 5850 2250 6050 2250 +Wire Wire Line + 6050 2250 6050 2300 +Wire Wire Line + 6050 2300 6650 2300 +Wire Wire Line + 7550 2250 8000 2250 +Wire Wire Line + 7600 3250 8150 3250 +Wire Wire Line + 4950 2200 4750 2200 +Wire Wire Line + 4750 2200 4750 1750 +Wire Wire Line + 4950 3300 4750 3300 +Wire Wire Line + 4750 3300 4750 3800 +Wire Wire Line + 4150 3250 4500 3250 +Wire Wire Line + 4500 3250 4500 3200 +Wire Wire Line + 4500 3200 4950 3200 +Wire Wire Line + 4150 2250 4400 2250 +Wire Wire Line + 4400 2250 4400 2300 +Wire Wire Line + 4400 2300 4950 2300 +Wire Wire Line + 7850 2250 7850 2600 +Wire Wire Line + 7850 2600 6450 2600 +Wire Wire Line + 6450 2600 6450 3200 +Wire Wire Line + 6450 3200 6700 3200 +Connection ~ 7850 2250 +Wire Wire Line + 7750 3250 7750 2750 +Wire Wire Line + 7750 2750 6250 2750 +Wire Wire Line + 6250 2750 6250 2200 +Wire Wire Line + 6250 2200 6650 2200 +Connection ~ 7750 3250 +Wire Wire Line + 3250 2200 2100 2200 +Wire Wire Line + 3250 2300 3000 2300 +Wire Wire Line + 3000 2300 3000 3200 +Wire Wire Line + 3000 3200 3250 3200 +Wire Wire Line + 2300 2200 2300 3300 +Connection ~ 2300 2200 +$Comp +L d_inverter U1 +U 1 1 68510965 +P 2700 3300 +F 0 "U1" H 2700 3200 60 0000 C CNN +F 1 "d_inverter" H 2700 3450 60 0000 C CNN +F 2 "" H 2750 3250 60 0000 C CNN +F 3 "" H 2750 3250 60 0000 C CNN + 1 2700 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 3300 3250 3300 +Wire Wire Line + 2300 3300 2400 3300 +Wire Wire Line + 3000 2750 1950 2750 +Wire Wire Line + 1950 2750 1950 3750 +Connection ~ 3000 2750 +$Comp +L PORT U2 +U 1 1 68510A2C +P 1850 2200 +F 0 "U2" H 1900 2300 30 0000 C CNN +F 1 "PORT" H 1850 2200 30 0000 C CNN +F 2 "" H 1850 2200 60 0000 C CNN +F 3 "" H 1850 2200 60 0000 C CNN + 1 1850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 2 1 68510A87 +P 1700 3750 +F 0 "U2" H 1750 3850 30 0000 C CNN +F 1 "PORT" H 1700 3750 30 0000 C CNN +F 2 "" H 1700 3750 60 0000 C CNN +F 3 "" H 1700 3750 60 0000 C CNN + 2 1700 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 3 1 68510ACA +P 4500 3800 +F 0 "U2" H 4550 3900 30 0000 C CNN +F 1 "PORT" H 4500 3800 30 0000 C CNN +F 2 "" H 4500 3800 60 0000 C CNN +F 3 "" H 4500 3800 60 0000 C CNN + 3 4500 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 5 1 68510AFD +P 8000 2500 +F 0 "U2" H 8050 2600 30 0000 C CNN +F 1 "PORT" H 8000 2500 30 0000 C CNN +F 2 "" H 8000 2500 60 0000 C CNN +F 3 "" H 8000 2500 60 0000 C CNN + 5 8000 2500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 4 1 68510B2C +P 8150 3500 +F 0 "U2" H 8200 3600 30 0000 C CNN +F 1 "PORT" H 8150 3500 30 0000 C CNN +F 2 "" H 8150 3500 60 0000 C CNN +F 3 "" H 8150 3500 60 0000 C CNN + 4 8150 3500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 6 1 68510B5D +P 4500 1750 +F 0 "U2" H 4550 1850 30 0000 C CNN +F 1 "PORT" H 4500 1750 30 0000 C CNN +F 2 "" H 4500 1750 60 0000 C CNN +F 3 "" H 4500 1750 60 0000 C CNN + 6 4500 1750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/dff/dff.sub b/library/SubcircuitLibrary/dff/dff.sub new file mode 100644 index 000000000..885e878fc --- /dev/null +++ b/library/SubcircuitLibrary/dff/dff.sub @@ -0,0 +1,34 @@ +* Subcircuit dff +.subckt dff net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ +* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and +* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and +* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand +* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7 +a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8 +a7 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends dff \ No newline at end of file diff --git a/library/SubcircuitLibrary/dff/dff_Previous_Values.xml b/library/SubcircuitLibrary/dff/dff_Previous_Values.xml new file mode 100644 index 000000000..2a57486b8 --- /dev/null +++ b/library/SubcircuitLibrary/dff/dff_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_andd_andd_nandd_nandd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/dlatch_own/analysis b/library/SubcircuitLibrary/dlatch_own/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own-cache.lib b/library/SubcircuitLibrary/dlatch_own/dlatch_own-cache.lib new file mode 100644 index 000000000..c743d042c --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir new file mode 100644 index 000000000..f79b758d8 --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir @@ -0,0 +1,16 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_own\dlatch_own.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 19:09:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and +U4 Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U4-Pad3_ d_and +U5 Net-_U3-Pad3_ Net-_U2-Pad3_ Net-_U2-Pad4_ d_nor +U6 Net-_U2-Pad4_ Net-_U4-Pad3_ Net-_U2-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir.out b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir.out new file mode 100644 index 000000000..5bcd05907 --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir.out @@ -0,0 +1,32 @@ +* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir + +* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and +* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor +* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ port +a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5 +a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6 +a5 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.pro b/library/SubcircuitLibrary/dlatch_own/dlatch_own.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.sch b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sch new file mode 100644 index 000000000..9ed392a0c --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U3 +U 1 1 6856B545 +P 4350 3350 +F 0 "U3" H 4350 3350 60 0000 C CNN +F 1 "d_and" H 4400 3450 60 0000 C CNN +F 2 "" H 4350 3350 60 0000 C CNN +F 3 "" H 4350 3350 60 0000 C CNN + 1 4350 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 6856B5D2 +P 4400 4750 +F 0 "U4" H 4400 4750 60 0000 C CNN +F 1 "d_and" H 4450 4850 60 0000 C CNN +F 2 "" H 4400 4750 60 0000 C CNN +F 3 "" H 4400 4750 60 0000 C CNN + 1 4400 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 6856B5DC +P 7300 3350 +F 0 "U5" H 7300 3350 60 0000 C CNN +F 1 "d_nor" H 7350 3450 60 0000 C CNN +F 2 "" H 7300 3350 60 0000 C CNN +F 3 "" H 7300 3350 60 0000 C CNN + 1 7300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 6856B689 +P 7300 4750 +F 0 "U6" H 7300 4750 60 0000 C CNN +F 1 "d_nor" H 7350 4850 60 0000 C CNN +F 2 "" H 7300 4750 60 0000 C CNN +F 3 "" H 7300 4750 60 0000 C CNN + 1 7300 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 6856B986 +P 2800 3250 +F 0 "U1" H 2800 3150 60 0000 C CNN +F 1 "d_inverter" H 2800 3400 60 0000 C CNN +F 2 "" H 2850 3200 60 0000 C CNN +F 3 "" H 2850 3200 60 0000 C CNN + 1 2800 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 3300 8750 3300 +Wire Wire Line + 7750 4700 9050 4700 +Wire Wire Line + 6850 4650 6500 4650 +Wire Wire Line + 6500 4650 6500 4300 +Wire Wire Line + 6500 4300 8400 4300 +Wire Wire Line + 8400 4300 8400 3300 +Connection ~ 8400 3300 +Wire Wire Line + 8250 4700 8250 3800 +Wire Wire Line + 8250 3800 6600 3800 +Wire Wire Line + 6600 3800 6600 3350 +Wire Wire Line + 6600 3350 6850 3350 +Connection ~ 8250 4700 +Wire Wire Line + 5150 4700 5150 4750 +Wire Wire Line + 5150 4750 6850 4750 +Wire Wire Line + 4850 4700 5150 4700 +Wire Wire Line + 4800 3300 6400 3300 +Wire Wire Line + 6400 3300 6400 3250 +Wire Wire Line + 6400 3250 6850 3250 +Wire Wire Line + 3900 3350 3450 3350 +Wire Wire Line + 3450 3350 3450 4650 +Wire Wire Line + 3450 4650 3950 4650 +Wire Wire Line + 3950 4750 2500 4750 +Wire Wire Line + 3100 3250 3900 3250 +Wire Wire Line + 2500 3250 2500 4150 +Wire Wire Line + 2500 4150 2800 4150 +Wire Wire Line + 2800 4150 2800 4750 +Connection ~ 2800 4750 +Wire Wire Line + 3450 3950 3200 3950 +Connection ~ 3450 3950 +$Comp +L PORT U2 +U 1 1 6856BAF3 +P 2250 4750 +F 0 "U2" H 2300 4850 30 0000 C CNN +F 1 "PORT" H 2250 4750 30 0000 C CNN +F 2 "" H 2250 4750 60 0000 C CNN +F 3 "" H 2250 4750 60 0000 C CNN + 1 2250 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 3 1 6856BB14 +P 9300 4700 +F 0 "U2" H 9350 4800 30 0000 C CNN +F 1 "PORT" H 9300 4700 30 0000 C CNN +F 2 "" H 9300 4700 60 0000 C CNN +F 3 "" H 9300 4700 60 0000 C CNN + 3 9300 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 6856BB59 +P 2950 3950 +F 0 "U2" H 3000 4050 30 0000 C CNN +F 1 "PORT" H 2950 3950 30 0000 C CNN +F 2 "" H 2950 3950 60 0000 C CNN +F 3 "" H 2950 3950 60 0000 C CNN + 2 2950 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 4 1 6856BB9A +P 9000 3300 +F 0 "U2" H 9050 3400 30 0000 C CNN +F 1 "PORT" H 9000 3300 30 0000 C CNN +F 2 "" H 9000 3300 60 0000 C CNN +F 3 "" H 9000 3300 60 0000 C CNN + 4 9000 3300 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.sub b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sub new file mode 100644 index 000000000..38e1779a5 --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sub @@ -0,0 +1,26 @@ +* Subcircuit dlatch_own +.subckt dlatch_own net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ +* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir +* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and +* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and +* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor +* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5 +a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6 +a5 net-_u1-pad1_ net-_u1-pad2_ u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends dlatch_own \ No newline at end of file diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own_Previous_Values.xml b/library/SubcircuitLibrary/dlatch_own/dlatch_own_Previous_Values.xml new file mode 100644 index 000000000..0a9ca5d55 --- /dev/null +++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nord_nord_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/tff_1/analysis b/library/SubcircuitLibrary/tff_1/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/tff_1/tff_1-cache.lib b/library/SubcircuitLibrary/tff_1/tff_1-cache.lib new file mode 100644 index 000000000..c07ae5124 --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/tff_1-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tff_1/tff_1.cir b/library/SubcircuitLibrary/tff_1/tff_1.cir new file mode 100644 index 000000000..5a146818a --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/tff_1.cir @@ -0,0 +1,19 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1\tff_1.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 12:05:50 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and +U3 Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_and +U4 Net-_U1-Pad3_ Net-_U2-Pad4_ Net-_U4-Pad3_ d_nand +U5 Net-_U2-Pad5_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_nand +U6 Net-_U2-Pad6_ Net-_U4-Pad3_ Net-_U6-Pad3_ d_and +U7 Net-_U5-Pad3_ Net-_U2-Pad3_ Net-_U7-Pad3_ d_and +U8 Net-_U6-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ d_nand +U9 Net-_U2-Pad5_ Net-_U7-Pad3_ Net-_U2-Pad4_ d_nand +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/tff_1/tff_1.cir.out b/library/SubcircuitLibrary/tff_1/tff_1.cir.out new file mode 100644 index 000000000..eb1d38f67 --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/tff_1.cir.out @@ -0,0 +1,44 @@ +* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and +* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and +* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand +* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4 +a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8 +a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tff_1/tff_1.pro b/library/SubcircuitLibrary/tff_1/tff_1.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/tff_1.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/tff_1/tff_1.sch b/library/SubcircuitLibrary/tff_1/tff_1.sch new file mode 100644 index 000000000..467a8221e --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/tff_1.sch @@ -0,0 +1,299 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:tff_1-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U1 +U 1 1 68510BDF +P 3350 2450 +F 0 "U1" H 3350 2450 60 0000 C CNN +F 1 "d_and" H 3400 2550 60 0000 C CNN +F 2 "" H 3350 2450 60 0000 C CNN +F 3 "" H 3350 2450 60 0000 C CNN + 1 3350 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 68510C68 +P 3400 3750 +F 0 "U3" H 3400 3750 60 0000 C CNN +F 1 "d_and" H 3450 3850 60 0000 C CNN +F 2 "" H 3400 3750 60 0000 C CNN +F 3 "" H 3400 3750 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68510CCF +P 5300 2450 +F 0 "U4" H 5300 2450 60 0000 C CNN +F 1 "d_nand" H 5350 2550 60 0000 C CNN +F 2 "" H 5300 2450 60 0000 C CNN +F 3 "" H 5300 2450 60 0000 C CNN + 1 5300 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68510D24 +P 5350 3700 +F 0 "U5" H 5350 3700 60 0000 C CNN +F 1 "d_nand" H 5400 3800 60 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 1 5350 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 2400 4600 2400 +Wire Wire Line + 4600 2400 4600 2350 +Wire Wire Line + 4600 2350 4850 2350 +Wire Wire Line + 3850 3700 4900 3700 +$Comp +L d_and U6 +U 1 1 685111F3 +P 6600 2400 +F 0 "U6" H 6600 2400 60 0000 C CNN +F 1 "d_and" H 6650 2500 60 0000 C CNN +F 2 "" H 6600 2400 60 0000 C CNN +F 3 "" H 6600 2400 60 0000 C CNN + 1 6600 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 685111F9 +P 6650 3700 +F 0 "U7" H 6650 3700 60 0000 C CNN +F 1 "d_and" H 6700 3800 60 0000 C CNN +F 2 "" H 6650 3700 60 0000 C CNN +F 3 "" H 6650 3700 60 0000 C CNN + 1 6650 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 685111FF +P 8550 2400 +F 0 "U8" H 8550 2400 60 0000 C CNN +F 1 "d_nand" H 8600 2500 60 0000 C CNN +F 2 "" H 8550 2400 60 0000 C CNN +F 3 "" H 8550 2400 60 0000 C CNN + 1 8550 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U9 +U 1 1 68511205 +P 8600 3650 +F 0 "U9" H 8600 3650 60 0000 C CNN +F 1 "d_nand" H 8650 3750 60 0000 C CNN +F 2 "" H 8600 3650 60 0000 C CNN +F 3 "" H 8600 3650 60 0000 C CNN + 1 8600 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7050 2350 7850 2350 +Wire Wire Line + 7850 2350 7850 2300 +Wire Wire Line + 7850 2300 8100 2300 +Wire Wire Line + 7100 3650 8150 3650 +Wire Wire Line + 5800 3650 5900 3650 +Wire Wire Line + 5900 3650 5900 3600 +Wire Wire Line + 5900 3600 6200 3600 +Wire Wire Line + 5750 2400 6150 2400 +Wire Wire Line + 6150 2300 5850 2300 +Wire Wire Line + 5850 2300 5850 1900 +Wire Wire Line + 6200 3700 6050 3700 +Wire Wire Line + 6050 3700 6050 4250 +Wire Wire Line + 9000 2350 9700 2350 +Wire Wire Line + 9050 3600 9900 3600 +Wire Wire Line + 9450 2350 9450 3050 +Wire Wire Line + 9450 3050 7750 3050 +Wire Wire Line + 7750 3050 7750 3550 +Wire Wire Line + 7750 3550 8150 3550 +Connection ~ 9450 2350 +Wire Wire Line + 9350 3600 9350 2700 +Wire Wire Line + 9350 2700 8000 2700 +Wire Wire Line + 8000 2700 8000 2400 +Wire Wire Line + 8000 2400 8100 2400 +Connection ~ 9350 3600 +Wire Wire Line + 7750 3200 4550 3200 +Wire Wire Line + 4550 3200 4550 3600 +Wire Wire Line + 4550 3600 4900 3600 +Connection ~ 7750 3200 +Wire Wire Line + 8000 2600 4700 2600 +Wire Wire Line + 4700 2600 4700 2450 +Wire Wire Line + 4700 2450 4850 2450 +Connection ~ 8000 2600 +Wire Wire Line + 2900 2450 2550 2450 +Wire Wire Line + 2550 2450 2550 3650 +Wire Wire Line + 2550 3650 2950 3650 +Wire Wire Line + 2550 3050 2050 3050 +Wire Wire Line + 2050 3050 2050 4200 +Connection ~ 2550 3050 +Wire Wire Line + 2900 2350 1800 2350 +Wire Wire Line + 1800 2350 1800 2300 +Wire Wire Line + 2150 2350 2150 3750 +Wire Wire Line + 2150 3750 2950 3750 +Connection ~ 2150 2350 +$Comp +L PORT U2 +U 1 1 68512107 +P 1550 2300 +F 0 "U2" H 1600 2400 30 0000 C CNN +F 1 "PORT" H 1550 2300 30 0000 C CNN +F 2 "" H 1550 2300 60 0000 C CNN +F 3 "" H 1550 2300 60 0000 C CNN + 1 1550 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 4 1 6851219B +P 9900 3850 +F 0 "U2" H 9950 3950 30 0000 C CNN +F 1 "PORT" H 9900 3850 30 0000 C CNN +F 2 "" H 9900 3850 60 0000 C CNN +F 3 "" H 9900 3850 60 0000 C CNN + 4 9900 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 5 1 685121CC +P 9700 2600 +F 0 "U2" H 9750 2700 30 0000 C CNN +F 1 "PORT" H 9700 2600 30 0000 C CNN +F 2 "" H 9700 2600 60 0000 C CNN +F 3 "" H 9700 2600 60 0000 C CNN + 5 9700 2600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 6 1 68512212 +P 5600 1900 +F 0 "U2" H 5650 2000 30 0000 C CNN +F 1 "PORT" H 5600 1900 30 0000 C CNN +F 2 "" H 5600 1900 60 0000 C CNN +F 3 "" H 5600 1900 60 0000 C CNN + 6 5600 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 2 1 68512275 +P 1800 4200 +F 0 "U2" H 1850 4300 30 0000 C CNN +F 1 "PORT" H 1800 4200 30 0000 C CNN +F 2 "" H 1800 4200 60 0000 C CNN +F 3 "" H 1800 4200 60 0000 C CNN + 2 1800 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 3 1 685122C6 +P 5800 4250 +F 0 "U2" H 5850 4350 30 0000 C CNN +F 1 "PORT" H 5800 4250 30 0000 C CNN +F 2 "" H 5800 4250 60 0000 C CNN +F 3 "" H 5800 4250 60 0000 C CNN + 3 5800 4250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tff_1/tff_1.sub b/library/SubcircuitLibrary/tff_1/tff_1.sub new file mode 100644 index 000000000..c7f567e0c --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/tff_1.sub @@ -0,0 +1,38 @@ +* Subcircuit tff_1 +.subckt tff_1 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ +* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand +* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand +* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and +* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and +* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand +* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4 +a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7 +a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8 +a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends tff_1 \ No newline at end of file diff --git a/library/SubcircuitLibrary/tff_1/tff_1_Previous_Values.xml b/library/SubcircuitLibrary/tff_1/tff_1_Previous_Values.xml new file mode 100644 index 000000000..ab6605eb4 --- /dev/null +++ b/library/SubcircuitLibrary/tff_1/tff_1_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nandd_nandd_andd_andd_nandd_nand \ No newline at end of file diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index e69de29bb..786a6eed9 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -0,0 +1,1092 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74AHC1G4210 +# +DEF 74AHC1G4210 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "74AHC1G4210" 50 -50 60 H V C CNN +F2 "" 0 -150 60 H I C CNN +F3 "" 0 -150 60 H I C CNN +DRAW +S -400 350 450 -550 0 1 0 N +X X1 1 -600 150 200 R 50 50 1 1 I +X X2 2 -600 -100 200 R 50 50 1 1 O +X GND 3 -600 -350 200 R 50 50 1 1 O +X Q 4 650 -350 200 L 50 50 1 1 O +X VCC 5 650 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 74AHC1G4212 +# +DEF 74AHC1G4212 X 0 40 Y Y 1 F N +F0 "X" 0 -350 60 H V C CNN +F1 "74AHC1G4212" 0 250 60 H V C CNN +F2 "" 0 -350 60 H I C CNN +F3 "" 0 -350 60 H I C CNN +DRAW +S -350 200 350 -300 0 1 0 N +X X1 1 -550 100 200 R 50 50 1 1 I +X X2 2 -550 -50 200 R 50 50 1 1 O +X GND 3 -550 -200 200 R 50 50 1 1 O +X Q 4 550 -100 200 L 50 50 1 1 O +X VCC 5 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74HC563 +# +DEF 74HC563 X 0 40 Y Y 1 F N +F0 "X" 0 -700 60 H V C CNN +F1 "74HC563" -50 500 60 H V C CNN +F2 "" 0 -700 60 H I C CNN +F3 "" 0 -700 60 H I C CNN +DRAW +S -350 450 250 -650 0 1 0 N +X OE 1 -550 350 200 R 50 50 1 1 I +X D0 2 -550 250 200 R 50 50 1 1 I +X D1 3 -550 150 200 R 50 50 1 1 I +X D2 4 -550 50 200 R 50 50 1 1 I +X D3 5 -550 -50 200 R 50 50 1 1 I +X D4 6 -550 -150 200 R 50 50 1 1 I +X D5 7 -550 -250 200 R 50 50 1 1 I +X D6 8 -550 -350 200 R 50 50 1 1 I +X D7 9 -550 -450 200 R 50 50 1 1 I +X GND 10 -550 -550 200 R 50 50 1 1 I +X VCC 20 450 350 200 L 50 50 1 1 I +X LE 11 450 -550 200 L 50 50 1 1 I +X Q7 12 450 -450 200 L 50 50 1 1 O +X Q6 13 450 -350 200 L 50 50 1 1 O +X Q5 14 450 -250 200 L 50 50 1 1 O +X Q4 15 450 -150 200 L 50 50 1 1 O +X Q3 16 450 -50 200 L 50 50 1 1 O +X Q2 17 450 50 200 L 50 50 1 1 O +X Q1 18 450 150 200 L 50 50 1 1 O +X Q0 19 450 250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# ICM7555 +# +DEF ICM7555 X 0 40 Y Y 1 F N +F0 "X" 0 -400 60 H V C CNN +F1 "ICM7555" 0 200 60 H V C CNN +F2 "" 0 -400 60 H I C CNN +F3 "" 0 -400 60 H I C CNN +DRAW +S -550 150 750 -350 0 1 0 N +X GND 1 -750 50 200 R 50 50 1 1 O +X TRIGGER_BAR 2 -750 -50 200 R 50 50 1 1 I +X OUTPUT 3 -750 -150 200 R 50 50 1 1 O +X RESET_BAR 4 -750 -250 200 R 50 50 1 1 I +X CONTROL_VOLTAGE 5 950 -250 200 L 50 50 1 1 I +X THRESHOLD 6 950 -150 200 L 50 50 1 1 I +X DISCHARGE 7 950 -50 200 L 50 50 1 1 O +X V+ 8 950 50 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A