Active clock reduction

[t-lohse]

During clock reduction, an enhancement to the analysis is to utilize the memory more efficiently by having different, but still used, clocks map to the same ClockIndex. If we can prove that two clocks are used different places in the system, they can share row and column in the DBM, and save memory. Beyond that, if a clock is only used in a part of the system, the DBM could be scaled down in the other parts of the system.