Baud Rate Clock Bug? #1
Description
I want to Use 250000 Baud Rate. So according to the top of VHDL file explanation, while my I_clk is 50MHz, I set:
I_clk_baud_count <= X"00C8";--means 200
it seems that the tx_clk should be 40us, but it is 40040ns in simulation.
See Simulation Here.
Is it wrong according to the code?and could it cause problem in my UART communication?