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Currently we have found several bugs in open-source instruments working with SystemVerilog.
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We are on the way of reporting them officially.
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To see the bugs and issues we have discovered, please visit our [website](https://deptycheck.github.io/verilog-model/).
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To see the bugs and issues we have discovered, please visit our [site](https://deptycheck.github.io/verilog-model/).
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## Installation
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### Usage
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The generator produces SystemVerilog test designs.
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The generator produces SystemVerilog test designs.
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Each generated file corresponds to a **separate test**.
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- By default, tests are printed to the console, but you can specify a directory to save files using `--to`.
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- Every run produces different tests. You can set the seed manually to make results reproducible with `--seed` (the `--seed` option expects two numbers).
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To see which seeds are actually used, add the `--seed-name` flag to include the seed in file names, and the `--seed-content` flag to print the seed inside the file.
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- Every run produces different tests. You can set the seed manually to make results reproducible with `--seed` (the `--seed` option expects two numbers).
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To see which seeds are actually used, add the `--seed-name` flag to include the seed in filenames, and the `--seed-content` flag to print the seed inside the file.
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