🐞 Bug Input pre is not used in the Verilog code for DflipFlop.

[philipabbey]

Is there an existing issue for this?

• I have searched the existing issues.

Describe the bug

Input pre is not used in the Verilog code for DflipFlop.

module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
    parameter WIDTH = 1;
    output reg [WIDTH-1:0] q, q_inv;
    input clk, a_rst, pre, en;
    input [WIDTH-1:0] d;

    always @ (posedge clk or posedge a_rst)
    if (a_rst) begin
        q <= 'b0;
        q_inv <= 'b1;
    end else if (en == 0) ;
    else begin
        q <= d;
        q_inv <= ~d;
    end
endmodule

This can cause the entire design to be optimised away during synthesis in Xilinx's Vivado, and it took some finding (since I only know VHDL ;-)

Steps to Reproduce

Not used the cv-frontend-vue code base at all, just noted the same mistake has been copied across from the original simulator.

Expected Behavior

The pre input should be used to set the value on reset with a_rst.

The following is a guess at the correction since I don't actually code in Verilog.

    if (a_rst) begin
        q <= pre;
        q_inv <= ~pre;

Screenshots

No response

Is the faced issue/bug related to the Vue simulator?

Yes

Used Vue simulator with or without backend?

None

Is the bug present only on the dev server, the build, or both?

Both

Device Information

Is the bug present only on the dev server, the build, or both?

In truth, no idea. I only note you have copied the mistake across from the original simulator and its there in your source code at https://github.com/CircuitVerse/cv-frontend-vue/blob/main/src/simulator/src/sequential/DflipFlop.js#L151-L152, so its there in at least one of the servers.

Additional Context

CircuitVerse/CircuitVerse#4985

Are you working on this issue?

No