diff --git a/docs/chapter4/8misc.md b/docs/chapter4/8misc.md index 63e14f7..1033ffd 100644 --- a/docs/chapter4/8misc.md +++ b/docs/chapter4/8misc.md @@ -9,6 +9,7 @@ 8. [Unequal Split](#unequal-split) 9. [Flag](#flag) 10. [Two's Complement](#twos-complement) +11. [Force Gate](#force-gate) ## ALU @@ -479,3 +480,59 @@ add 1 + 1 You can verify the behavior of the **Two’s Complement** circuit element in the live circuit embedded below: + +## Force Gate + +The **Force Gate** is a logical circuit element designed to manipulate and control binary data. It enables the user to force specific values onto the inputs of a connected circuit, allowing for custom simulations and testing scenarios. This documentation provides an overview of the Force Gate circuit element in CircuitVerse, its properties, and its usage. + +>Properties that can be customized in the **PROPERTIES** panel include: **Direction, BitWidth** + +![drawing](../images/img_chapter4/4.25.png) + +
Figure 4.25: Relevant attributes for the Force Gate element
+ +Table 4.25: Truth table for a Force Gate + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enable + Input + Output +
0 + 0 + 0 +
0 + 1 + 0 +
1 + 0 + 1 +
1 + 1 + 1 +
+ + \ No newline at end of file diff --git a/docs/images/img_chapter4/4.25.png b/docs/images/img_chapter4/4.25.png new file mode 100644 index 0000000..ed15ba6 Binary files /dev/null and b/docs/images/img_chapter4/4.25.png differ