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+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353273:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3833362e3030384d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3530382e3036364d42:00:00 +eof:1390542424 diff --git a/LAB10.cache/wt/synthesis_details.wdf b/LAB10.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000..78f8d66 --- /dev/null +++ b/LAB10.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/LAB10.cache/wt/webtalk_pa.xml b/LAB10.cache/wt/webtalk_pa.xml index fc79d2c..e0d02b7 100644 --- a/LAB10.cache/wt/webtalk_pa.xml +++ b/LAB10.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -17,31 +17,164 @@ This means code written to parse this file will need to be revisited each subseq - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + - + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
diff --git a/LAB10.cache/wt/xsim.wdf b/LAB10.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/LAB10.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/LAB10.ip_user_files/README.txt b/LAB10.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/LAB10.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/LAB10.runs/.jobs/vrs_config_1.xml b/LAB10.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_10.xml b/LAB10.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_11.xml b/LAB10.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_12.xml b/LAB10.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_13.xml b/LAB10.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_14.xml b/LAB10.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_15.xml b/LAB10.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..69b00d7 --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_16.xml b/LAB10.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_17.xml b/LAB10.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_18.xml b/LAB10.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..c5153ff --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_19.xml b/LAB10.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_2.xml b/LAB10.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..69b00d7 --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_3.xml b/LAB10.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..69b00d7 --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_4.xml b/LAB10.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..b5ddff8 --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_5.xml b/LAB10.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..c5153ff --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_6.xml b/LAB10.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_7.xml b/LAB10.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..c5153ff --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_8.xml b/LAB10.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/.jobs/vrs_config_9.xml b/LAB10.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..80a63dc --- /dev/null +++ b/LAB10.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB10.runs/impl_1/.Vivado_Implementation.queue.rst b/LAB10.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/impl_1/.init_design.begin.rst b/LAB10.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..af3b8df --- /dev/null +++ b/LAB10.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/impl_1/.init_design.end.rst b/LAB10.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/impl_1/.opt_design.begin.rst b/LAB10.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..af3b8df --- /dev/null +++ b/LAB10.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/impl_1/.opt_design.end.rst b/LAB10.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/impl_1/.place_design.begin.rst b/LAB10.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..af3b8df --- /dev/null +++ b/LAB10.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/impl_1/.place_design.end.rst b/LAB10.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/impl_1/.route_design.begin.rst b/LAB10.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..af3b8df --- /dev/null +++ b/LAB10.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/impl_1/.route_design.end.rst b/LAB10.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/impl_1/.vivado.begin.rst b/LAB10.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..4e43045 --- /dev/null +++ b/LAB10.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/impl_1/.vivado.end.rst b/LAB10.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/impl_1/.write_bitstream.begin.rst b/LAB10.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..af3b8df --- /dev/null +++ b/LAB10.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/impl_1/.write_bitstream.end.rst b/LAB10.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/impl_1/ISEWrap.js b/LAB10.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/LAB10.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/LAB10.runs/impl_1/ISEWrap.sh b/LAB10.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/LAB10.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/LAB10.runs/impl_1/Processor.bit b/LAB10.runs/impl_1/Processor.bit new file mode 100644 index 0000000..343f2ae Binary files /dev/null and b/LAB10.runs/impl_1/Processor.bit differ diff --git a/LAB10.runs/impl_1/Processor.tcl b/LAB10.runs/impl_1/Processor.tcl new file mode 100644 index 0000000..65ce21e --- /dev/null +++ b/LAB10.runs/impl_1/Processor.tcl @@ -0,0 +1,171 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {HDL 9-1061} -limit 100000 +set_msg_config -id {HDL 9-1654} -limit 100000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + create_project -in_memory -part xc7a35tcpg236-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.cache/wt} [current_project] + set_property parent.project_path {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.xpr} [current_project] + set_property ip_output_repo {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.cache/ip}} [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1/Processor.dcp}} + read_xdc {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc}} + link_design -top Processor -part xc7a35tcpg236-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force Processor_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file Processor_drc_opted.rpt -pb Processor_drc_opted.pb -rpx Processor_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force Processor_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file Processor_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file Processor_utilization_placed.rpt -pb Processor_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Processor_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force Processor_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file Processor_drc_routed.rpt -pb Processor_drc_routed.pb -rpx Processor_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file Processor_methodology_drc_routed.rpt -pb Processor_methodology_drc_routed.pb -rpx Processor_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file Processor_power_routed.rpt -pb Processor_power_summary_routed.pb -rpx Processor_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file Processor_route_status.rpt -pb Processor_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Processor_timing_summary_routed.rpt -pb Processor_timing_summary_routed.pb -rpx Processor_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Processor_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Processor_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file Processor_bus_skew_routed.rpt -pb Processor_bus_skew_routed.pb -rpx Processor_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force Processor_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force Processor.mmi } + write_bitstream -force Processor.bit + catch {write_debug_probes -quiet -force Processor} + catch {file copy -force Processor.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/LAB10.runs/impl_1/Processor.vdi b/LAB10.runs/impl_1/Processor.vdi new file mode 100644 index 0000000..b3f2fe1 --- /dev/null +++ b/LAB10.runs/impl_1/Processor.vdi @@ -0,0 +1,517 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Jul 29 14:06:45 2022 +# Process ID: 19292 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1 +# Command line: vivado.exe -log Processor.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Processor.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor.vdi +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Processor.tcl -notrace +Command: link_design -top Processor -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +Finished Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 645.871 ; gain = 314.016 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 657.137 ; gain = 11.266 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1b850c94f + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1206.449 ; gain = 549.312 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1b850c94f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1a54f8e79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 8 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 13fc52385 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 1 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 13fc52385 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: ad02a8d3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.102 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.111 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.117 . Memory (MB): peak = 1206.449 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1206.449 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1206.449 ; gain = 560.578 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Processor_drc_opted.rpt -pb Processor_drc_opted.pb -rpx Processor_drc_opted.rpx +Command: report_drc -file Processor_drc_opted.rpt -pb Processor_drc_opted.pb -rpx Processor_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx1/Vivado/2018.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_drc_opted.rpt. +report_drc completed successfully +report_drc: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ab20fe45 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1206.449 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 7957d9d9 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 11b6ede17 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 11b6ede17 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 +Phase 1 Placer Initialization | Checksum: 11b6ede17 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: f2818846 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 2.2 Physical Synthesis In Placer +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1216.516 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------- +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.2 Physical Synthesis In Placer | Checksum: df6e7ea0 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 +Phase 2 Global Placement | Checksum: 94d0b064 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 94d0b064 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10c169849 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 14dd126b5 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 14dd126b5 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: dc516a22 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: fef2ea51 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: fef2ea51 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 +Phase 3 Detail Placement | Checksum: fef2ea51 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 145c7ab5b + +Phase 4.1.1.1 BUFG Insertion +INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: 145c7ab5b + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +INFO: [Place 30-746] Post Placement Timing Summary WNS=4.932. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +Phase 4.1 Post Commit Optimization | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 21d0243db + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21d0243db + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +Ending Placer Task | Checksum: 15a51725a + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +INFO: [Common 17-83] Releasing license: Implementation +47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1236.480 ; gain = 30.031 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1240.867 ; gain = 4.363 +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Processor_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.113 . Memory (MB): peak = 1243.918 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Processor_utilization_placed.rpt -pb Processor_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1243.918 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Processor_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1243.918 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 7b536ee3 ConstDB: 0 ShapeSum: defe0377 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1342.371 ; gain = 98.453 +Post Restoration Checksum: NetGraph: a12456b2 NumContArr: f5240909 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1342.371 ; gain = 98.453 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1348.305 ; gain = 104.387 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1348.305 ; gain = 104.387 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 26b919b55 + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1352.160 ; gain = 108.242 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.936 | TNS=0.000 | WHS=-0.065 | THS=-0.114 | + +Phase 2 Router Initialization | Checksum: 1c2bf44b5 + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 136478cca + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.822 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 1c0baeacd + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.822 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +Phase 4 Rip-up And Reroute | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +Phase 5 Delay and Skew Optimization | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.915 | TNS=0.000 | WHS=0.250 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +Phase 6 Post Hold Fix | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0285418 % + Global Horizontal Routing Utilization = 0.0422957 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 2533fda9d + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=4.915 | TNS=0.000 | WHS=0.250 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 2533fda9d + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:01:01 ; elapsed = 00:00:58 . Memory (MB): peak = 1352.430 ; gain = 108.512 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1352.430 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Processor_drc_routed.rpt -pb Processor_drc_routed.pb -rpx Processor_drc_routed.rpx +Command: report_drc -file Processor_drc_routed.rpt -pb Processor_drc_routed.pb -rpx Processor_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Processor_methodology_drc_routed.rpt -pb Processor_methodology_drc_routed.pb -rpx Processor_methodology_drc_routed.rpx +Command: report_methodology -file Processor_methodology_drc_routed.rpt -pb Processor_methodology_drc_routed.pb -rpx Processor_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Processor_power_routed.rpt -pb Processor_power_summary_routed.pb -rpx Processor_power_routed.rpx +Command: report_power -file Processor_power_routed.rpt -pb Processor_power_summary_routed.pb -rpx Processor_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +77 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Processor_route_status.rpt -pb Processor_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Processor_timing_summary_routed.rpt -pb Processor_timing_summary_routed.pb -rpx Processor_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file Processor_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file Processor_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Processor_bus_skew_routed.rpt -pb Processor_bus_skew_routed.pb -rpx Processor_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force Processor.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./Processor.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +95 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:38 . Memory (MB): peak = 1792.078 ; gain = 406.340 +INFO: [Common 17-206] Exiting Vivado at Fri Jul 29 14:09:53 2022... diff --git a/LAB10.runs/impl_1/Processor_bus_skew_routed.pb b/LAB10.runs/impl_1/Processor_bus_skew_routed.pb new file mode 100644 index 0000000..3390588 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_bus_skew_routed.pb differ diff --git a/LAB10.runs/impl_1/Processor_bus_skew_routed.rpt b/LAB10.runs/impl_1/Processor_bus_skew_routed.rpt new file mode 100644 index 0000000..02e0956 --- /dev/null +++ b/LAB10.runs/impl_1/Processor_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:09:14 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file Processor_bus_skew_routed.rpt -pb Processor_bus_skew_routed.pb -rpx Processor_bus_skew_routed.rpx +| Design : Processor +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.22 2018-03-21 +------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git a/LAB10.runs/impl_1/Processor_bus_skew_routed.rpx b/LAB10.runs/impl_1/Processor_bus_skew_routed.rpx new file mode 100644 index 0000000..e981d9a Binary files /dev/null and b/LAB10.runs/impl_1/Processor_bus_skew_routed.rpx differ diff --git a/LAB10.runs/impl_1/Processor_clock_utilization_routed.rpt b/LAB10.runs/impl_1/Processor_clock_utilization_routed.rpt new file mode 100644 index 0000000..6822cfd --- /dev/null +++ b/LAB10.runs/impl_1/Processor_clock_utilization_routed.rpt @@ -0,0 +1,159 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:09:14 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_clock_utilization -file Processor_clock_utilization_routed.rpt +| Design : Processor +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.22 2018-03-21 +--------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Local Clock Details +5. Clock Regions: Key Resource Utilization +6. Clock Regions : Global Clock Summary +7. Device Cell Placement Summary for Global Clock g0 +8. Clock Region Cell Placement per Global Clock: Region X1Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-------------------------+------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-------------------------+------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 34 | 0 | 10.000 | sys_clk_pin | Clk_In_IBUF_BUFG_inst/O | Clk_In_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-------------------------+------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+--------------------+-------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+--------------------+-------------+ +| src0 | g0 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | 10.000 | sys_clk_pin | Clk_In_IBUF_inst/O | Clk_In_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+--------------------+-------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Local Clock Details +---------------------- + ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+-------------------------+---------------+ +| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+-------------------------+---------------|| +| 0 | FDRE/Q | None | SLICE_X61Y20/AFF | X1Y0 | 16 | 1 | | | Slow_Clk0/Clk_out_reg/Q | Slow_Clk0/CLK - Static - ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+-------------------------+---------------|| +* Local Clocks in this context represents only clocks driven by non-global buffers +** Clock Loads column represents the clock pin loads (pin count) +*** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +5. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 50 | 1500 | 31 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +6. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 1 | ++----+----+----+ + + +7. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+------------------+ +| g0 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | 34 | 0 | 0 | 0 | Clk_In_IBUF_BUFG | ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 34 | ++----+----+-----+ + + +8. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ +| g0 | n/a | BUFG/O | None | 34 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Clk_In_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells Clk_In_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y26 [get_ports Clk_In] + +# Clock net "Clk_In_IBUF_BUFG" driven by instance "Clk_In_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_Clk_In_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_Clk_In_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Clk_In_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_Clk_In_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +#endgroup diff --git a/LAB10.runs/impl_1/Processor_control_sets_placed.rpt b/LAB10.runs/impl_1/Processor_control_sets_placed.rpt new file mode 100644 index 0000000..4884739 --- /dev/null +++ b/LAB10.runs/impl_1/Processor_control_sets_placed.rpt @@ -0,0 +1,73 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:08:11 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file Processor_control_sets_placed.rpt +| Design : Processor +| Device : xc7a35t +-------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 6 | +| Unused register locations in slices containing registers | 12 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 6 | 2 | +| 8 | 2 | +| 10 | 1 | +| 16+ | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 12 | 3 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 62 | 8 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 26 | 7 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++-------------------+------------------------+-----------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++-------------------+------------------------+-----------------------------+------------------+----------------+ +| Slow_Clk0/CLK | | | 1 | 6 | +| Clk_In_IBUF_BUFG | | | 2 | 6 | +| Slow_Clk0/CLK | Program_counter0/En[0] | Reset_IBUF | 2 | 8 | +| Slow_Clk0/CLK | Program_counter0/En[1] | Reset_IBUF | 3 | 8 | +| Slow_Clk0/CLK | Program_counter0/En[2] | Reset_IBUF | 2 | 10 | +| Clk_In_IBUF_BUFG | | Slow_Clk0/count[31]_i_1_n_0 | 8 | 62 | ++-------------------+------------------------+-----------------------------+------------------+----------------+ + + diff --git a/LAB10.runs/impl_1/Processor_drc_opted.pb b/LAB10.runs/impl_1/Processor_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_drc_opted.pb differ diff --git a/LAB10.runs/impl_1/Processor_drc_opted.rpt b/LAB10.runs/impl_1/Processor_drc_opted.rpt new file mode 100644 index 0000000..b06aa57 --- /dev/null +++ b/LAB10.runs/impl_1/Processor_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:08:02 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_drc -file Processor_drc_opted.rpt -pb Processor_drc_opted.pb -rpx Processor_drc_opted.rpx +| Design : Processor +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/LAB10.runs/impl_1/Processor_drc_opted.rpx b/LAB10.runs/impl_1/Processor_drc_opted.rpx new file mode 100644 index 0000000..064818c Binary files /dev/null and b/LAB10.runs/impl_1/Processor_drc_opted.rpx differ diff --git a/LAB10.runs/impl_1/Processor_drc_routed.pb b/LAB10.runs/impl_1/Processor_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_drc_routed.pb differ diff --git a/LAB10.runs/impl_1/Processor_drc_routed.rpt b/LAB10.runs/impl_1/Processor_drc_routed.rpt new file mode 100644 index 0000000..f964c6a --- /dev/null +++ b/LAB10.runs/impl_1/Processor_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:09:11 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_drc -file Processor_drc_routed.rpt -pb Processor_drc_routed.pb -rpx Processor_drc_routed.rpx +| Design : Processor +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/LAB10.runs/impl_1/Processor_drc_routed.rpx b/LAB10.runs/impl_1/Processor_drc_routed.rpx new file mode 100644 index 0000000..47be4d5 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_drc_routed.rpx differ diff --git a/LAB10.runs/impl_1/Processor_io_placed.rpt b/LAB10.runs/impl_1/Processor_io_placed.rpt new file mode 100644 index 0000000..a7f334f --- /dev/null +++ b/LAB10.runs/impl_1/Processor_io_placed.rpt @@ -0,0 +1,280 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:08:11 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_io -file Processor_io_placed.rpt +| Design : Processor +| Device : xc7a35t +| Speed File : -1 +| Package : cpg236 +| Package Version : FINAL 2014-02-19 +| Package Pin Delay Version : VERS. 2.0 2014-02-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 19 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+---------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+---------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C15 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E19 | R7_out[1] | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | OverFlow | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| P1 | Zero | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| R2 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | anode_out[0] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | anode_out[1] | High Range | IO_L11P_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U5 | S_7Seg_out[4] | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U7 | S_7Seg_out[6] | High Range | IO_L19P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U8 | S_7Seg_out[2] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U14 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| U16 | R7_out[0] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | Reset | High Range | IO_L18N_T2_A11_D27_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| U19 | R7_out[2] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V2 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | anode_out[2] | High Range | IO_L11N_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V5 | S_7Seg_out[5] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | S_7Seg_out[3] | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V19 | R7_out[3] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W2 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W4 | anode_out[3] | High Range | IO_L12N_T1_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W5 | Clk_In | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| W6 | S_7Seg_out[1] | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W7 | S_7Seg_out[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| W14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+---------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/LAB10.runs/impl_1/Processor_methodology_drc_routed.pb b/LAB10.runs/impl_1/Processor_methodology_drc_routed.pb new file mode 100644 index 0000000..2a7ba55 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_methodology_drc_routed.pb differ diff --git a/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpt b/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpt new file mode 100644 index 0000000..cc365df --- /dev/null +++ b/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpt @@ -0,0 +1,115 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:09:13 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_methodology -file Processor_methodology_drc_routed.rpt -pb Processor_methodology_drc_routed.pb -rpx Processor_methodology_drc_routed.rpx +| Design : Processor +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 16 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 16 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin Program_counter0/MemorySelect_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin Program_counter0/MemorySelect_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin Program_counter0/MemorySelect_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R21/Q_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R21/Q_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R21/Q_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R21/Q_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R31/Q_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R31/Q_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R31/Q_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R31/Q_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R71/Q_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R71/Q_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R71/Q_reg[1]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R71/Q_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin Register_bank0/R71/Q_reg[3]/C is not reached by a timing clock +Related violations: + + diff --git a/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpx b/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpx new file mode 100644 index 0000000..394d73b Binary files /dev/null and b/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpx differ diff --git a/LAB10.runs/impl_1/Processor_opt.dcp b/LAB10.runs/impl_1/Processor_opt.dcp new file mode 100644 index 0000000..26f3fb4 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_opt.dcp differ diff --git a/LAB10.runs/impl_1/Processor_placed.dcp b/LAB10.runs/impl_1/Processor_placed.dcp new file mode 100644 index 0000000..69788ac Binary files /dev/null and b/LAB10.runs/impl_1/Processor_placed.dcp differ diff --git a/LAB10.runs/impl_1/Processor_power_routed.rpt b/LAB10.runs/impl_1/Processor_power_routed.rpt new file mode 100644 index 0000000..f815333 --- /dev/null +++ b/LAB10.runs/impl_1/Processor_power_routed.rpt @@ -0,0 +1,155 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:09:14 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_power -file Processor_power_routed.rpt -pb Processor_power_summary_routed.pb -rpx Processor_power_routed.rpx +| Design : Processor +| Device : xc7a35tcpg236-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.070 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.001 | +| Device Static (W) | 0.068 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 84.7 | +| Junction Temperature (C) | 25.3 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | <0.001 | 3 | --- | --- | +| Slice Logic | <0.001 | 132 | --- | --- | +| LUT as Logic | <0.001 | 50 | 20800 | 0.24 | +| CARRY4 | <0.001 | 8 | 8150 | 0.10 | +| Register | <0.001 | 50 | 41600 | 0.12 | +| Others | 0.000 | 6 | --- | --- | +| Signals | <0.001 | 121 | --- | --- | +| I/O | <0.001 | 19 | 106 | 17.92 | +| Static Power | 0.068 | | | | +| Total | 0.070 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.011 | 0.001 | 0.010 | +| Vccaux | 1.800 | 0.013 | 0.000 | 0.013 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------------+--------+-----------------+ +| sys_clk_pin | Clk_In | 10.0 | ++-------------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------------------+-----------+ +| Name | Power (W) | ++------------------------+-----------+ +| Processor | 0.001 | +| Mux_8way_4bit1 | <0.001 | +| Decoder_3_to_8_0 | <0.001 | +| Decoder_2_to_4_0 | <0.001 | +| Program_counter0 | <0.001 | +| Register_bank0 | <0.001 | +| R21 | 0.000 | +| R31 | <0.001 | +| R71 | <0.001 | +| Slow_Clk0 | <0.001 | ++------------------------+-----------+ + + diff --git a/LAB10.runs/impl_1/Processor_power_routed.rpx b/LAB10.runs/impl_1/Processor_power_routed.rpx new file mode 100644 index 0000000..9428696 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_power_routed.rpx differ diff --git a/LAB10.runs/impl_1/Processor_power_summary_routed.pb b/LAB10.runs/impl_1/Processor_power_summary_routed.pb new file mode 100644 index 0000000..7704bbe Binary files /dev/null and b/LAB10.runs/impl_1/Processor_power_summary_routed.pb differ diff --git a/LAB10.runs/impl_1/Processor_route_status.pb b/LAB10.runs/impl_1/Processor_route_status.pb new file mode 100644 index 0000000..618d244 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_route_status.pb differ diff --git a/LAB10.runs/impl_1/Processor_route_status.rpt b/LAB10.runs/impl_1/Processor_route_status.rpt new file mode 100644 index 0000000..cc938f8 --- /dev/null +++ b/LAB10.runs/impl_1/Processor_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 181 : + # of nets not needing routing.......... : 56 : + # of internally routed nets........ : 56 : + # of routable nets..................... : 125 : + # of fully routed nets............. : 125 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/LAB10.runs/impl_1/Processor_routed.dcp b/LAB10.runs/impl_1/Processor_routed.dcp new file mode 100644 index 0000000..32e6ba8 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_routed.dcp differ diff --git a/LAB10.runs/impl_1/Processor_timing_summary_routed.pb b/LAB10.runs/impl_1/Processor_timing_summary_routed.pb new file mode 100644 index 0000000..751fea6 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_timing_summary_routed.pb differ diff --git a/LAB10.runs/impl_1/Processor_timing_summary_routed.rpt b/LAB10.runs/impl_1/Processor_timing_summary_routed.rpt new file mode 100644 index 0000000..cce2262 --- /dev/null +++ b/LAB10.runs/impl_1/Processor_timing_summary_routed.rpt @@ -0,0 +1,1373 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:09:14 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file Processor_timing_summary_routed.rpt -pb Processor_timing_summary_routed.pb -rpx Processor_timing_summary_routed.rpx -warn_on_violation +| Design : Processor +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.22 2018-03-21 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 16 register/latch pins with no clock driven by root clock pin: Slow_Clk0/Clk_out_reg/Q (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 42 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 13 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 4.975 0.000 0 65 0.265 0.000 0 65 4.500 0.000 0 35 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +sys_clk_pin {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +sys_clk_pin 4.975 0.000 0 65 0.265 0.000 0 65 4.500 0.000 0 35 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_clk_pin + To Clock: sys_clk_pin + +Setup : 0 Failing Endpoints, Worst Slack 4.975ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.265ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.975ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[1]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.466ns (logic 1.086ns (24.319%) route 3.380ns (75.681%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.298ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 1.051 9.616 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.511 14.852 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[1]/C + clock pessimism 0.298 15.150 + clock uncertainty -0.035 15.115 + SLICE_X60Y16 FDRE (Setup_fdre_C_R) -0.524 14.591 Slow_Clk0/count_reg[1] + ------------------------------------------------------------------- + required time 14.591 + arrival time -9.616 + ------------------------------------------------------------------- + slack 4.975 + +Slack (MET) : 4.975ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[2]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.466ns (logic 1.086ns (24.319%) route 3.380ns (75.681%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.298ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 1.051 9.616 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[2]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.511 14.852 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[2]/C + clock pessimism 0.298 15.150 + clock uncertainty -0.035 15.115 + SLICE_X60Y16 FDRE (Setup_fdre_C_R) -0.524 14.591 Slow_Clk0/count_reg[2] + ------------------------------------------------------------------- + required time 14.591 + arrival time -9.616 + ------------------------------------------------------------------- + slack 4.975 + +Slack (MET) : 4.975ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[3]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.466ns (logic 1.086ns (24.319%) route 3.380ns (75.681%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.298ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 1.051 9.616 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[3]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.511 14.852 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[3]/C + clock pessimism 0.298 15.150 + clock uncertainty -0.035 15.115 + SLICE_X60Y16 FDRE (Setup_fdre_C_R) -0.524 14.591 Slow_Clk0/count_reg[3] + ------------------------------------------------------------------- + required time 14.591 + arrival time -9.616 + ------------------------------------------------------------------- + slack 4.975 + +Slack (MET) : 4.975ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[4]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.466ns (logic 1.086ns (24.319%) route 3.380ns (75.681%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.852ns = ( 14.852 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.298ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 1.051 9.616 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.511 14.852 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + clock pessimism 0.298 15.150 + clock uncertainty -0.035 15.115 + SLICE_X60Y16 FDRE (Setup_fdre_C_R) -0.524 14.591 Slow_Clk0/count_reg[4] + ------------------------------------------------------------------- + required time 14.591 + arrival time -9.616 + ------------------------------------------------------------------- + slack 4.975 + +Slack (MET) : 5.042ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[5]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.374ns (logic 1.086ns (24.830%) route 3.288ns (75.170%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: -0.025ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.851ns = ( 14.851 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.274ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 0.959 9.524 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[5]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.510 14.851 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[5]/C + clock pessimism 0.274 15.125 + clock uncertainty -0.035 15.090 + SLICE_X60Y17 FDRE (Setup_fdre_C_R) -0.524 14.566 Slow_Clk0/count_reg[5] + ------------------------------------------------------------------- + required time 14.566 + arrival time -9.524 + ------------------------------------------------------------------- + slack 5.042 + +Slack (MET) : 5.042ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[6]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.374ns (logic 1.086ns (24.830%) route 3.288ns (75.170%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: -0.025ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.851ns = ( 14.851 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.274ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 0.959 9.524 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[6]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.510 14.851 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[6]/C + clock pessimism 0.274 15.125 + clock uncertainty -0.035 15.090 + SLICE_X60Y17 FDRE (Setup_fdre_C_R) -0.524 14.566 Slow_Clk0/count_reg[6] + ------------------------------------------------------------------- + required time 14.566 + arrival time -9.524 + ------------------------------------------------------------------- + slack 5.042 + +Slack (MET) : 5.042ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[7]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.374ns (logic 1.086ns (24.830%) route 3.288ns (75.170%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: -0.025ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.851ns = ( 14.851 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.274ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 0.959 9.524 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[7]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.510 14.851 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[7]/C + clock pessimism 0.274 15.125 + clock uncertainty -0.035 15.090 + SLICE_X60Y17 FDRE (Setup_fdre_C_R) -0.524 14.566 Slow_Clk0/count_reg[7] + ------------------------------------------------------------------- + required time 14.566 + arrival time -9.524 + ------------------------------------------------------------------- + slack 5.042 + +Slack (MET) : 5.042ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[8]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.374ns (logic 1.086ns (24.830%) route 3.288ns (75.170%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: -0.025ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.851ns = ( 14.851 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.274ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 0.959 9.524 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[8]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.510 14.851 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[8]/C + clock pessimism 0.274 15.125 + clock uncertainty -0.035 15.090 + SLICE_X60Y17 FDRE (Setup_fdre_C_R) -0.524 14.566 Slow_Clk0/count_reg[8] + ------------------------------------------------------------------- + required time 14.566 + arrival time -9.524 + ------------------------------------------------------------------- + slack 5.042 + +Slack (MET) : 5.089ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[10]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.325ns (logic 1.086ns (25.112%) route 3.239ns (74.888%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: -0.027ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.274ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 0.910 9.475 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y18 FDRE r Slow_Clk0/count_reg[10]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.508 14.849 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y18 FDRE r Slow_Clk0/count_reg[10]/C + clock pessimism 0.274 15.123 + clock uncertainty -0.035 15.088 + SLICE_X60Y18 FDRE (Setup_fdre_C_R) -0.524 14.564 Slow_Clk0/count_reg[10] + ------------------------------------------------------------------- + required time 14.564 + arrival time -9.475 + ------------------------------------------------------------------- + slack 5.089 + +Slack (MET) : 5.089ns (required time - arrival time) + Source: Slow_Clk0/count_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[11]/R + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 4.325ns (logic 1.086ns (25.112%) route 3.239ns (74.888%)) + Logic Levels: 3 (LUT4=2 LUT5=1) + Clock Path Skew: -0.027ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.849ns = ( 14.849 - 10.000 ) + Source Clock Delay (SCD): 5.150ns + Clock Pessimism Removal (CPR): 0.274ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.629 5.150 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.518 5.668 f Slow_Clk0/count_reg[4]/Q + net (fo=2, routed) 0.809 6.478 Slow_Clk0/count[4] + SLICE_X61Y17 LUT4 (Prop_lut4_I1_O) 0.124 6.602 f Slow_Clk0/count[31]_i_7/O + net (fo=1, routed) 0.553 7.155 Slow_Clk0/count[31]_i_7_n_0 + SLICE_X61Y16 LUT5 (Prop_lut5_I4_O) 0.118 7.273 f Slow_Clk0/count[31]_i_3/O + net (fo=3, routed) 0.966 8.239 Slow_Clk0/count[31]_i_3_n_0 + SLICE_X61Y20 LUT4 (Prop_lut4_I1_O) 0.326 8.565 r Slow_Clk0/count[31]_i_1/O + net (fo=31, routed) 0.910 9.475 Slow_Clk0/count[31]_i_1_n_0 + SLICE_X60Y18 FDRE r Slow_Clk0/count_reg[11]/R + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r Clk_In (IN) + net (fo=0) 0.000 10.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r Clk_In_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 1.508 14.849 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y18 FDRE r Slow_Clk0/count_reg[11]/C + clock pessimism 0.274 15.123 + clock uncertainty -0.035 15.088 + SLICE_X60Y18 FDRE (Setup_fdre_C_R) -0.524 14.564 Slow_Clk0/count_reg[11] + ------------------------------------------------------------------- + required time 14.564 + arrival time -9.475 + ------------------------------------------------------------------- + slack 5.089 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.265ns (arrival time - required time) + Source: Slow_Clk0/count_reg[23]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.399ns (logic 0.274ns (68.589%) route 0.125ns (31.411%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.979ns + Source Clock Delay (SCD): 1.467ns + Clock Pessimism Removal (CPR): 0.512ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.584 1.467 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y21 FDRE r Slow_Clk0/count_reg[23]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y21 FDRE (Prop_fdre_C_Q) 0.164 1.631 r Slow_Clk0/count_reg[23]/Q + net (fo=2, routed) 0.125 1.757 Slow_Clk0/count[23] + SLICE_X60Y21 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.110 1.867 r Slow_Clk0/count0_carry__4/O[2] + net (fo=1, routed) 0.000 1.867 Slow_Clk0/data0[23] + SLICE_X60Y21 FDRE r Slow_Clk0/count_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.852 1.979 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y21 FDRE r Slow_Clk0/count_reg[23]/C + clock pessimism -0.512 1.467 + SLICE_X60Y21 FDRE (Hold_fdre_C_D) 0.134 1.601 Slow_Clk0/count_reg[23] + ------------------------------------------------------------------- + required time -1.601 + arrival time 1.867 + ------------------------------------------------------------------- + slack 0.265 + +Slack (MET) : 0.265ns (arrival time - required time) + Source: Slow_Clk0/count_reg[19]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.399ns (logic 0.274ns (68.589%) route 0.125ns (31.411%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.980ns + Source Clock Delay (SCD): 1.468ns + Clock Pessimism Removal (CPR): 0.512ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.585 1.468 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y20 FDRE r Slow_Clk0/count_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y20 FDRE (Prop_fdre_C_Q) 0.164 1.632 r Slow_Clk0/count_reg[19]/Q + net (fo=2, routed) 0.125 1.758 Slow_Clk0/count[19] + SLICE_X60Y20 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.110 1.868 r Slow_Clk0/count0_carry__3/O[2] + net (fo=1, routed) 0.000 1.868 Slow_Clk0/data0[19] + SLICE_X60Y20 FDRE r Slow_Clk0/count_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.853 1.980 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y20 FDRE r Slow_Clk0/count_reg[19]/C + clock pessimism -0.512 1.468 + SLICE_X60Y20 FDRE (Hold_fdre_C_D) 0.134 1.602 Slow_Clk0/count_reg[19] + ------------------------------------------------------------------- + required time -1.602 + arrival time 1.868 + ------------------------------------------------------------------- + slack 0.265 + +Slack (MET) : 0.265ns (arrival time - required time) + Source: Slow_Clk0/count_reg[7]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.399ns (logic 0.274ns (68.589%) route 0.125ns (31.411%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.983ns + Source Clock Delay (SCD): 1.471ns + Clock Pessimism Removal (CPR): 0.512ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.588 1.471 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y17 FDRE (Prop_fdre_C_Q) 0.164 1.635 r Slow_Clk0/count_reg[7]/Q + net (fo=2, routed) 0.125 1.761 Slow_Clk0/count[7] + SLICE_X60Y17 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.110 1.871 r Slow_Clk0/count0_carry__0/O[2] + net (fo=1, routed) 0.000 1.871 Slow_Clk0/data0[7] + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.856 1.983 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y17 FDRE r Slow_Clk0/count_reg[7]/C + clock pessimism -0.512 1.471 + SLICE_X60Y17 FDRE (Hold_fdre_C_D) 0.134 1.605 Slow_Clk0/count_reg[7] + ------------------------------------------------------------------- + required time -1.605 + arrival time 1.871 + ------------------------------------------------------------------- + slack 0.265 + +Slack (MET) : 0.265ns (arrival time - required time) + Source: Slow_Clk0/count_reg[31]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.399ns (logic 0.274ns (68.589%) route 0.125ns (31.411%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.976ns + Source Clock Delay (SCD): 1.465ns + Clock Pessimism Removal (CPR): 0.511ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.582 1.465 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y23 FDRE r Slow_Clk0/count_reg[31]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y23 FDRE (Prop_fdre_C_Q) 0.164 1.629 r Slow_Clk0/count_reg[31]/Q + net (fo=2, routed) 0.125 1.755 Slow_Clk0/count[31] + SLICE_X60Y23 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.110 1.865 r Slow_Clk0/count0_carry__6/O[2] + net (fo=1, routed) 0.000 1.865 Slow_Clk0/data0[31] + SLICE_X60Y23 FDRE r Slow_Clk0/count_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.849 1.976 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y23 FDRE r Slow_Clk0/count_reg[31]/C + clock pessimism -0.511 1.465 + SLICE_X60Y23 FDRE (Hold_fdre_C_D) 0.134 1.599 Slow_Clk0/count_reg[31] + ------------------------------------------------------------------- + required time -1.599 + arrival time 1.865 + ------------------------------------------------------------------- + slack 0.265 + +Slack (MET) : 0.266ns (arrival time - required time) + Source: Slow_Clk0/count_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.400ns (logic 0.274ns (68.560%) route 0.126ns (31.440%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.984ns + Source Clock Delay (SCD): 1.472ns + Clock Pessimism Removal (CPR): 0.512ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.589 1.472 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y16 FDRE (Prop_fdre_C_Q) 0.164 1.636 r Slow_Clk0/count_reg[3]/Q + net (fo=2, routed) 0.126 1.762 Slow_Clk0/count[3] + SLICE_X60Y16 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.110 1.872 r Slow_Clk0/count0_carry/O[2] + net (fo=1, routed) 0.000 1.872 Slow_Clk0/data0[3] + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.857 1.984 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[3]/C + clock pessimism -0.512 1.472 + SLICE_X60Y16 FDRE (Hold_fdre_C_D) 0.134 1.606 Slow_Clk0/count_reg[3] + ------------------------------------------------------------------- + required time -1.606 + arrival time 1.872 + ------------------------------------------------------------------- + slack 0.266 + +Slack (MET) : 0.267ns (arrival time - required time) + Source: Slow_Clk0/count_reg[11]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.401ns (logic 0.274ns (68.412%) route 0.127ns (31.588%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.982ns + Source Clock Delay (SCD): 1.470ns + Clock Pessimism Removal (CPR): 0.512ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.587 1.470 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y18 FDRE r Slow_Clk0/count_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y18 FDRE (Prop_fdre_C_Q) 0.164 1.634 r Slow_Clk0/count_reg[11]/Q + net (fo=2, routed) 0.127 1.761 Slow_Clk0/count[11] + SLICE_X60Y18 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.110 1.871 r Slow_Clk0/count0_carry__1/O[2] + net (fo=1, routed) 0.000 1.871 Slow_Clk0/data0[11] + SLICE_X60Y18 FDRE r Slow_Clk0/count_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.855 1.982 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y18 FDRE r Slow_Clk0/count_reg[11]/C + clock pessimism -0.512 1.470 + SLICE_X60Y18 FDRE (Hold_fdre_C_D) 0.134 1.604 Slow_Clk0/count_reg[11] + ------------------------------------------------------------------- + required time -1.604 + arrival time 1.871 + ------------------------------------------------------------------- + slack 0.267 + +Slack (MET) : 0.282ns (arrival time - required time) + Source: Slow_Clk0/count_reg[18]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/Clk_status_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.254ns (65.649%) route 0.133ns (34.351%)) + Logic Levels: 2 (LUT5=2) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.980ns + Source Clock Delay (SCD): 1.468ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.585 1.468 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y20 FDRE r Slow_Clk0/count_reg[18]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y20 FDRE (Prop_fdre_C_Q) 0.164 1.632 f Slow_Clk0/count_reg[18]/Q + net (fo=2, routed) 0.060 1.692 Slow_Clk0/count[18] + SLICE_X61Y20 LUT5 (Prop_lut5_I1_O) 0.045 1.737 r Slow_Clk0/count[31]_i_5/O + net (fo=3, routed) 0.073 1.810 Slow_Clk0/count[31]_i_5_n_0 + SLICE_X61Y20 LUT5 (Prop_lut5_I0_O) 0.045 1.855 r Slow_Clk0/Clk_status_i_1/O + net (fo=1, routed) 0.000 1.855 Slow_Clk0/Clk_status_i_1_n_0 + SLICE_X61Y20 FDRE r Slow_Clk0/Clk_status_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.853 1.980 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X61Y20 FDRE r Slow_Clk0/Clk_status_reg/C + clock pessimism -0.499 1.481 + SLICE_X61Y20 FDRE (Hold_fdre_C_D) 0.092 1.573 Slow_Clk0/Clk_status_reg + ------------------------------------------------------------------- + required time -1.573 + arrival time 1.855 + ------------------------------------------------------------------- + slack 0.282 + +Slack (MET) : 0.283ns (arrival time - required time) + Source: Slow_Clk0/count_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.430ns (logic 0.299ns (69.611%) route 0.131ns (30.389%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.984ns + Source Clock Delay (SCD): 1.472ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.589 1.472 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X61Y16 FDRE r Slow_Clk0/count_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X61Y16 FDRE (Prop_fdre_C_Q) 0.141 1.613 r Slow_Clk0/count_reg[0]/Q + net (fo=3, routed) 0.131 1.744 Slow_Clk0/count[0] + SLICE_X60Y16 CARRY4 (Prop_carry4_CYINIT_O[0]) + 0.158 1.902 r Slow_Clk0/count0_carry/O[0] + net (fo=1, routed) 0.000 1.902 Slow_Clk0/data0[1] + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.857 1.984 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y16 FDRE r Slow_Clk0/count_reg[1]/C + clock pessimism -0.499 1.485 + SLICE_X60Y16 FDRE (Hold_fdre_C_D) 0.134 1.619 Slow_Clk0/count_reg[1] + ------------------------------------------------------------------- + required time -1.619 + arrival time 1.902 + ------------------------------------------------------------------- + slack 0.283 + +Slack (MET) : 0.284ns (arrival time - required time) + Source: Slow_Clk0/count_reg[18]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/Clk_out_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.388ns (logic 0.254ns (65.480%) route 0.134ns (34.520%)) + Logic Levels: 2 (LUT5=1 LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.980ns + Source Clock Delay (SCD): 1.468ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.585 1.468 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y20 FDRE r Slow_Clk0/count_reg[18]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y20 FDRE (Prop_fdre_C_Q) 0.164 1.632 f Slow_Clk0/count_reg[18]/Q + net (fo=2, routed) 0.060 1.692 Slow_Clk0/count[18] + SLICE_X61Y20 LUT5 (Prop_lut5_I1_O) 0.045 1.737 r Slow_Clk0/count[31]_i_5/O + net (fo=3, routed) 0.074 1.811 Slow_Clk0/count[31]_i_5_n_0 + SLICE_X61Y20 LUT6 (Prop_lut6_I4_O) 0.045 1.856 r Slow_Clk0/Clk_out_i_1/O + net (fo=1, routed) 0.000 1.856 Slow_Clk0/Clk_out_i_1_n_0 + SLICE_X61Y20 FDRE r Slow_Clk0/Clk_out_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.853 1.980 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X61Y20 FDRE r Slow_Clk0/Clk_out_reg/C + clock pessimism -0.499 1.481 + SLICE_X61Y20 FDRE (Hold_fdre_C_D) 0.091 1.572 Slow_Clk0/Clk_out_reg + ------------------------------------------------------------------- + required time -1.572 + arrival time 1.856 + ------------------------------------------------------------------- + slack 0.284 + +Slack (MET) : 0.301ns (arrival time - required time) + Source: Slow_Clk0/count_reg[23]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: Slow_Clk0/count_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.310ns (71.185%) route 0.125ns (28.815%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.979ns + Source Clock Delay (SCD): 1.467ns + Clock Pessimism Removal (CPR): 0.512ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.584 1.467 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y21 FDRE r Slow_Clk0/count_reg[23]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y21 FDRE (Prop_fdre_C_Q) 0.164 1.631 r Slow_Clk0/count_reg[23]/Q + net (fo=2, routed) 0.125 1.757 Slow_Clk0/count[23] + SLICE_X60Y21 CARRY4 (Prop_carry4_S[2]_O[3]) + 0.146 1.903 r Slow_Clk0/count0_carry__4/O[3] + net (fo=1, routed) 0.000 1.903 Slow_Clk0/data0[24] + SLICE_X60Y21 FDRE r Slow_Clk0/count_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r Clk_In (IN) + net (fo=0) 0.000 0.000 Clk_In + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r Clk_In_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 Clk_In_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r Clk_In_IBUF_BUFG_inst/O + net (fo=34, routed) 0.852 1.979 Slow_Clk0/Clk_In_IBUF_BUFG + SLICE_X60Y21 FDRE r Slow_Clk0/count_reg[24]/C + clock pessimism -0.512 1.467 + SLICE_X60Y21 FDRE (Hold_fdre_C_D) 0.134 1.601 Slow_Clk0/count_reg[24] + ------------------------------------------------------------------- + required time -1.601 + arrival time 1.903 + ------------------------------------------------------------------- + slack 0.301 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_clk_pin +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { Clk_In } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 Clk_In_IBUF_BUFG_inst/I +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X61Y20 Slow_Clk0/Clk_out_reg/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X61Y20 Slow_Clk0/Clk_status_reg/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X61Y16 Slow_Clk0/count_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X60Y18 Slow_Clk0/count_reg[10]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X60Y18 Slow_Clk0/count_reg[11]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X60Y18 Slow_Clk0/count_reg[12]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X60Y19 Slow_Clk0/count_reg[13]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X60Y19 Slow_Clk0/count_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X60Y19 Slow_Clk0/count_reg[15]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X61Y20 Slow_Clk0/Clk_out_reg/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X61Y20 Slow_Clk0/Clk_status_reg/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y19 Slow_Clk0/count_reg[13]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y19 Slow_Clk0/count_reg[14]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y19 Slow_Clk0/count_reg[15]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y19 Slow_Clk0/count_reg[16]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y20 Slow_Clk0/count_reg[17]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y20 Slow_Clk0/count_reg[18]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y20 Slow_Clk0/count_reg[19]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y20 Slow_Clk0/count_reg[20]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X61Y16 Slow_Clk0/count_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y16 Slow_Clk0/count_reg[1]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y22 Slow_Clk0/count_reg[25]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y22 Slow_Clk0/count_reg[26]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y22 Slow_Clk0/count_reg[27]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y22 Slow_Clk0/count_reg[28]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y23 Slow_Clk0/count_reg[29]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y16 Slow_Clk0/count_reg[2]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y23 Slow_Clk0/count_reg[30]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X60Y23 Slow_Clk0/count_reg[31]/C + + + diff --git a/LAB10.runs/impl_1/Processor_timing_summary_routed.rpx b/LAB10.runs/impl_1/Processor_timing_summary_routed.rpx new file mode 100644 index 0000000..6816cff Binary files /dev/null and b/LAB10.runs/impl_1/Processor_timing_summary_routed.rpx differ diff --git a/LAB10.runs/impl_1/Processor_utilization_placed.pb b/LAB10.runs/impl_1/Processor_utilization_placed.pb new file mode 100644 index 0000000..27bf2a0 Binary files /dev/null and b/LAB10.runs/impl_1/Processor_utilization_placed.pb differ diff --git a/LAB10.runs/impl_1/Processor_utilization_placed.rpt b/LAB10.runs/impl_1/Processor_utilization_placed.rpt new file mode 100644 index 0000000..7d092fb --- /dev/null +++ b/LAB10.runs/impl_1/Processor_utilization_placed.rpt @@ -0,0 +1,208 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:08:11 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_utilization -file Processor_utilization_placed.rpt -pb Processor_utilization_placed.pb +| Design : Processor +| Device : 7a35tcpg236-1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 50 | 0 | 20800 | 0.24 | +| LUT as Logic | 50 | 0 | 20800 | 0.24 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 50 | 0 | 41600 | 0.12 | +| Register as Flip Flop | 50 | 0 | 41600 | 0.12 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 50 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 24 | 0 | 8150 | 0.29 | +| SLICEL | 16 | 0 | | | +| SLICEM | 8 | 0 | | | +| LUT as Logic | 50 | 0 | 20800 | 0.24 | +| using O5 output only | 0 | | | | +| using O6 output only | 32 | | | | +| using O5 and O6 | 18 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 6 | 0 | 20800 | 0.03 | +| fully used LUT-FF pairs | 1 | | | | +| LUT-FF pairs with one unused LUT output | 3 | | | | +| LUT-FF pairs with one unused Flip Flop | 5 | | | | +| Unique Control Sets | 6 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 19 | 19 | 106 | 17.92 | +| IOB Master Pads | 7 | | | | +| IOB Slave Pads | 12 | | | | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 50 | Flop & Latch | +| LUT4 | 22 | LUT | +| OBUF | 17 | IO | +| LUT3 | 15 | LUT | +| LUT5 | 11 | LUT | +| LUT6 | 10 | LUT | +| LUT2 | 9 | LUT | +| CARRY4 | 8 | CarryLogic | +| IBUF | 2 | IO | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/LAB10.runs/impl_1/gen_run.xml b/LAB10.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..840c3e7 --- /dev/null +++ b/LAB10.runs/impl_1/gen_run.xml @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LAB10.runs/impl_1/htr.txt b/LAB10.runs/impl_1/htr.txt new file mode 100644 index 0000000..f8be692 --- /dev/null +++ b/LAB10.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log Processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Processor.tcl -notrace diff --git a/LAB10.runs/impl_1/init_design.pb b/LAB10.runs/impl_1/init_design.pb new file mode 100644 index 0000000..fecd71e Binary files /dev/null and b/LAB10.runs/impl_1/init_design.pb differ diff --git a/LAB10.runs/impl_1/opt_design.pb b/LAB10.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..a1fa884 Binary files /dev/null and b/LAB10.runs/impl_1/opt_design.pb differ diff --git a/LAB10.runs/impl_1/place_design.pb b/LAB10.runs/impl_1/place_design.pb new file mode 100644 index 0000000..5d5513c Binary files /dev/null and b/LAB10.runs/impl_1/place_design.pb differ diff --git a/LAB10.runs/impl_1/project.wdf b/LAB10.runs/impl_1/project.wdf new file mode 100644 index 0000000..87167cc --- /dev/null +++ b/LAB10.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ +version:1 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--- /dev/null +++ b/LAB10.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64;C:/Xilinx1/Vivado/2018.2/bin;"; +} else { + PathVal = "C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64;C:/Xilinx1/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log Processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Processor.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/LAB10.runs/impl_1/runme.bat b/LAB10.runs/impl_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/LAB10.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LAB10.runs/impl_1/runme.log b/LAB10.runs/impl_1/runme.log new file mode 100644 index 0000000..fd32b60 --- /dev/null +++ b/LAB10.runs/impl_1/runme.log @@ -0,0 +1,516 @@ + +*** Running vivado + with args -log Processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Processor.tcl -notrace + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source Processor.tcl -notrace +Command: link_design -top Processor -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +Finished Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 645.871 ; gain = 314.016 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 657.137 ; gain = 11.266 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1b850c94f + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1206.449 ; gain = 549.312 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1b850c94f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1a54f8e79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 8 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 13fc52385 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 1 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 13fc52385 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: ad02a8d3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.102 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.111 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.117 . Memory (MB): peak = 1206.449 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1206.449 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 13d691068 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1206.449 ; gain = 560.578 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1206.449 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Processor_drc_opted.rpt -pb Processor_drc_opted.pb -rpx Processor_drc_opted.rpx +Command: report_drc -file Processor_drc_opted.rpt -pb Processor_drc_opted.pb -rpx Processor_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx1/Vivado/2018.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_drc_opted.rpt. +report_drc completed successfully +report_drc: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ab20fe45 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1206.449 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1206.449 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 7957d9d9 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 11b6ede17 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 11b6ede17 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 +Phase 1 Placer Initialization | Checksum: 11b6ede17 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: f2818846 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 2.2 Physical Synthesis In Placer +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1216.516 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------- +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.2 Physical Synthesis In Placer | Checksum: df6e7ea0 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 +Phase 2 Global Placement | Checksum: 94d0b064 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 94d0b064 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10c169849 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 14dd126b5 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 14dd126b5 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: dc516a22 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: fef2ea51 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: fef2ea51 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 +Phase 3 Detail Placement | Checksum: fef2ea51 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1216.516 ; gain = 10.066 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 145c7ab5b + +Phase 4.1.1.1 BUFG Insertion +INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: 145c7ab5b + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +INFO: [Place 30-746] Post Placement Timing Summary WNS=4.932. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +Phase 4.1 Post Commit Optimization | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1a9cf03c7 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 21d0243db + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21d0243db + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +Ending Placer Task | Checksum: 15a51725a + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1236.480 ; gain = 30.031 +INFO: [Common 17-83] Releasing license: Implementation +47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 1236.480 ; gain = 30.031 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1240.867 ; gain = 4.363 +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Processor_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.113 . Memory (MB): peak = 1243.918 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Processor_utilization_placed.rpt -pb Processor_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1243.918 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Processor_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1243.918 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 7b536ee3 ConstDB: 0 ShapeSum: defe0377 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1342.371 ; gain = 98.453 +Post Restoration Checksum: NetGraph: a12456b2 NumContArr: f5240909 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1342.371 ; gain = 98.453 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1348.305 ; gain = 104.387 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 196485fbb + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1348.305 ; gain = 104.387 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 26b919b55 + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1352.160 ; gain = 108.242 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.936 | TNS=0.000 | WHS=-0.065 | THS=-0.114 | + +Phase 2 Router Initialization | Checksum: 1c2bf44b5 + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 136478cca + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:55 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.822 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 1c0baeacd + +Time (s): cpu = 00:00:56 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.822 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +Phase 4 Rip-up And Reroute | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +Phase 5 Delay and Skew Optimization | Checksum: 2212318ac + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=4.915 | TNS=0.000 | WHS=0.250 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 +Phase 6 Post Hold Fix | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0285418 % + Global Horizontal Routing Utilization = 0.0422957 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.160 ; gain = 108.242 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 265f33538 + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 2533fda9d + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=4.915 | TNS=0.000 | WHS=0.250 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 2533fda9d + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:57 ; elapsed = 00:00:56 . Memory (MB): peak = 1352.430 ; gain = 108.512 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:01:01 ; elapsed = 00:00:58 . Memory (MB): peak = 1352.430 ; gain = 108.512 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1352.430 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Processor_drc_routed.rpt -pb Processor_drc_routed.pb -rpx Processor_drc_routed.rpx +Command: report_drc -file Processor_drc_routed.rpt -pb Processor_drc_routed.pb -rpx Processor_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Processor_methodology_drc_routed.rpt -pb Processor_methodology_drc_routed.pb -rpx Processor_methodology_drc_routed.rpx +Command: report_methodology -file Processor_methodology_drc_routed.rpt -pb Processor_methodology_drc_routed.pb -rpx Processor_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Processor_power_routed.rpt -pb Processor_power_summary_routed.pb -rpx Processor_power_routed.rpx +Command: report_power -file Processor_power_routed.rpt -pb Processor_power_summary_routed.pb -rpx Processor_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +77 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Processor_route_status.rpt -pb Processor_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Processor_timing_summary_routed.rpt -pb Processor_timing_summary_routed.pb -rpx Processor_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file Processor_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file Processor_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Processor_bus_skew_routed.rpt -pb Processor_bus_skew_routed.pb -rpx Processor_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force Processor.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./Processor.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +95 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:38 . Memory (MB): peak = 1792.078 ; gain = 406.340 +INFO: [Common 17-206] Exiting Vivado at Fri Jul 29 14:09:53 2022... diff --git a/LAB10.runs/impl_1/runme.sh b/LAB10.runs/impl_1/runme.sh new file mode 100644 index 0000000..0bd3947 --- /dev/null +++ b/LAB10.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64:C:/Xilinx1/Vivado/2018.2/bin +else + PATH=C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64:C:/Xilinx1/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log Processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Processor.tcl -notrace + + diff --git a/LAB10.runs/impl_1/usage_statistics_webtalk.html b/LAB10.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..401fc25 --- /dev/null +++ b/LAB10.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,797 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedFri Jul 29 14:09:33 2022os_platformWIN64
product_versionVivado v2018.2 (64-bit)project_idf330702f431647419194c50ab3747a93
project_iteration13random_id69c21d34-fbe6-435b-acbb-7c2162b3576f
registration_id69c21d34-fbe6-435b-acbb-7c2162b3576froute_designTRUE
target_devicexc7a35ttarget_familyartix7
target_packagecpg236target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-9750H CPU @ 2.60GHzcpu_speed2592 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram34.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
gui_handlers
abstractcombinedpanel_add_element=1abstractcombinedpanel_remove_selected_elements=5abstractsearchablepanel_show_search=4addsrcwizard_specify_hdl_netlist_block_design=7
addsrcwizard_specify_or_create_constraint_files=1addsrcwizard_specify_simulation_specific_hdl_files=13basedialog_apply=1basedialog_cancel=23
basedialog_ok=110basedialog_yes=14boardchooser_board_table=1closeplanner_yes=1
cmdmsgdialog_messages=4cmdmsgdialog_ok=25cmdmsgdialog_open_messages_view=1constraintschooserpanel_add_existing_or_create_new_constraints=1
constraintschooserpanel_add_files=1createsrcfiledialog_file_location=5createsrcfiledialog_file_name=25createsrcfiledialog_file_type=8
definemodulesdialog_define_modules_and_specify_io_ports=166expreporttreepanel_exp_report_tree_table=31expruntreepanel_exp_run_tree_table=1filesetpanel_file_set_panel_tree=2245
filesetpanel_messages=4flownavigatortreepanel_flow_navigator_tree=180gettingstartedview_create_new_project=1gettingstartedview_open_project=1
graphicalview_zoom_fit=91graphicalview_zoom_in=1hcodeeditor_blank_operations=1hcodeeditor_close=1
hcodeeditor_search_text_combo_box=26hinputhandler_replace_text=10logmonitor_monitor=2mainmenumgr_checkpoint=5
mainmenumgr_export=2mainmenumgr_file=14mainmenumgr_ip=5mainmenumgr_open_recent_project=1
mainmenumgr_project=9mainmenumgr_text_editor=3msgtreepanel_message_view_tree=33netlistschematicview_show_cells_in_this_schematic=4
netlisttreeview_floorplanning=4netlisttreeview_netlist_tree=10openfileaction_ok=4pacommandnames_add_sources=68
pacommandnames_auto_fit_selection=3pacommandnames_auto_update_hier=102pacommandnames_close_project=2pacommandnames_edit_simulation_sets=5
pacommandnames_goto_instantiation=3pacommandnames_make_active_simset=19pacommandnames_move_to_design_set=1pacommandnames_open_hardware_manager=1
pacommandnames_open_project=4pacommandnames_reports_window=3pacommandnames_run_bitgen=1pacommandnames_schematic=1
pacommandnames_select_area=6pacommandnames_set_as_top=6pacommandnames_simulation_reset=35pacommandnames_simulation_run=35
pacommandnames_simulation_run_behavioral=113pacommandnames_src_replace_file=11pacommandnames_toggle_view_nav=20pacommandnames_write_config_memory_file=2
pacommandnames_zoom_fit=6pacommandnames_zoom_in=4paviews_code=63paviews_par_report=2
planaheadtab_show_flow_navigator=20progressdialog_background=1progressdialog_cancel=2project_automatic_update_and_compile_order=1
projectnamechooser_choose_project_location=1projectnamechooser_project_name=2projecttab_close_design=1projecttab_reload=3
propertiesview_previous_object=17propertypanels_statistics_table=6rdicommands_copy=12rdicommands_delete=7
rdicommands_paste=1rdicommands_properties=3rdicommands_redo=1rdicommands_save_file=46
rdicommands_settings=3rdiviews_waveform_viewer=60rungadget_show_warning_and_error_messages_in_messages=1saveprojectutils_save=6
schematicview_previous=9schematicview_regenerate=6schematicview_remove=2schematicview_toggle_autohide_pins_for_selected_cells=2
selectareadialog_select_all=1settingsprojectgeneralpage_target_language=2simulationobjectspanel_simulation_objects_tree_table=106simulationscopespanel_simulate_scope_table=81
srcchooserpanel_add_files_below_to_this_simulation_set=17srcchooserpanel_add_hdl_and_netlist_files_to_your_project=58srcchooserpanel_add_or_create_source_file=4srcchooserpanel_create_file=24
srcchooserpanel_include_all_design_sources_for_simulation=13srcchooserpanel_make_active=8srcchoosertable_src_chooser_table=12srcconflictdialog_dont_overwrite_existing_files=6
srcconflictdialog_ok=1srcconflictdialog_view_conflicts=1srcmenu_ip_hierarchy=103srcmenu_open_selected_source_files=2
srcmenu_refresh_hierarchy=2stalemoreaction_out_of_date_details=1stalerundialog_no=1syntheticagettingstartedview_recent_projects=14
touchpointsurveydialog_no=1touchpointsurveydialog_remind_me_later=2waveformnametree_waveform_name_tree=81waveformview_find=1
waveformview_previous_transition=1
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
java_command_handlers
addsources=68closeproject=3editdelete=11editproperties=2
editsimulationsets=5editundo=2makeactivesimset=19movetodesignset=1
newproject=1openproject=5reportmethodology=1reportutilization=1
runbitgen=17runimplementation=3runschematic=3runsynthesis=4
savefileproxyhandler=1settopnode=6showsource=3showview=16
simulationclose=1simulationrun=111timingconstraintswizard=1toggleautofitselection=4
toggleselectareamode=6toggleviewnavigator=20toolssettings=3updatesourcefiles=11
viewtaskimplementation=2viewtaskrtlanalysis=2viewtasksynthesis=2waveformsaveconfiguration=3
writecfgmemfile=1zoomfit=6zoomin=4
+ + + +
other_data
guimode=34
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=130simulator_language=Mixedsrcsetcount=20synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDLtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + + +
post_unisim_transformation
bufg=1carry4=8fdre=49gnd=3
ibuf=2lut1=1lut2=13lut3=15
lut4=22lut5=11lut6=14obuf=17
vcc=3
+
+ + + + + + + + + + + + + + + +
pre_unisim_transformation
bufg=1carry4=8fdre=49gnd=3
ibuf=2lut1=1lut2=13lut3=15
lut4=22lut5=11lut6=14obuf=17
vcc=3
+

+ + + + +
report_drc
+ + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
cfgbvs-1=1
+

+ + + + +
report_methodology
+ + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-waived=default::[not_specified]
+
+ + + +
results
timing-17=16
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-l=default::[not_specified]-name=default::[not_specified]-no_propagation=default::[not_specified]
-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]-vid=default::[not_specified]
-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")clocks=0.000585confidence_level_clock_activity=Low
confidence_level_design_state=Highconfidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=Medium
confidence_level_overall=Lowcustomer=TBDcustomer_class=TBDdevstatic=0.068404
die=xc7a35tcpg236-1dsp_output_toggle=12.500000dynamic=0.001489effective_thetaja=5.0
enable_probability=0.990000family=artix7ff_toggle=12.500000flow_state=routed
heatsink=medium (Medium Profile)i/o=0.000064input_toggle=12.500000junction_temp=25.3 (C)
logic=0.000449mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=0.069893
output_enable=1.000000output_load=5.000000output_toggle=12.500000package=cpg236
pct_clock_constrained=1.000000pct_inputs_defined=50platform=nt64process=typical
ram_enable=50.000000ram_write=50.000000read_saif=Falseset/reset_probability=0.000000
signal_rate=Falsesignals=0.000390simulation_file=Nonespeedgrade=-1
static_prob=Falsetemp_grade=commercialthetajb=7.5 (C/W)thetasa=4.6 (C/W)
toggle_rate=Falseuser_board_temp=25.0 (C)user_effective_thetaja=5.0user_junc_temp=25.3 (C)
user_thetajb=7.5 (C/W)user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000
vccadc_total_current=0.020000vccadc_voltage=1.800000vccaux_dynamic_current=0.000000vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.012615
vccaux_total_current=0.012615vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000161
vccbram_total_current=0.000161vccbram_voltage=1.000000vccint_dynamic_current=0.001489vccint_static_current=0.009536
vccint_total_current=0.011025vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000
vcco12_total_current=0.000000vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000
vcco135_total_current=0.000000vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000
vcco15_total_current=0.000000vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000
vcco18_total_current=0.000000vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000
vcco25_total_current=0.000000vcco25_voltage=2.500000vcco33_dynamic_current=0.000000vcco33_static_current=0.000000
vcco33_total_current=0.000000vcco33_voltage=3.300000version=2018.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=72bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=20bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=10bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=20bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=5mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=5plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=90dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=50block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=100ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=50ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1carry4_functional_category=CarryLogiccarry4_used=8
fdre_functional_category=Flop & Latchfdre_used=50ibuf_functional_category=IOibuf_used=2
lut1_functional_category=LUTlut1_used=1lut2_functional_category=LUTlut2_used=9
lut3_functional_category=LUTlut3_used=15lut4_functional_category=LUTlut4_used=22
lut5_functional_category=LUTlut5_used=11lut6_functional_category=LUTlut6_used=10
obuf_functional_category=IOobuf_used=17
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=16300f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=8150f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=50lut_as_logic_util_percentage=0.24
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600register_as_flip_flop_fixed=0register_as_flip_flop_used=50register_as_flip_flop_util_percentage=0.12
register_as_latch_available=41600register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=20800slice_luts_fixed=0slice_luts_used=50slice_luts_util_percentage=0.24
slice_registers_available=41600slice_registers_fixed=0slice_registers_used=50slice_registers_util_percentage=0.12
fully_used_lut_ff_pairs_fixed=0.12fully_used_lut_ff_pairs_used=1lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=50lut_as_logic_util_percentage=0.24
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=5
lut_ff_pairs_with_one_unused_lut_output_fixed=5lut_ff_pairs_with_one_unused_lut_output_used=3lut_flip_flop_pairs_available=20800lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=6lut_flip_flop_pairs_util_percentage=0.03slice_available=8150slice_fixed=0
slice_used=24slice_util_percentage=0.29slicel_fixed=0slicel_used=16
slicem_fixed=0slicem_used=8unique_control_sets_used=6using_o5_and_o6_fixed=6
using_o5_and_o6_used=18using_o5_output_only_fixed=18using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=32
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=129245bogomips=0bram18=0bram36=0
bufg=0bufr=0congestion_level=0ctrls=6
dsp=0effort=2estimated_expansions=103530ff=50
global_clocks=1high_fanout_nets=0iob=19lut=67
movable_instances=152nets=185pins=775pll=0
router_runtime=0.000000router_timing_driven=1threads=2timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a35tcpg236-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=Processor-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:52shls_ip=0memory_gain=508.066MBmemory_peak=836.008MB
+

+ + + +
xsim
+ + + + +
command_line_options
-sim_mode=default::behavioral-sim_type=default::
+

+ + diff --git a/LAB10.runs/impl_1/usage_statistics_webtalk.xml b/LAB10.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..cc8a4b6 --- /dev/null +++ b/LAB10.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,726 @@ + + +
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+ diff --git a/LAB10.runs/impl_1/vivado.jou b/LAB10.runs/impl_1/vivado.jou new file mode 100644 index 0000000..5bfccf5 --- /dev/null +++ b/LAB10.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Jul 29 14:06:45 2022 +# Process ID: 19292 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1 +# Command line: vivado.exe -log Processor.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Processor.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor.vdi +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Processor.tcl -notrace diff --git a/LAB10.runs/impl_1/vivado.pb b/LAB10.runs/impl_1/vivado.pb new file mode 100644 index 0000000..340c7f6 Binary files /dev/null and b/LAB10.runs/impl_1/vivado.pb differ diff --git a/LAB10.runs/impl_1/vivado_1324.backup.jou b/LAB10.runs/impl_1/vivado_1324.backup.jou new file mode 100644 index 0000000..c14c226 --- /dev/null +++ b/LAB10.runs/impl_1/vivado_1324.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Jul 29 13:56:45 2022 +# Process ID: 1324 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1 +# Command line: vivado.exe -log Processor.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Processor.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1/Processor.vdi +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Processor.tcl -notrace diff --git a/LAB10.runs/impl_1/write_bitstream.pb b/LAB10.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..12cc6a4 Binary files /dev/null and b/LAB10.runs/impl_1/write_bitstream.pb differ diff --git a/LAB10.runs/synth_1/.Vivado_Synthesis.queue.rst b/LAB10.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/synth_1/.Xil/Processor_propImpl.xdc b/LAB10.runs/synth_1/.Xil/Processor_propImpl.xdc new file mode 100644 index 0000000..6c831b5 --- /dev/null +++ b/LAB10.runs/synth_1/.Xil/Processor_propImpl.xdc @@ -0,0 +1,39 @@ +set_property SRC_FILE_INFO {cfile:{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc} rfile:{../../../LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc} id:1} [current_design] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W5 [get_ports Clk_In] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U16 [get_ports {R7_out[0]}] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E19 [get_ports {R7_out[1]}] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U19 [get_ports {R7_out[2]}] +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V19 [get_ports {R7_out[3]}] +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P1 [get_ports {Zero}] +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN L1 [get_ports {OverFlow}] +set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W7 [get_ports {S_7Seg_out[0]}] +set_property src_info {type:XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W6 [get_ports {S_7Seg_out[1]}] +set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U8 [get_ports {S_7Seg_out[2]}] +set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V8 [get_ports {S_7Seg_out[3]}] +set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U5 [get_ports {S_7Seg_out[4]}] +set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V5 [get_ports {S_7Seg_out[5]}] +set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U7 [get_ports {S_7Seg_out[6]}] +set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U2 [get_ports {anode_out[0]}] +set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U4 [get_ports {anode_out[1]}] +set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V4 [get_ports {anode_out[2]}] +set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W4 [get_ports {anode_out[3]}] +set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U18 [get_ports Reset] diff --git a/LAB10.runs/synth_1/.vivado.begin.rst b/LAB10.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..30513f8 --- /dev/null +++ b/LAB10.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB10.runs/synth_1/.vivado.end.rst b/LAB10.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/synth_1/ISEWrap.js b/LAB10.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/LAB10.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/LAB10.runs/synth_1/ISEWrap.sh b/LAB10.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/LAB10.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/LAB10.runs/synth_1/Processor.dcp b/LAB10.runs/synth_1/Processor.dcp new file mode 100644 index 0000000..57257a9 Binary files /dev/null and b/LAB10.runs/synth_1/Processor.dcp differ diff --git a/LAB10.runs/synth_1/Processor.tcl b/LAB10.runs/synth_1/Processor.tcl new file mode 100644 index 0000000..ed1bc83 --- /dev/null +++ b/LAB10.runs/synth_1/Processor.tcl @@ -0,0 +1,76 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_msg_config -id {HDL 9-1061} -limit 100000 +set_msg_config -id {HDL 9-1654} -limit 100000 +create_project -in_memory -part xc7a35tcpg236-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.cache/wt} [current_project] +set_property parent.project_path {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.xpr} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language VHDL [current_project] +set_property ip_output_repo {c:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.cache/ip} [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_vhdl -library xil_defaultlib { + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd} + {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd} +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc}} +set_property used_in_implementation false [get_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc}}] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top Processor -part xc7a35tcpg236-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef Processor.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file Processor_utilization_synth.rpt -pb Processor_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/LAB10.runs/synth_1/Processor.vds b/LAB10.runs/synth_1/Processor.vds new file mode 100644 index 0000000..3591e0e --- /dev/null +++ b/LAB10.runs/synth_1/Processor.vds @@ -0,0 +1,452 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Jul 29 14:05:12 2022 +# Process ID: 26256 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1 +# Command line: vivado.exe -log Processor.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Processor.tcl +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1/Processor.vds +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source Processor.tcl -notrace +create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 326.727 ; gain = 97.309 +Command: synth_design -top Processor -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 25220 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 434.832 ; gain = 95.383 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'Processor' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:45] +INFO: [Synth 8-3491] module 'Slow_Clk' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd:34' bound to instance 'Slow_Clk0' of component 'Slow_Clk' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:244] +INFO: [Synth 8-638] synthesizing module 'Slow_Clk' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd:39] +INFO: [Synth 8-256] done synthesizing module 'Slow_Clk' (1#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd:39] +INFO: [Synth 8-3491] module 'Register_bank' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:34' bound to instance 'Register_bank0' of component 'Register_bank' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:249] +INFO: [Synth 8-638] synthesizing module 'Register_bank' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:52] +INFO: [Synth 8-3491] module 'Decoder_3_to_8' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:34' bound to instance 'Decoder_3_to_8_0' of component 'Decoder_3_to_8' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:70] +INFO: [Synth 8-638] synthesizing module 'Decoder_3_to_8' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:40] +INFO: [Synth 8-3491] module 'Decoder_2_to_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:34' bound to instance 'Decoder_2_to_4_0' of component 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:52] +INFO: [Synth 8-638] synthesizing module 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'Decoder_2_to_4' (2#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:40] +INFO: [Synth 8-3491] module 'Decoder_2_to_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:34' bound to instance 'Decoder_2_to_4_1' of component 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:58] +INFO: [Synth 8-256] done synthesizing module 'Decoder_3_to_8' (3#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:40] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R01' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:76] +INFO: [Synth 8-638] synthesizing module 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Reg' (4#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:42] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R11' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:84] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R21' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:92] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R31' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:100] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R41' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:108] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R51' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:116] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R61' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:124] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R71' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:132] +INFO: [Synth 8-256] done synthesizing module 'Register_bank' (5#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:52] +INFO: [Synth 8-3491] module 'Mux_2way_3bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd:34' bound to instance 'Mux_2way_3bit0' of component 'Mux_2way_3bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:267] +INFO: [Synth 8-638] synthesizing module 'Mux_2way_3bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Mux_2way_3bit' (6#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd:42] +INFO: [Synth 8-3491] module 'Mux_2way_4bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd:34' bound to instance 'Mux_2way_4bit0' of component 'Mux_2way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:277] +INFO: [Synth 8-638] synthesizing module 'Mux_2way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'Mux_2way_4bit' (7#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd:44] +INFO: [Synth 8-3491] module 'Mux_8way_4bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:34' bound to instance 'Mux_8way_4bit1' of component 'Mux_8way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:286] +INFO: [Synth 8-638] synthesizing module 'Mux_8way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:56] +INFO: [Synth 8-3491] module 'Decoder_3_to_8' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:34' bound to instance 'Decoder_3_to_8_0' of component 'Decoder_3_to_8' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:79] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_0' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:85] +INFO: [Synth 8-638] synthesizing module 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'quad_tri_state_buffer' (8#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:40] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_1' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:91] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_2' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:97] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_3' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:103] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_4' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:109] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_5' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:115] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_6' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:121] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_7' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:127] +INFO: [Synth 8-256] done synthesizing module 'Mux_8way_4bit' (9#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:56] +INFO: [Synth 8-3491] module 'Mux_8way_4bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:34' bound to instance 'Mux_8way_4bit2' of component 'Mux_8way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:307] +INFO: [Synth 8-3491] module 'AddSubUnitBit_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:34' bound to instance 'AddSubUnitBit_40' of component 'AddSubUnitBit_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:329] +INFO: [Synth 8-638] synthesizing module 'AddSubUnitBit_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:43] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_0' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:63] +INFO: [Synth 8-638] synthesizing module 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:42] +INFO: [Synth 8-3491] module 'HA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:34' bound to instance 'HA_0' of component 'HA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:55] +INFO: [Synth 8-638] synthesizing module 'HA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:41] +INFO: [Synth 8-256] done synthesizing module 'HA' (10#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:41] +INFO: [Synth 8-3491] module 'HA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:34' bound to instance 'HA_1' of component 'HA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:63] +INFO: [Synth 8-256] done synthesizing module 'FA' (11#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:42] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_1' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:72] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_2' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:81] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_3' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:90] +INFO: [Synth 8-256] done synthesizing module 'AddSubUnitBit_4' (12#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:43] +INFO: [Synth 8-3491] module 'Instruction_Decoder' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:34' bound to instance 'Instruction_Decoder0' of component 'Instruction_Decoder' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:341] +INFO: [Synth 8-638] synthesizing module 'Instruction_Decoder' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:47] +INFO: [Synth 8-3491] module 'Decoder_2_to_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:34' bound to instance 'Decoder_2_to_4_0' of component 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:60] +INFO: [Synth 8-256] done synthesizing module 'Instruction_Decoder' (13#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:47] +INFO: [Synth 8-3491] module 'Program_ROM' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd:34' bound to instance 'Program_ROM0' of component 'Program_ROM' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:354] +INFO: [Synth 8-638] synthesizing module 'Program_ROM' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd:39] +INFO: [Synth 8-256] done synthesizing module 'Program_ROM' (14#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd:39] +INFO: [Synth 8-3491] module 'AdderBit_3' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:37' bound to instance 'AdderBit_30' of component 'AdderBit_3' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:359] +INFO: [Synth 8-638] synthesizing module 'AdderBit_3' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:43] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_0' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:59] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_1' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:67] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_2' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:75] +WARNING: [Synth 8-3848] Net C_OUT in module/entity AdderBit_3 does not have driver. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'AdderBit_3' (15#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:43] +INFO: [Synth 8-3491] module 'Program_counter' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd:34' bound to instance 'Program_counter0' of component 'Program_counter' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:366] +INFO: [Synth 8-638] synthesizing module 'Program_counter' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Program_counter' (16#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd:42] +INFO: [Synth 8-3491] module 'R7_7_seg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:34' bound to instance 'R7_7_seg_0' of component 'R7_7_seg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:373] +INFO: [Synth 8-638] synthesizing module 'R7_7_seg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:42] +INFO: [Synth 8-3491] module 'LUT_16_7' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd:35' bound to instance 'LUT_16_7_0' of component 'LUT_16_7' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:52] +INFO: [Synth 8-638] synthesizing module 'LUT_16_7' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'LUT_16_7' (17#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'R7_7_seg' (18#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Processor' (19#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:45] +WARNING: [Synth 8-3331] design AdderBit_3 has unconnected port C_OUT +WARNING: [Synth 8-3331] design Mux_8way_4bit has unconnected port EN +WARNING: [Synth 8-3331] design Mux_2way_4bit has unconnected port EN +WARNING: [Synth 8-3331] design Mux_2way_3bit has unconnected port EN +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 490.234 ; gain = 150.785 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 490.234 ; gain = 150.785 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 490.234 ; gain = 150.785 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +Finished Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Processor_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/Processor_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 815.527 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5545] ROM "count" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "Clk_status" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5544] ROM "sevenSegment_ROM" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sevenSegment_ROM" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 18 ++---Registers : + 32 Bit Registers := 1 + 4 Bit Registers := 8 + 3 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 9 Input 12 Bit Muxes := 1 + 17 Input 7 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module Slow_Clk +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module Reg +Detailed RTL Component Info : ++---Registers : + 4 Bit Registers := 1 +Module Mux_2way_3bit +Detailed RTL Component Info : ++---Muxes : + 2 Input 3 Bit Muxes := 1 +Module Mux_2way_4bit +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 1 +Module HA +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 +Module AddSubUnitBit_4 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 4 +Module Program_ROM +Detailed RTL Component Info : ++---Muxes : + 9 Input 12 Bit Muxes := 1 +Module Program_counter +Detailed RTL Component Info : ++---Registers : + 3 Bit Registers := 1 +Module LUT_16_7 +Detailed RTL Component Info : ++---Muxes : + 17 Input 7 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5545] ROM "Slow_Clk0/count" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "Slow_Clk0/Clk_status" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +WARNING: [Synth 8-3917] design Processor has port anode_out[3] driven by constant 1 +WARNING: [Synth 8-3917] design Processor has port anode_out[2] driven by constant 1 +WARNING: [Synth 8-3917] design Processor has port anode_out[1] driven by constant 1 +WARNING: [Synth 8-3917] design Processor has port anode_out[0] driven by constant 0 +INFO: [Synth 8-3886] merging instance 'Register_bank0/R01/Q_reg[3]' (FDRE) to 'Register_bank0/R01/Q_reg[2]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R01/Q_reg[2]' (FDRE) to 'Register_bank0/R01/Q_reg[1]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R01/Q_reg[1]' (FDRE) to 'Register_bank0/R01/Q_reg[0]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R01/Q_reg[0] ) +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R01/Q_reg[0]) is unused and will be removed from module Processor. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 835.219 ; gain = 495.770 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[1]' (FDRE) to 'Register_bank0/R51/Q_reg[1]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[1]' (FDRE) to 'Register_bank0/R51/Q_reg[1]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[1]' (FDRE) to 'Register_bank0/R61/Q_reg[1]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[1] ) +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[0]' (FDRE) to 'Register_bank0/R51/Q_reg[0]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[0]' (FDRE) to 'Register_bank0/R51/Q_reg[0]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[0]' (FDRE) to 'Register_bank0/R61/Q_reg[0]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[0] ) +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[3]' (FDRE) to 'Register_bank0/R51/Q_reg[3]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[3]' (FDRE) to 'Register_bank0/R51/Q_reg[3]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[3]' (FDRE) to 'Register_bank0/R61/Q_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[3] ) +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[2]' (FDRE) to 'Register_bank0/R51/Q_reg[2]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[2]' (FDRE) to 'Register_bank0/R51/Q_reg[2]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[2]' (FDRE) to 'Register_bank0/R61/Q_reg[2]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[2] ) +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[1]) is unused and will be removed from module Processor. +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[0]) is unused and will be removed from module Processor. +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[3]) is unused and will be removed from module Processor. +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[2]) is unused and will be removed from module Processor. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 8| +|3 |LUT1 | 1| +|4 |LUT2 | 13| +|5 |LUT3 | 15| +|6 |LUT4 | 22| +|7 |LUT5 | 11| +|8 |LUT6 | 14| +|9 |FDRE | 49| +|10 |IBUF | 2| +|11 |OBUF | 17| ++------+-------+------+ + +Report Instance Areas: ++------+-----------------------+----------------+------+ +| |Instance |Module |Cells | ++------+-----------------------+----------------+------+ +|1 |top | | 153| +|2 | Mux_8way_4bit1 |Mux_8way_4bit | 1| +|3 | Decoder_3_to_8_0 |Decoder_3_to_8 | 1| +|4 | Decoder_2_to_4_0 |Decoder_2_to_4 | 1| +|5 | Program_counter0 |Program_counter | 30| +|6 | Register_bank0 |Register_bank | 48| +|7 | R21 |Reg | 4| +|8 | R31 |Reg_0 | 12| +|9 | R71 |Reg_1 | 32| +|10 | Slow_Clk0 |Slow_Clk | 54| ++------+-----------------------+----------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 9 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:39 . Memory (MB): peak = 836.008 ; gain = 171.266 +Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +119 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 836.008 ; gain = 509.281 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1/Processor.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file Processor_utilization_synth.rpt -pb Processor_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 836.008 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Fri Jul 29 14:06:37 2022... diff --git a/LAB10.runs/synth_1/Processor_utilization_synth.pb b/LAB10.runs/synth_1/Processor_utilization_synth.pb new file mode 100644 index 0000000..f57d38a Binary files /dev/null and b/LAB10.runs/synth_1/Processor_utilization_synth.pb differ diff --git a/LAB10.runs/synth_1/Processor_utilization_synth.rpt b/LAB10.runs/synth_1/Processor_utilization_synth.rpt new file mode 100644 index 0000000..b8d170f --- /dev/null +++ b/LAB10.runs/synth_1/Processor_utilization_synth.rpt @@ -0,0 +1,181 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Jul 29 14:06:37 2022 +| Host : Chamaru-XPS running 64-bit major release (build 9200) +| Command : report_utilization -file Processor_utilization_synth.rpt -pb Processor_utilization_synth.pb +| Design : Processor +| Device : 7a35tcpg236-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 60 | 0 | 20800 | 0.29 | +| LUT as Logic | 60 | 0 | 20800 | 0.29 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 49 | 0 | 41600 | 0.12 | +| Register as Flip Flop | 49 | 0 | 41600 | 0.12 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 49 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 19 | 0 | 106 | 17.92 | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 49 | Flop & Latch | +| LUT4 | 22 | LUT | +| OBUF | 17 | IO | +| LUT3 | 15 | LUT | +| LUT6 | 14 | LUT | +| LUT2 | 13 | LUT | +| LUT5 | 11 | LUT | +| CARRY4 | 8 | CarryLogic | +| IBUF | 2 | IO | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/LAB10.runs/synth_1/__synthesis_is_complete__ b/LAB10.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.runs/synth_1/gen_run.xml b/LAB10.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..e69a28c --- /dev/null +++ b/LAB10.runs/synth_1/gen_run.xml @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LAB10.runs/synth_1/htr.txt b/LAB10.runs/synth_1/htr.txt new file mode 100644 index 0000000..8553206 --- /dev/null +++ b/LAB10.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log Processor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Processor.tcl diff --git a/LAB10.runs/synth_1/rundef.js b/LAB10.runs/synth_1/rundef.js new file mode 100644 index 0000000..d9abc6a --- /dev/null +++ b/LAB10.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64;C:/Xilinx1/Vivado/2018.2/bin;"; +} else { + PathVal = "C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64;C:/Xilinx1/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log Processor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Processor.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/LAB10.runs/synth_1/runme.bat b/LAB10.runs/synth_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/LAB10.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LAB10.runs/synth_1/runme.log b/LAB10.runs/synth_1/runme.log new file mode 100644 index 0000000..5cdccee --- /dev/null +++ b/LAB10.runs/synth_1/runme.log @@ -0,0 +1,451 @@ + +*** Running vivado + with args -log Processor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Processor.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source Processor.tcl -notrace +create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 326.727 ; gain = 97.309 +Command: synth_design -top Processor -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 25220 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 434.832 ; gain = 95.383 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'Processor' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:45] +INFO: [Synth 8-3491] module 'Slow_Clk' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd:34' bound to instance 'Slow_Clk0' of component 'Slow_Clk' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:244] +INFO: [Synth 8-638] synthesizing module 'Slow_Clk' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd:39] +INFO: [Synth 8-256] done synthesizing module 'Slow_Clk' (1#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd:39] +INFO: [Synth 8-3491] module 'Register_bank' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:34' bound to instance 'Register_bank0' of component 'Register_bank' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:249] +INFO: [Synth 8-638] synthesizing module 'Register_bank' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:52] +INFO: [Synth 8-3491] module 'Decoder_3_to_8' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:34' bound to instance 'Decoder_3_to_8_0' of component 'Decoder_3_to_8' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:70] +INFO: [Synth 8-638] synthesizing module 'Decoder_3_to_8' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:40] +INFO: [Synth 8-3491] module 'Decoder_2_to_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:34' bound to instance 'Decoder_2_to_4_0' of component 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:52] +INFO: [Synth 8-638] synthesizing module 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'Decoder_2_to_4' (2#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:40] +INFO: [Synth 8-3491] module 'Decoder_2_to_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:34' bound to instance 'Decoder_2_to_4_1' of component 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:58] +INFO: [Synth 8-256] done synthesizing module 'Decoder_3_to_8' (3#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:40] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R01' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:76] +INFO: [Synth 8-638] synthesizing module 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Reg' (4#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:42] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R11' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:84] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R21' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:92] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R31' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:100] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R41' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:108] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R51' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:116] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R61' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:124] +INFO: [Synth 8-3491] module 'Reg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd:34' bound to instance 'R71' of component 'Reg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:132] +INFO: [Synth 8-256] done synthesizing module 'Register_bank' (5#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd:52] +INFO: [Synth 8-3491] module 'Mux_2way_3bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd:34' bound to instance 'Mux_2way_3bit0' of component 'Mux_2way_3bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:267] +INFO: [Synth 8-638] synthesizing module 'Mux_2way_3bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Mux_2way_3bit' (6#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd:42] +INFO: [Synth 8-3491] module 'Mux_2way_4bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd:34' bound to instance 'Mux_2way_4bit0' of component 'Mux_2way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:277] +INFO: [Synth 8-638] synthesizing module 'Mux_2way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd:44] +INFO: [Synth 8-256] done synthesizing module 'Mux_2way_4bit' (7#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd:44] +INFO: [Synth 8-3491] module 'Mux_8way_4bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:34' bound to instance 'Mux_8way_4bit1' of component 'Mux_8way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:286] +INFO: [Synth 8-638] synthesizing module 'Mux_8way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:56] +INFO: [Synth 8-3491] module 'Decoder_3_to_8' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd:34' bound to instance 'Decoder_3_to_8_0' of component 'Decoder_3_to_8' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:79] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_0' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:85] +INFO: [Synth 8-638] synthesizing module 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'quad_tri_state_buffer' (8#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:40] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_1' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:91] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_2' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:97] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_3' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:103] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_4' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:109] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_5' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:115] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_6' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:121] +INFO: [Synth 8-3491] module 'quad_tri_state_buffer' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd:34' bound to instance 'quad_tri_state_buffer_7' of component 'quad_tri_state_buffer' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:127] +INFO: [Synth 8-256] done synthesizing module 'Mux_8way_4bit' (9#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:56] +INFO: [Synth 8-3491] module 'Mux_8way_4bit' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd:34' bound to instance 'Mux_8way_4bit2' of component 'Mux_8way_4bit' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:307] +INFO: [Synth 8-3491] module 'AddSubUnitBit_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:34' bound to instance 'AddSubUnitBit_40' of component 'AddSubUnitBit_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:329] +INFO: [Synth 8-638] synthesizing module 'AddSubUnitBit_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:43] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_0' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:63] +INFO: [Synth 8-638] synthesizing module 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:42] +INFO: [Synth 8-3491] module 'HA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:34' bound to instance 'HA_0' of component 'HA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:55] +INFO: [Synth 8-638] synthesizing module 'HA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:41] +INFO: [Synth 8-256] done synthesizing module 'HA' (10#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:41] +INFO: [Synth 8-3491] module 'HA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd:34' bound to instance 'HA_1' of component 'HA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:63] +INFO: [Synth 8-256] done synthesizing module 'FA' (11#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:42] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_1' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:72] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_2' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:81] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_3' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:90] +INFO: [Synth 8-256] done synthesizing module 'AddSubUnitBit_4' (12#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd:43] +INFO: [Synth 8-3491] module 'Instruction_Decoder' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:34' bound to instance 'Instruction_Decoder0' of component 'Instruction_Decoder' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:341] +INFO: [Synth 8-638] synthesizing module 'Instruction_Decoder' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:47] +INFO: [Synth 8-3491] module 'Decoder_2_to_4' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd:34' bound to instance 'Decoder_2_to_4_0' of component 'Decoder_2_to_4' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:60] +INFO: [Synth 8-256] done synthesizing module 'Instruction_Decoder' (13#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd:47] +INFO: [Synth 8-3491] module 'Program_ROM' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd:34' bound to instance 'Program_ROM0' of component 'Program_ROM' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:354] +INFO: [Synth 8-638] synthesizing module 'Program_ROM' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd:39] +INFO: [Synth 8-256] done synthesizing module 'Program_ROM' (14#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd:39] +INFO: [Synth 8-3491] module 'AdderBit_3' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:37' bound to instance 'AdderBit_30' of component 'AdderBit_3' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:359] +INFO: [Synth 8-638] synthesizing module 'AdderBit_3' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:43] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_0' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:59] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_1' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:67] +INFO: [Synth 8-3491] module 'FA' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd:34' bound to instance 'FA_2' of component 'FA' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:75] +WARNING: [Synth 8-3848] Net C_OUT in module/entity AdderBit_3 does not have driver. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'AdderBit_3' (15#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd:43] +INFO: [Synth 8-3491] module 'Program_counter' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd:34' bound to instance 'Program_counter0' of component 'Program_counter' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:366] +INFO: [Synth 8-638] synthesizing module 'Program_counter' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Program_counter' (16#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd:42] +INFO: [Synth 8-3491] module 'R7_7_seg' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:34' bound to instance 'R7_7_seg_0' of component 'R7_7_seg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:373] +INFO: [Synth 8-638] synthesizing module 'R7_7_seg' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:42] +INFO: [Synth 8-3491] module 'LUT_16_7' declared at 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd:35' bound to instance 'LUT_16_7_0' of component 'LUT_16_7' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:52] +INFO: [Synth 8-638] synthesizing module 'LUT_16_7' [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'LUT_16_7' (17#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd:40] +INFO: [Synth 8-256] done synthesizing module 'R7_7_seg' (18#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd:42] +INFO: [Synth 8-256] done synthesizing module 'Processor' (19#1) [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:45] +WARNING: [Synth 8-3331] design AdderBit_3 has unconnected port C_OUT +WARNING: [Synth 8-3331] design Mux_8way_4bit has unconnected port EN +WARNING: [Synth 8-3331] design Mux_2way_4bit has unconnected port EN +WARNING: [Synth 8-3331] design Mux_2way_3bit has unconnected port EN +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 490.234 ; gain = 150.785 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 490.234 ; gain = 150.785 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 490.234 ; gain = 150.785 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +Finished Parsing XDC File [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Processor_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/Processor_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 815.527 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5545] ROM "count" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "Clk_status" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5544] ROM "sevenSegment_ROM" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sevenSegment_ROM" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 18 ++---Registers : + 32 Bit Registers := 1 + 4 Bit Registers := 8 + 3 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 9 Input 12 Bit Muxes := 1 + 17 Input 7 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module Slow_Clk +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module Reg +Detailed RTL Component Info : ++---Registers : + 4 Bit Registers := 1 +Module Mux_2way_3bit +Detailed RTL Component Info : ++---Muxes : + 2 Input 3 Bit Muxes := 1 +Module Mux_2way_4bit +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 1 +Module HA +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 +Module AddSubUnitBit_4 +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 4 +Module Program_ROM +Detailed RTL Component Info : ++---Muxes : + 9 Input 12 Bit Muxes := 1 +Module Program_counter +Detailed RTL Component Info : ++---Registers : + 3 Bit Registers := 1 +Module LUT_16_7 +Detailed RTL Component Info : ++---Muxes : + 17 Input 7 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5545] ROM "Slow_Clk0/count" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "Slow_Clk0/Clk_status" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +WARNING: [Synth 8-3917] design Processor has port anode_out[3] driven by constant 1 +WARNING: [Synth 8-3917] design Processor has port anode_out[2] driven by constant 1 +WARNING: [Synth 8-3917] design Processor has port anode_out[1] driven by constant 1 +WARNING: [Synth 8-3917] design Processor has port anode_out[0] driven by constant 0 +INFO: [Synth 8-3886] merging instance 'Register_bank0/R01/Q_reg[3]' (FDRE) to 'Register_bank0/R01/Q_reg[2]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R01/Q_reg[2]' (FDRE) to 'Register_bank0/R01/Q_reg[1]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R01/Q_reg[1]' (FDRE) to 'Register_bank0/R01/Q_reg[0]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R01/Q_reg[0] ) +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R01/Q_reg[0]) is unused and will be removed from module Processor. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 815.527 ; gain = 476.078 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 835.219 ; gain = 495.770 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[1]' (FDRE) to 'Register_bank0/R51/Q_reg[1]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[1]' (FDRE) to 'Register_bank0/R51/Q_reg[1]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[1]' (FDRE) to 'Register_bank0/R61/Q_reg[1]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[1] ) +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[0]' (FDRE) to 'Register_bank0/R51/Q_reg[0]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[0]' (FDRE) to 'Register_bank0/R51/Q_reg[0]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[0]' (FDRE) to 'Register_bank0/R61/Q_reg[0]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[0] ) +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[3]' (FDRE) to 'Register_bank0/R51/Q_reg[3]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[3]' (FDRE) to 'Register_bank0/R51/Q_reg[3]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[3]' (FDRE) to 'Register_bank0/R61/Q_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[3] ) +INFO: [Synth 8-3886] merging instance 'Register_bank0/R11/Q_reg[2]' (FDRE) to 'Register_bank0/R51/Q_reg[2]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R41/Q_reg[2]' (FDRE) to 'Register_bank0/R51/Q_reg[2]' +INFO: [Synth 8-3886] merging instance 'Register_bank0/R51/Q_reg[2]' (FDRE) to 'Register_bank0/R61/Q_reg[2]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Register_bank0/R61/Q_reg[2] ) +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[1]) is unused and will be removed from module Processor. +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[0]) is unused and will be removed from module Processor. +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[3]) is unused and will be removed from module Processor. +WARNING: [Synth 8-3332] Sequential element (Register_bank0/R61/Q_reg[2]) is unused and will be removed from module Processor. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 8| +|3 |LUT1 | 1| +|4 |LUT2 | 13| +|5 |LUT3 | 15| +|6 |LUT4 | 22| +|7 |LUT5 | 11| +|8 |LUT6 | 14| +|9 |FDRE | 49| +|10 |IBUF | 2| +|11 |OBUF | 17| ++------+-------+------+ + +Report Instance Areas: ++------+-----------------------+----------------+------+ +| |Instance |Module |Cells | ++------+-----------------------+----------------+------+ +|1 |top | | 153| +|2 | Mux_8way_4bit1 |Mux_8way_4bit | 1| +|3 | Decoder_3_to_8_0 |Decoder_3_to_8 | 1| +|4 | Decoder_2_to_4_0 |Decoder_2_to_4 | 1| +|5 | Program_counter0 |Program_counter | 30| +|6 | Register_bank0 |Register_bank | 48| +|7 | R21 |Reg | 4| +|8 | R31 |Reg_0 | 12| +|9 | R71 |Reg_1 | 32| +|10 | Slow_Clk0 |Slow_Clk | 54| ++------+-----------------------+----------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 9 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:39 . Memory (MB): peak = 836.008 ; gain = 171.266 +Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:51 . Memory (MB): peak = 836.008 ; gain = 496.559 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +119 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 836.008 ; gain = 509.281 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1/Processor.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file Processor_utilization_synth.rpt -pb Processor_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 836.008 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Fri Jul 29 14:06:37 2022... diff --git a/LAB10.runs/synth_1/runme.sh b/LAB10.runs/synth_1/runme.sh new file mode 100644 index 0000000..d411538 --- /dev/null +++ b/LAB10.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64:C:/Xilinx1/Vivado/2018.2/bin +else + PATH=C:/Xilinx1/SDK/2018.2/bin;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/bin/nt64;C:/Xilinx1/Vivado/2018.2/ids_lite/ISE/lib/nt64:C:/Xilinx1/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log Processor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Processor.tcl diff --git a/LAB10.runs/synth_1/vivado.jou b/LAB10.runs/synth_1/vivado.jou new file mode 100644 index 0000000..39a686f --- /dev/null +++ b/LAB10.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Jul 29 14:05:12 2022 +# Process ID: 26256 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1 +# Command line: vivado.exe -log Processor.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Processor.tcl +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1/Processor.vds +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source Processor.tcl -notrace diff --git a/LAB10.runs/synth_1/vivado.pb b/LAB10.runs/synth_1/vivado.pb new file mode 100644 index 0000000..9d04681 Binary files /dev/null and b/LAB10.runs/synth_1/vivado.pb differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4.vhd b/LAB10.sim/TB_AddSubUnitBit_4.vhd new file mode 100644 index 0000000..708ffb3 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4.vhd @@ -0,0 +1,82 @@ +---------------------------------------------------------------------------------- +-- Company: University of Moratuwa +-- Engineer: Ginushmal Vikumkith - 200734G +-- +-- Create Date: 07/07/2022 07:13:45 PM +-- Design Name: +-- Module Name: TB_AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_AddSubUnitBit_4 is +-- Port ( ); +end TB_AddSubUnitBit_4; + +architecture Behavioral of TB_AddSubUnitBit_4 is +component AddSubUnitBit_4 + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; +-- If substraction, 1 +-- If addition 0 + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end component; + signal A,B,S : STD_LOGIC_VECTOR (3 downto 0); + signal Overflow,Zero,AddSub_Select : STD_LOGIC:='0'; +begin +UUT: AddSubUnitBit_4 + PORT MAP( + A=>A, + B=>B, + S=>S, + Overflow=>Overflow, + Zero=>Zero, + AddSub_Select=>AddSub_Select + ); +process begin +-- This program was developed by Ginushmal Vikumjith - 200734G - +-- My Index number in binary is 11 0001 0000 0001 1110 +-- Let's test 0011 - 0001= 0010 +-- 0001 + 1110 = 1111 + +--Testing 0011 - 0001= 0010 + A<="0011"; + B<="0001"; + -- because we have to subtract AddSub_Select=1 + AddSub_Select<='1'; + WAIT FOR 100ns; + +-- Testing 0001 + 1110 = 1111 + A<="0110"; + B<="1001"; + -- because we have to add AddSub_Select=0 + AddSub_Select<='0'; + WAIT; + +end process; +end Behavioral; \ No newline at end of file diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4.tcl b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4_behav.wdb b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4_behav.wdb new file mode 100644 index 0000000..8c2f08f Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4_behav.wdb differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj new file mode 100644 index 0000000..8e0012a --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/TB_AddSubUnitBit_4/imports/sim_1/AddSubUnitBit_4.vhd" \ +"../../../../LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd" \ +"../../../../LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd" \ +"../../../../LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.sim/TB_AddSubUnitBit_4.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/compile.bat b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/compile.bat new file mode 100644 index 0000000..5f158f9 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 28 03:59:17 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj" +call xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/compile.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/compile.log new file mode 100644 index 0000000..26d1aba --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/compile.log @@ -0,0 +1,8 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/sim_1/AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AddSubUnitBit_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity FA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity HA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.sim/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/elaborate.bat b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/elaborate.bat new file mode 100644 index 0000000..2577b35 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 28 03:59:20 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/elaborate.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/elaborate.log new file mode 100644 index 0000000..1d4f782 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/elaborate.log @@ -0,0 +1,17 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_addsubunitbit_4 +Built simulation snapshot TB_AddSubUnitBit_4_behav diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/simulate.bat b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/simulate.bat new file mode 100644 index 0000000..ddbdb25 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 28 03:59:27 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_AddSubUnitBit_4_behav -key {Behavioral:TB_AddSubUnitBit_4:Functional:TB_AddSubUnitBit_4} -tclbatch TB_AddSubUnitBit_4.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/simulate.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.jou b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.jou new file mode 100644 index 0000000..ca168c0 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:45 2022 +# Process ID: 22240 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log new file mode 100644 index 0000000..b295152 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:45 2022 +# Process ID: 22240 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 11:59:45 2022... diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_21372.backup.jou b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_21372.backup.jou new file mode 100644 index 0000000..3a78df4 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_21372.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 16:19:39 2022 +# Process ID: 21372 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_21372.backup.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_21372.backup.log new file mode 100644 index 0000000..d2ff349 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_21372.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 16:19:39 2022 +# Process ID: 21372 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 16:19:40 2022... diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_24844.backup.jou b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_24844.backup.jou new file mode 100644 index 0000000..3f4c5ff --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_24844.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:59:27 2022 +# Process ID: 24844 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_24844.backup.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_24844.backup.log new file mode 100644 index 0000000..e261e6c --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_24844.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:59:27 2022 +# Process ID: 24844 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 03:59:27 2022... diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_33524.backup.jou b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_33524.backup.jou new file mode 100644 index 0000000..cf3e537 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_33524.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sat Jul 23 22:43:41 2022 +# Process ID: 33524 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_33524.backup.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_33524.backup.log new file mode 100644 index 0000000..e7793e7 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_33524.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sat Jul 23 22:43:41 2022 +# Process ID: 33524 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Sat Jul 23 22:43:42 2022... diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_52008.backup.jou b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_52008.backup.jou new file mode 100644 index 0000000..a0b005a --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_52008.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 16:19:00 2022 +# Process ID: 52008 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_52008.backup.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_52008.backup.log new file mode 100644 index 0000000..ed99a72 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_52008.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 16:19:00 2022 +# Process ID: 52008 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 16:19:01 2022... diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_9252.backup.jou b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_9252.backup.jou new file mode 100644 index 0000000..3e2ff6c --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_9252.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sat Jul 23 22:48:33 2022 +# Process ID: 9252 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_9252.backup.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_9252.backup.log new file mode 100644 index 0000000..ceba725 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk_9252.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sat Jul 23 22:48:33 2022 +# Process ID: 9252 +# Current directory: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Sat Jul 23 22:48:34 2022... diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xelab.pb b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xelab.pb new file mode 100644 index 0000000..9c49bbe Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt new file mode 100644 index 0000000..44528b9 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_AddSubUnitBit_4_behav" "xil_defaultlib.TB_AddSubUnitBit_4" -log "elaborate.log" diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..26caa5d Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c new file mode 100644 index 0000000..39b938a --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_53(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_51(char*, char *); +extern void execute_52(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_53, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_51, (funcp)execute_52, (funcp)execute_22, (funcp)execute_23, (funcp)execute_17, (funcp)execute_18, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc", (void **)funcTab, 12); + iki_vhdl_file_variable_register(dp + 8152); + iki_vhdl_file_variable_register(dp + 8208); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..819ad10 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..c5a8b0c --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658960964 +1658989784 +21 +0 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.html b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..b344a96 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,52 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedMon Jul 25 16:19:38 2022os_platformWIN64
product_versionXSIM v2018.2 (64-bit)project_idf330702f431647419194c50ab3747a93
project_iteration5random_id42d18b2525b056b7b3ef00b7402b363d
registration_id42d18b2525b056b7b3ef00b7402b363droute_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-10210U CPU @ 1.60GHzcpu_speed2112 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + +
usage
iteration=0runtime=1 ussimulation_memory=6432_KBsimulation_time=0.01_sec
+

+ + diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.xml b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..e24c3d8 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,43 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
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+
+
+ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg new file mode 100644 index 0000000..da87928 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem new file mode 100644 index 0000000..53693b7 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc new file mode 100644 index 0000000..7e35504 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx new file mode 100644 index 0000000..f987eff --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 7043693660055732396 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe\" \"xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti new file mode 100644 index 0000000..fe5aa4b Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type new file mode 100644 index 0000000..7f47fdf Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg new file mode 100644 index 0000000..22ec848 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimcrash.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe new file mode 100644 index 0000000..7518a68 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log new file mode 100644 index 0000000..d78c777 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe -simmode gui -wdb TB_AddSubUnitBit_4_behav.wdb -simrunnum 0 -socket 62965 +Design successfully loaded +Design Loading Memory Usage: 6472 KB (Peak: 6472 KB) +Design Loading CPU Usage: 77 ms +Simulation completed +Simulation Memory Usage: 7076 KB (Peak: 7076 KB) +Simulation CPU Usage: 77 ms diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb new file mode 100644 index 0000000..9206a12 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb new file mode 100644 index 0000000..1aea049 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb new file mode 100644 index 0000000..2ab02f8 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb new file mode 100644 index 0000000..c2d89bc Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb differ diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..a6bfde2 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,8 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.sim/TB_AddSubUnitBit_4.vhd,1658769784,vhdl,,,,tb_addsubunitbit_4,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd,1658769784,vhdl,,,,fa,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd,1658769784,vhdl,,,,ha,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/sim_1/AddSubUnitBit_4.vhd,1658769784,vhdl,,,,addsubunitbit_4,,,,,,,, diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.ini b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xvhdl.log b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xvhdl.log new file mode 100644 index 0000000..26d1aba --- /dev/null +++ b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xvhdl.log @@ -0,0 +1,8 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/sim_1/AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AddSubUnitBit_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity FA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity HA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.sim/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 diff --git a/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xvhdl.pb b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..469a8a2 Binary files /dev/null and b/LAB10.sim/TB_AddSubUnitBit_4/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3.tcl b/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3_behav.wdb b/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3_behav.wdb new file mode 100644 index 0000000..9c650fa Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3_behav.wdb differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3_vhdl.prj b/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3_vhdl.prj new file mode 100644 index 0000000..02e9d53 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/TB_AdderBit_3_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/new/AdderBit_3.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/FA.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/HA.vhd" \ +"../../../../LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/compile.bat b/LAB10.sim/TB_AdderBit_3/behav/xsim/compile.bat new file mode 100644 index 0000000..0eed934 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Fri Jul 29 13:46:18 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_AdderBit_3_vhdl.prj" +call xvhdl --incr --relax -prj TB_AdderBit_3_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/compile.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/compile.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/elaborate.bat b/LAB10.sim/TB_AdderBit_3/behav/xsim/elaborate.bat new file mode 100644 index 0000000..a64bd56 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Fri Jul 29 13:46:21 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AdderBit_3_behav xil_defaultlib.TB_AdderBit_3 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/elaborate.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/elaborate.log new file mode 100644 index 0000000..0efa4cb --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/elaborate.log @@ -0,0 +1,7 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AdderBit_3_behav xil_defaultlib.TB_AdderBit_3 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/simulate.bat b/LAB10.sim/TB_AdderBit_3/behav/xsim/simulate.bat new file mode 100644 index 0000000..b3ada1c --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Fri Jul 29 13:46:25 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_AdderBit_3_behav -key {Behavioral:TB_AdderBit_3:Functional:TB_AdderBit_3} -tclbatch TB_AdderBit_3.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/simulate.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.jou b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.jou new file mode 100644 index 0000000..5582dba --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Jul 29 13:47:00 2022 +# Process ID: 23160 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log new file mode 100644 index 0000000..74c6ff5 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Jul 29 13:47:00 2022 +# Process ID: 23160 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Fri Jul 29 13:47:00 2022... diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_10800.backup.jou b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_10800.backup.jou new file mode 100644 index 0000000..9eea75a --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_10800.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:06:57 2022 +# Process ID: 10800 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_10800.backup.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_10800.backup.log new file mode 100644 index 0000000..0efd597 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_10800.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:06:57 2022 +# Process ID: 10800 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 04:06:57 2022... diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_24228.backup.jou b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_24228.backup.jou new file mode 100644 index 0000000..4316bb2 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_24228.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:19 2022 +# Process ID: 24228 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_24228.backup.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_24228.backup.log new file mode 100644 index 0000000..df27bd1 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_24228.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:19 2022 +# Process ID: 24228 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 11:59:19 2022... diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_31148.backup.jou b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_31148.backup.jou new file mode 100644 index 0000000..d203bb2 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_31148.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 01:47:02 2022 +# Process ID: 31148 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_31148.backup.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_31148.backup.log new file mode 100644 index 0000000..d052ad5 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_31148.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 01:47:02 2022 +# Process ID: 31148 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 01:47:03 2022... diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_8724.backup.jou b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_8724.backup.jou new file mode 100644 index 0000000..70f8b18 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_8724.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 04:07:09 2022 +# Process ID: 8724 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_8724.backup.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_8724.backup.log new file mode 100644 index 0000000..31f6baf --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk_8724.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 04:07:09 2022 +# Process ID: 8724 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 04:07:09 2022... diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xelab.pb b/LAB10.sim/TB_AdderBit_3/behav/xsim/xelab.pb new file mode 100644 index 0000000..72e72cb Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/Compile_Options.txt b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/Compile_Options.txt new file mode 100644 index 0000000..31315bb --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_AdderBit_3_behav" "xil_defaultlib.TB_AdderBit_3" -log "elaborate.log" diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/TempBreakPointFile.txt b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..b1f24f9 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_1.c b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_1.c new file mode 100644 index 0000000..b58e1f7 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_1.c @@ -0,0 +1,103 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_38(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[6] = {(funcp)execute_38, (funcp)execute_17, (funcp)execute_18, (funcp)execute_12, (funcp)execute_13, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 6; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_AdderBit_3_behav/xsim.reloc", (void **)funcTab, 6); + iki_vhdl_file_variable_register(dp + 6352); + iki_vhdl_file_variable_register(dp + 6408); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_AdderBit_3_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_AdderBit_3_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_AdderBit_3_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_AdderBit_3_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_AdderBit_3_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..046ef94 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..a71a2bb --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658961427 +1659082619 +6 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.dbg b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.dbg new file mode 100644 index 0000000..620cbc9 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.mem b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.mem new file mode 100644 index 0000000..a0c6204 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.mem differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.reloc b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.reloc new file mode 100644 index 0000000..d04bf6a Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.rlx b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.rlx new file mode 100644 index 0000000..fc720cf --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 2689242358053468812 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AdderBit_3_behav xil_defaultlib.TB_AdderBit_3" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_AdderBit_3_behav/xsimk.exe\" \"xsim.dir/TB_AdderBit_3_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_AdderBit_3_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.rtti b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.rtti new file mode 100644 index 0000000..7c32079 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.svtype b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.type b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.type new file mode 100644 index 0000000..20eba0b Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.type differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.xdbg b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.xdbg new file mode 100644 index 0000000..286b825 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimSettings.ini b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimcrash.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimk.exe b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimk.exe new file mode 100644 index 0000000..7c9ea3f Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimkernel.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimkernel.log new file mode 100644 index 0000000..723bc25 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/TB_AdderBit_3_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_AdderBit_3_behav/xsimk.exe -simmode gui -wdb TB_AdderBit_3_behav.wdb -simrunnum 0 -socket 59471 +Design successfully loaded +Design Loading Memory Usage: 6440 KB (Peak: 6440 KB) +Design Loading CPU Usage: 31 ms +Simulation completed +Simulation Memory Usage: 7052 KB (Peak: 7052 KB) +Simulation CPU Usage: 31 ms diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/adderbit_3.vdb b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/adderbit_3.vdb new file mode 100644 index 0000000..8d3fab0 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/adderbit_3.vdb differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb new file mode 100644 index 0000000..a60bb59 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb new file mode 100644 index 0000000..3536344 Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/tb_adderbit_3.vdb b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/tb_adderbit_3.vdb new file mode 100644 index 0000000..7bb17fc Binary files /dev/null and b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/tb_adderbit_3.vdb differ diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..a68224c --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,8 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd,1658780154,vhdl,,,,tb_adderbit_3,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd,1658769782,vhdl,,,,fa,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd,1658769782,vhdl,,,,ha,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd,1658864815,vhdl,,,,adderbit_3,,,,,,,, diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.ini b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xvhdl.log b/LAB10.sim/TB_AdderBit_3/behav/xsim/xvhdl.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_AdderBit_3/behav/xsim/xvhdl.pb b/LAB10.sim/TB_AdderBit_3/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/LAB10.sim/TB_AdderBit_3/behav/xsim/xvhdl.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8.tcl b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8_behav.wdb b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8_behav.wdb new file mode 100644 index 0000000..343ff6b Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8_behav.wdb differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8_vhdl.prj b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8_vhdl.prj new file mode 100644 index 0000000..365380b --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/TB_Decoder_3_to_8_vhdl.prj @@ -0,0 +1,8 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd" \ +"../../../../LAB10.srcs/TB_Decoder_3_to_8/new/TB_Decoder_3_to_8.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/compile.bat b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/compile.bat new file mode 100644 index 0000000..beea44c --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Mon Jul 25 21:57:46 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_Decoder_3_to_8_vhdl.prj" +call xvhdl --incr --relax -prj TB_Decoder_3_to_8_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/compile.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/compile.log new file mode 100644 index 0000000..45c6d5f --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/compile.log @@ -0,0 +1,6 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Decoder_3_to_8/new/TB_Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Decoder_3_to_8 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/elaborate.bat b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/elaborate.bat new file mode 100644 index 0000000..55270f2 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Mon Jul 25 21:57:48 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Decoder_3_to_8_behav xil_defaultlib.TB_Decoder_3_to_8 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/elaborate.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/elaborate.log new file mode 100644 index 0000000..0d1a573 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/elaborate.log @@ -0,0 +1,16 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Decoder_3_to_8_behav xil_defaultlib.TB_Decoder_3_to_8 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_decoder_3_to_8 +Built simulation snapshot TB_Decoder_3_to_8_behav diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/simulate.bat b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/simulate.bat new file mode 100644 index 0000000..e0f1af3 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Mon Jul 25 21:57:50 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_Decoder_3_to_8_behav -key {Behavioral:TB_Decoder_3_to_8:Functional:TB_Decoder_3_to_8} -tclbatch TB_Decoder_3_to_8.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/simulate.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.jou b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.jou new file mode 100644 index 0000000..944b0c4 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 19:23:23 2022 +# Process ID: 24756 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.log new file mode 100644 index 0000000..922facb --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 19:23:23 2022 +# Process ID: 24756 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 19:23:23 2022... diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk_2052.backup.jou b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk_2052.backup.jou new file mode 100644 index 0000000..3decfb5 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk_2052.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 19:21:23 2022 +# Process ID: 2052 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk_2052.backup.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk_2052.backup.log new file mode 100644 index 0000000..91e295e --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk_2052.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 19:21:23 2022 +# Process ID: 2052 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 19:21:23 2022... diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xelab.pb b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xelab.pb new file mode 100644 index 0000000..34ff72f Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/Compile_Options.txt b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/Compile_Options.txt new file mode 100644 index 0000000..692e434 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Decoder_3_to_8_behav" "xil_defaultlib.TB_Decoder_3_to_8" -log "elaborate.log" diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..7cdb0e5 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_1.c b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_1.c new file mode 100644 index 0000000..4e04f87 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_23(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void transaction_5(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_6(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_23, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)transaction_5, (funcp)transaction_6, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Decoder_3_to_8_behav/xsim.reloc", (void **)funcTab, 12); + iki_vhdl_file_variable_register(dp + 4040); + iki_vhdl_file_variable_register(dp + 4096); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Decoder_3_to_8_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Decoder_3_to_8_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Decoder_3_to_8_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Decoder_3_to_8_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Decoder_3_to_8_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..f5770a6 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..bf1b49e --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658757081 +1658757201 +7 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/xsim_webtalk.tcl b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..03d7ce6 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Mon Jul 25 22:50:26 2022" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "42d18b2525b056b7b3ef00b7402b363d" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "f330702f431647419194c50ab3747a93" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "6" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2112 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "4" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6964_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3153998198 -regid "" -xml C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.dbg b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.dbg new file mode 100644 index 0000000..61fcaf9 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.mem b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.mem new file mode 100644 index 0000000..f2b1d99 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.reloc b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.reloc new file mode 100644 index 0000000..e051878 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.rlx b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.rlx new file mode 100644 index 0000000..25e0d98 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 1497540949433926728 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Decoder_3_to_8_behav xil_defaultlib.TB_Decoder_3_to_8" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Decoder_3_to_8_behav/xsimk.exe\" \"xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Decoder_3_to_8_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.rtti b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.rtti new file mode 100644 index 0000000..4ca2b54 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.svtype b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.type b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.type new file mode 100644 index 0000000..13a2381 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.type differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.xdbg b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.xdbg new file mode 100644 index 0000000..89c2049 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimSettings.ini b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimcrash.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimk.exe b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimk.exe new file mode 100644 index 0000000..d4d6d37 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimkernel.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimkernel.log new file mode 100644 index 0000000..a1b4c06 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/TB_Decoder_3_to_8_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_Decoder_3_to_8_behav/xsimk.exe -simmode gui -wdb TB_Decoder_3_to_8_behav.wdb -simrunnum 0 -socket 62567 +Design successfully loaded +Design Loading Memory Usage: 6424 KB (Peak: 6424 KB) +Design Loading CPU Usage: 15 ms +Simulation completed +Simulation Memory Usage: 6964 KB (Peak: 6964 KB) +Simulation CPU Usage: 30 ms diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb new file mode 100644 index 0000000..6480829 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb new file mode 100644 index 0000000..fa60309 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/tb_decoder_3_to_8.vdb b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/tb_decoder_3_to_8.vdb new file mode 100644 index 0000000..0009a16 Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/tb_decoder_3_to_8.vdb differ diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..19147f9 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,7 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Decoder_3_to_8/new/TB_Decoder_3_to_8.vhd,1658757031,vhdl,,,,tb_decoder_3_to_8,,,,,,,, +C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd,1658766208,vhdl,,,,decoder_2_to_4,,,,,,,, +C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd,1658766300,vhdl,,,,decoder_3_to_8,,,,,,,, diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.ini b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xvhdl.log b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xvhdl.log new file mode 100644 index 0000000..45c6d5f --- /dev/null +++ b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xvhdl.log @@ -0,0 +1,6 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Decoder_3_to_8/new/TB_Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Decoder_3_to_8 diff --git a/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..eb0fd3c Binary files /dev/null and b/LAB10.sim/TB_Decoder_3_to_8/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/TB_Instruction_Decoder.vhd b/LAB10.sim/TB_Instruction_Decoder.vhd new file mode 100644 index 0000000..0157ce1 --- /dev/null +++ b/LAB10.sim/TB_Instruction_Decoder.vhd @@ -0,0 +1,120 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/25/2022 10:14:33 PM +-- Design Name: +-- Module Name: TB_Instruction_Decoder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Instruction_Decoder is +-- Port ( ); +end TB_Instruction_Decoder; + +architecture Behavioral of TB_Instruction_Decoder is +component Instruction_Decoder +Port ( Instruction_Bus : in STD_LOGIC_VECTOR (11 downto 0); + Reg_Check_for_Jump : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : out STD_LOGIC_VECTOR (2 downto 0); + Load_Select : out STD_LOGIC; + Immediate_value : out STD_LOGIC_VECTOR (3 downto 0); + Register_select_01 : out STD_LOGIC_VECTOR (2 downto 0); + Register_select_02 : out STD_LOGIC_VECTOR (2 downto 0); + ADD_SUB_Select : out STD_LOGIC; + Jump_Flag : out STD_LOGIC; + Address_to_jump : out STD_LOGIC_VECTOR (2 downto 0)); +end component; +signal Instruction_Bus :STD_LOGIC_VECTOR (11 downto 0); +signal Reg_Check_for_Jump,Immediate_value : STD_LOGIC_VECTOR (3 downto 0); +signal Reg_Enable, Register_select_01, Register_select_02, Address_to_jump :STD_LOGIC_VECTOR (2 downto 0); +signal Load_Select :STD_LOGIC; +signal ADD_SUB_Select : STD_LOGIC; +signal Jump_Flag : STD_LOGIC; + +begin +UUT: Instruction_Decoder +port map( +Instruction_Bus=>Instruction_Bus, +Reg_Check_for_Jump=>Reg_Check_for_Jump, +Immediate_value=>Immediate_value, +Reg_Enable=>Reg_Enable, +Register_select_01=>Register_select_01, +Register_select_02=>Register_select_02, +Address_to_jump=>Address_to_jump, +Load_Select=>Load_Select, +ADD_SUB_Select=>ADD_SUB_Select, +Jump_Flag=>Jump_Flag +); +process +begin + + +Instruction_Bus<="100010001010"; +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="100100000001"; +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="010100000000"; --2 +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="000010100000"; --3 +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="110010000111"; --4 +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="110000000011"; --5 +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="111111111111"; --6 +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="111111111111"; --7 +Reg_Check_for_Jump<="0001"; +wait for 100ns; + +Instruction_Bus<="000010100000"; --3 +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="000010100000"; --3 +Reg_Check_for_Jump<="0000"; +wait for 100ns; + +Instruction_Bus<="110010000111"; --4 +Reg_Check_for_Jump<="0000"; +wait ; +end process; +end Behavioral; diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder.tcl b/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder_behav.wdb b/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder_behav.wdb new file mode 100644 index 0000000..60454b1 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder_behav.wdb differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder_vhdl.prj b/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder_vhdl.prj new file mode 100644 index 0000000..5a8d7fa --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/TB_Instruction_Decoder_vhdl.prj @@ -0,0 +1,8 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" \ +"../../../../LAB10.srcs/sources_1/new/Instruction_Decoder.vhd" \ +"../../../TB_Instruction_Decoder.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/compile.bat b/LAB10.sim/TB_Instruction_decoder/behav/xsim/compile.bat new file mode 100644 index 0000000..1d58a2e --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 28 04:01:44 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +call xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/compile.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/compile.log new file mode 100644 index 0000000..2b1ff59 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/compile.log @@ -0,0 +1,6 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Instruction_Decoder diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.bat b/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.bat new file mode 100644 index 0000000..cbbbf12 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 28 04:01:47 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.log new file mode 100644 index 0000000..6897937 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.log @@ -0,0 +1,16 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_instruction_decoder +Built simulation snapshot TB_Instruction_Decoder_behav diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/simulate.bat b/LAB10.sim/TB_Instruction_decoder/behav/xsim/simulate.bat new file mode 100644 index 0000000..a3eeb3f --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 28 04:01:52 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_Instruction_Decoder_behav -key {Behavioral:TB_Instruction_decoder:Functional:TB_Instruction_Decoder} -tclbatch TB_Instruction_Decoder.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/simulate.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.jou b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.jou new file mode 100644 index 0000000..54202ed --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:36 2022 +# Process ID: 21484 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log new file mode 100644 index 0000000..94d553e --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:36 2022 +# Process ID: 21484 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 11:59:36 2022... diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_16548.backup.jou b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_16548.backup.jou new file mode 100644 index 0000000..1899c50 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_16548.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 22:37:43 2022 +# Process ID: 16548 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_16548.backup.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_16548.backup.log new file mode 100644 index 0000000..90a7def --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_16548.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 22:37:43 2022 +# Process ID: 16548 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 22:37:44 2022... diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_21172.backup.jou b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_21172.backup.jou new file mode 100644 index 0000000..bbe9c00 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_21172.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 04:01:52 2022 +# Process ID: 21172 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_21172.backup.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_21172.backup.log new file mode 100644 index 0000000..2ba2c66 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_21172.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 04:01:52 2022 +# Process ID: 21172 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 04:01:52 2022... diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_24444.backup.jou b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_24444.backup.jou new file mode 100644 index 0000000..9ccbefc --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_24444.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 22:38:44 2022 +# Process ID: 24444 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_24444.backup.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_24444.backup.log new file mode 100644 index 0000000..869d0d4 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk_24444.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 22:38:44 2022 +# Process ID: 24444 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 22:38:45 2022... diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xelab.pb b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xelab.pb new file mode 100644 index 0000000..9a5908b Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/Compile_Options.txt b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/Compile_Options.txt new file mode 100644 index 0000000..a4d10ea --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Instruction_Decoder_behav" "xil_defaultlib.TB_Instruction_Decoder" -log "elaborate.log" diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..01acf4b Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_1.c b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_1.c new file mode 100644 index 0000000..a395b85 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_1.c @@ -0,0 +1,119 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_26(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_10(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_11(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_12(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_13(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[22] = {(funcp)execute_26, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_10, (funcp)transaction_11, (funcp)transaction_12, (funcp)transaction_13}; +const int NumRelocateId= 22; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Instruction_Decoder_behav/xsim.reloc", (void **)funcTab, 22); + iki_vhdl_file_variable_register(dp + 5888); + iki_vhdl_file_variable_register(dp + 5944); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Instruction_Decoder_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Instruction_Decoder_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Instruction_Decoder_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Instruction_Decoder_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Instruction_Decoder_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..fa43f78 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..5e444d1 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658961110 +1658989775 +17 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/usage_statistics_ext_xsim.html b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..47ca978 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedMon Jul 25 22:38:43 2022os_platformWIN64
product_versionXSIM v2018.2 (64-bit)project_idf330702f431647419194c50ab3747a93
project_iteration2random_id42d18b2525b056b7b3ef00b7402b363d
registration_id42d18b2525b056b7b3ef00b7402b363droute_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-10210U CPU @ 1.60GHzcpu_speed2112 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=0runtime=1 ussimulation_memory=6956_KBsimulation_time=0.03_sec
trace_waveform=true
+

+ + diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/usage_statistics_ext_xsim.xml b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..9e47529 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.dbg b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.dbg new file mode 100644 index 0000000..040548a Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.mem b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.mem new file mode 100644 index 0000000..df32ca1 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.reloc b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.reloc new file mode 100644 index 0000000..708f433 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.rlx b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.rlx new file mode 100644 index 0000000..64ddaff --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 1260905375183720612 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Instruction_Decoder_behav/xsimk.exe\" \"xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Instruction_Decoder_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.rtti b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.rtti new file mode 100644 index 0000000..a409f94 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.svtype b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.type b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.type new file mode 100644 index 0000000..29f3b0f Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.type differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.xdbg b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.xdbg new file mode 100644 index 0000000..344005b Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimSettings.ini b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimcrash.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimk.exe b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimk.exe new file mode 100644 index 0000000..573e7f2 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimkernel.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimkernel.log new file mode 100644 index 0000000..5b7cad0 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/TB_Instruction_Decoder_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_Instruction_Decoder_behav/xsimk.exe -simmode gui -wdb TB_Instruction_Decoder_behav.wdb -simrunnum 0 -socket 63003 +Design successfully loaded +Design Loading Memory Usage: 6464 KB (Peak: 6464 KB) +Design Loading CPU Usage: 109 ms +Simulation completed +Simulation Memory Usage: 7072 KB (Peak: 7072 KB) +Simulation CPU Usage: 155 ms diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb new file mode 100644 index 0000000..0f31929 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/instruction_decoder.vdb b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/instruction_decoder.vdb new file mode 100644 index 0000000..352837c Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/instruction_decoder.vdb differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/tb_instruction_decoder.vdb b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/tb_instruction_decoder.vdb new file mode 100644 index 0000000..f327fc2 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/tb_instruction_decoder.vdb differ diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..faefa47 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,7 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_Decoder.vhd,1658774576,vhdl,,,,tb_instruction_decoder,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd,1658864626,vhdl,,,,decoder_2_to_4,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd,1658863814,vhdl,,,,instruction_decoder,,,,,,,, diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.ini b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xvhdl.log b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xvhdl.log new file mode 100644 index 0000000..2b1ff59 --- /dev/null +++ b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xvhdl.log @@ -0,0 +1,6 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Instruction_Decoder diff --git a/LAB10.sim/TB_Instruction_decoder/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..b9a4488 Binary files /dev/null and b/LAB10.sim/TB_Instruction_decoder/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit.tcl b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit_behav.wdb b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit_behav.wdb new file mode 100644 index 0000000..9cd1d64 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit_behav.wdb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit_vhdl.prj b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit_vhdl.prj new file mode 100644 index 0000000..e76bf28 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/TB_Mux_2_to_1_3bit_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/TB_Mux_2_to_1_3bit/imports/new/Mux_2_to_1_3bit.vhd" \ +"../../../../LAB10.srcs/TB_Mux_2_to_1_3bit/new/TB_Mux_2_to_1_3bit.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/compile.bat b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/compile.bat new file mode 100644 index 0000000..58bacc7 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 28 03:44:49 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_Mux_2_to_1_3bit_vhdl.prj" +call xvhdl --incr --relax -prj TB_Mux_2_to_1_3bit_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/compile.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/compile.log new file mode 100644 index 0000000..6c8a615 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/compile.log @@ -0,0 +1,4 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_3bit/imports/new/Mux_2_to_1_3bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_3bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_3bit/new/TB_Mux_2_to_1_3bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Mux_2_to_1_3bit diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/elaborate.bat b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/elaborate.bat new file mode 100644 index 0000000..aa6eecd --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 28 03:44:52 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_2_to_1_3bit_behav xil_defaultlib.TB_Mux_2_to_1_3bit -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/elaborate.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/elaborate.log new file mode 100644 index 0000000..f003a88 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/elaborate.log @@ -0,0 +1,15 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_2_to_1_3bit_behav xil_defaultlib.TB_Mux_2_to_1_3bit -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_mux_2_to_1_3bit +Built simulation snapshot TB_Mux_2_to_1_3bit_behav diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/simulate.bat b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/simulate.bat new file mode 100644 index 0000000..45f6212 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 28 03:44:57 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_Mux_2_to_1_3bit_behav -key {Behavioral:TB_Mux_2_to_1_3bit:Functional:TB_Mux_2_to_1_3bit} -tclbatch TB_Mux_2_to_1_3bit.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/simulate.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.jou b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.jou new file mode 100644 index 0000000..2eb7dd5 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 12:00:11 2022 +# Process ID: 22816 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log new file mode 100644 index 0000000..8bf1a78 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 12:00:11 2022 +# Process ID: 22816 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 12:00:11 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_16236.backup.jou b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_16236.backup.jou new file mode 100644 index 0000000..05a63d5 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_16236.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:43:57 2022 +# Process ID: 16236 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_16236.backup.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_16236.backup.log new file mode 100644 index 0000000..ffb31a5 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_16236.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:43:57 2022 +# Process ID: 16236 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 20:43:57 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_19368.backup.jou b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_19368.backup.jou new file mode 100644 index 0000000..f0b251c --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_19368.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:42:12 2022 +# Process ID: 19368 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_19368.backup.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_19368.backup.log new file mode 100644 index 0000000..4652c6e --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_19368.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:42:12 2022 +# Process ID: 19368 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 20:42:12 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_32420.backup.jou b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_32420.backup.jou new file mode 100644 index 0000000..c5b1a23 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_32420.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:44:57 2022 +# Process ID: 32420 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_32420.backup.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_32420.backup.log new file mode 100644 index 0000000..b65e162 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk_32420.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:44:57 2022 +# Process ID: 32420 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 03:44:57 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xelab.pb b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xelab.pb new file mode 100644 index 0000000..aaf2e5c Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/Compile_Options.txt b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/Compile_Options.txt new file mode 100644 index 0000000..82c9451 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Mux_2_to_1_3bit_behav" "xil_defaultlib.TB_Mux_2_to_1_3bit" -log "elaborate.log" diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..68e98b6 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_1.c b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_1.c new file mode 100644 index 0000000..b40d26a --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_1.c @@ -0,0 +1,100 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_8(char*, char *); +extern void execute_7(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[3] = {(funcp)execute_8, (funcp)execute_7, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 3; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.reloc", (void **)funcTab, 3); + iki_vhdl_file_variable_register(dp + 2608); + iki_vhdl_file_variable_register(dp + 2664); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..0fc039e Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..eecaed0 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658960095 +1658989810 +7 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.dbg b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.dbg new file mode 100644 index 0000000..a46e47a Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.mem b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.mem new file mode 100644 index 0000000..d0eade7 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.reloc b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.reloc new file mode 100644 index 0000000..c0cebb8 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.rlx b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.rlx new file mode 100644 index 0000000..a613c44 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 6395731114929238212 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_2_to_1_3bit_behav xil_defaultlib.TB_Mux_2_to_1_3bit" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimk.exe\" \"xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Mux_2_to_1_3bit_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.rtti b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.rtti new file mode 100644 index 0000000..2567ece Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.svtype b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.type b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.type new file mode 100644 index 0000000..8e0a2e2 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.type differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.xdbg b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.xdbg new file mode 100644 index 0000000..9ce3ddd Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimSettings.ini b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimcrash.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimk.exe b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimk.exe new file mode 100644 index 0000000..878ba69 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimkernel.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimkernel.log new file mode 100644 index 0000000..1130f80 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_Mux_2_to_1_3bit_behav/xsimk.exe -simmode gui -wdb TB_Mux_2_to_1_3bit_behav.wdb -simrunnum 0 -socket 62751 +Design successfully loaded +Design Loading Memory Usage: 6452 KB (Peak: 6452 KB) +Design Loading CPU Usage: 77 ms +Simulation completed +Simulation Memory Usage: 7052 KB (Peak: 7052 KB) +Simulation CPU Usage: 109 ms diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/mux_2way_3bit.vdb b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/mux_2way_3bit.vdb new file mode 100644 index 0000000..5ec75c5 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/mux_2way_3bit.vdb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_2_to_1_3bit.vdb b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_2_to_1_3bit.vdb new file mode 100644 index 0000000..16f90f1 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_2_to_1_3bit.vdb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..532e0aa --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,6 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_3bit/imports/new/Mux_2_to_1_3bit.vhd,1658769784,vhdl,,,,mux_2way_3bit,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_3bit/new/TB_Mux_2_to_1_3bit.vhd,1658769784,vhdl,,,,tb_mux_2_to_1_3bit,,,,,,,, diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.ini b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xvhdl.log b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xvhdl.log new file mode 100644 index 0000000..6c8a615 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xvhdl.log @@ -0,0 +1,4 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_3bit/imports/new/Mux_2_to_1_3bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_3bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_3bit/new/TB_Mux_2_to_1_3bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Mux_2_to_1_3bit diff --git a/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..8c43f36 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_3bit/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit.tcl b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit_behav.wdb b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit_behav.wdb new file mode 100644 index 0000000..30d5dbc Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit_behav.wdb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit_vhdl.prj b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit_vhdl.prj new file mode 100644 index 0000000..c2c0f00 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/TB_Mux_2_to_1_4bit_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd" \ +"../../../../LAB10.srcs/TB_Mux_2_to_1_4bit/new/TB_Mux_2_to_1_4bit.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/compile.bat b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/compile.bat new file mode 100644 index 0000000..b38d7cd --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 28 03:49:17 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_Mux_2_to_1_4bit_vhdl.prj" +call xvhdl --incr --relax -prj TB_Mux_2_to_1_4bit_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/compile.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/compile.log new file mode 100644 index 0000000..2c75444 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/compile.log @@ -0,0 +1,4 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_4bit/new/TB_Mux_2_to_1_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Mux_2_to_1_4bit diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/elaborate.bat b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/elaborate.bat new file mode 100644 index 0000000..f138017 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 28 03:49:21 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_2_to_1_4bit_behav xil_defaultlib.TB_Mux_2_to_1_4bit -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/elaborate.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/elaborate.log new file mode 100644 index 0000000..9ff85cd --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/elaborate.log @@ -0,0 +1,15 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_2_to_1_4bit_behav xil_defaultlib.TB_Mux_2_to_1_4bit -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_mux_2_to_1_4bit +Built simulation snapshot TB_Mux_2_to_1_4bit_behav diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/simulate.bat b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/simulate.bat new file mode 100644 index 0000000..7496cd2 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 28 03:49:28 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_Mux_2_to_1_4bit_behav -key {Behavioral:TB_Mux_2_to_1_4bit:Functional:TB_Mux_2_to_1_4bit} -tclbatch TB_Mux_2_to_1_4bit.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/simulate.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.jou b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.jou new file mode 100644 index 0000000..fc1448d --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 12:00:02 2022 +# Process ID: 28812 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log new file mode 100644 index 0000000..999f118 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 12:00:02 2022 +# Process ID: 28812 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 12:00:02 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_15508.backup.jou b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_15508.backup.jou new file mode 100644 index 0000000..0ef48d6 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_15508.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:20:28 2022 +# Process ID: 15508 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_15508.backup.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_15508.backup.log new file mode 100644 index 0000000..9a62e30 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_15508.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:20:28 2022 +# Process ID: 15508 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 20:20:28 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_28296.backup.jou b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_28296.backup.jou new file mode 100644 index 0000000..30dc8bc --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_28296.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:49:27 2022 +# Process ID: 28296 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_28296.backup.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_28296.backup.log new file mode 100644 index 0000000..2c20b0c --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_28296.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:49:27 2022 +# Process ID: 28296 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 03:49:27 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_7576.backup.jou b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_7576.backup.jou new file mode 100644 index 0000000..8e85c83 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_7576.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:18:38 2022 +# Process ID: 7576 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_7576.backup.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_7576.backup.log new file mode 100644 index 0000000..3da535d --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk_7576.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 20:18:38 2022 +# Process ID: 7576 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 20:18:38 2022... diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xelab.pb b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xelab.pb new file mode 100644 index 0000000..56b22f2 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/Compile_Options.txt b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/Compile_Options.txt new file mode 100644 index 0000000..9f4e4fd --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Mux_2_to_1_4bit_behav" "xil_defaultlib.TB_Mux_2_to_1_4bit" -log "elaborate.log" diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..0bd09c2 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_1.c b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_1.c new file mode 100644 index 0000000..b8c213b --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_1.c @@ -0,0 +1,100 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_8(char*, char *); +extern void execute_7(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[3] = {(funcp)execute_8, (funcp)execute_7, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 3; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.reloc", (void **)funcTab, 3); + iki_vhdl_file_variable_register(dp + 2608); + iki_vhdl_file_variable_register(dp + 2664); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..e8eedec Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..cc70a9e --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658960365 +1658989801 +7 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.dbg b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.dbg new file mode 100644 index 0000000..b6aa8e9 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.mem b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.mem new file mode 100644 index 0000000..26ea030 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.reloc b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.reloc new file mode 100644 index 0000000..dc3db6f Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.rlx b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.rlx new file mode 100644 index 0000000..6405dd7 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 6758640008996849246 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_2_to_1_4bit_behav xil_defaultlib.TB_Mux_2_to_1_4bit" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimk.exe\" \"xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Mux_2_to_1_4bit_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.rtti b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.rtti new file mode 100644 index 0000000..9fc408e Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.svtype b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.type b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.type new file mode 100644 index 0000000..72032b5 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.type differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.xdbg b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.xdbg new file mode 100644 index 0000000..29723e4 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimSettings.ini b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimcrash.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimk.exe b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimk.exe new file mode 100644 index 0000000..68d8b86 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimkernel.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimkernel.log new file mode 100644 index 0000000..cc6c048 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_Mux_2_to_1_4bit_behav/xsimk.exe -simmode gui -wdb TB_Mux_2_to_1_4bit_behav.wdb -simrunnum 0 -socket 62812 +Design successfully loaded +Design Loading Memory Usage: 6456 KB (Peak: 6456 KB) +Design Loading CPU Usage: 61 ms +Simulation completed +Simulation Memory Usage: 7048 KB (Peak: 7048 KB) +Simulation CPU Usage: 61 ms diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/mux_2way_4bit.vdb b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/mux_2way_4bit.vdb new file mode 100644 index 0000000..03a8962 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/mux_2way_4bit.vdb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_2_to_1_4bit.vdb b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_2_to_1_4bit.vdb new file mode 100644 index 0000000..f3d7167 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_2_to_1_4bit.vdb differ diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..eb8936c --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,6 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_4bit/new/TB_Mux_2_to_1_4bit.vhd,1658769784,vhdl,,,,tb_mux_2_to_1_4bit,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd,1658864677,vhdl,,,,mux_2way_4bit,,,,,,,, diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.ini b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xvhdl.log b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xvhdl.log new file mode 100644 index 0000000..2c75444 --- /dev/null +++ b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xvhdl.log @@ -0,0 +1,4 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_2_to_1_4bit/new/TB_Mux_2_to_1_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Mux_2_to_1_4bit diff --git a/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..ec5b444 Binary files /dev/null and b/LAB10.sim/TB_Mux_2_to_1_4bit/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/TB_Mux_8_to_1.vhd b/LAB10.sim/TB_Mux_8_to_1.vhd new file mode 100644 index 0000000..1b6cc87 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1.vhd @@ -0,0 +1,43 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/23/2022 10:40:58 PM +-- Design Name: +-- Module Name: TB_Mux_8_to_1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Mux_8_to_1 is +-- Port ( ); +end TB_Mux_8_to_1; + +architecture Behavioral of TB_Mux_8_to_1 is + +begin + + +end Behavioral; diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1.tcl b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1_behav.wdb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1_behav.wdb new file mode 100644 index 0000000..d2cedec Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1_behav.wdb differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1_vhdl.prj b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1_vhdl.prj new file mode 100644 index 0000000..ff8128a --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/TB_Mux_8_to_1_vhdl.prj @@ -0,0 +1,10 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" \ +"../../../../LAB10.srcs/TB_Mux_8_to_1/imports/new/Decoder_3_to_8.vhd" \ +"../../../../LAB10.srcs/TB_Mux_8_to_1/imports/new/Mux_8way_4bit.vhd" \ +"../../../../LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd" \ +"../../../../LAB10.srcs/TB_Mux_8_to_1/imports/LAB10.sim/TB_Mux_8_to_1.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/compile.bat b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/compile.bat new file mode 100644 index 0000000..b9db122 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 28 03:56:34 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_Mux_8_to_1_vhdl.prj" +call xvhdl --incr --relax -prj TB_Mux_8_to_1_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/compile.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/compile.log new file mode 100644 index 0000000..eb5b341 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/compile.log @@ -0,0 +1,10 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/new/Mux_8way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_8way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity quad_tri_state_buffer +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/LAB10.sim/TB_Mux_8_to_1.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Mux_8_to_1 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/elaborate.bat b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..62cf164 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 28 03:56:37 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_8_to_1_behav xil_defaultlib.TB_Mux_8_to_1 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/elaborate.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..5098305 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/elaborate.log @@ -0,0 +1,18 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_8_to_1_behav xil_defaultlib.TB_Mux_8_to_1 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_mux_8_to_1 +Built simulation snapshot TB_Mux_8_to_1_behav diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/simulate.bat b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..27ec273 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 28 03:56:44 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_Mux_8_to_1_behav -key {Behavioral:TB_Mux_8_to_1:Functional:TB_Mux_8_to_1} -tclbatch TB_Mux_8_to_1.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/simulate.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.jou b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..8081c29 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:54 2022 +# Process ID: 1768 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log new file mode 100644 index 0000000..7c994b5 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:54 2022 +# Process ID: 1768 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 11:59:54 2022... diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_19528.backup.jou b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_19528.backup.jou new file mode 100644 index 0000000..24c917f --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_19528.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 17:43:07 2022 +# Process ID: 19528 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_19528.backup.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_19528.backup.log new file mode 100644 index 0000000..9478d7b --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_19528.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 17:43:07 2022 +# Process ID: 19528 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 17:43:07 2022... diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_21780.backup.jou b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_21780.backup.jou new file mode 100644 index 0000000..0c82288 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_21780.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:56:43 2022 +# Process ID: 21780 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_21780.backup.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_21780.backup.log new file mode 100644 index 0000000..e74580c --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_21780.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:56:43 2022 +# Process ID: 21780 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 03:56:43 2022... diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_5768.backup.jou b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_5768.backup.jou new file mode 100644 index 0000000..9263eb0 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_5768.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 17:44:42 2022 +# Process ID: 5768 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_5768.backup.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_5768.backup.log new file mode 100644 index 0000000..7aa5a32 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk_5768.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 17:44:42 2022 +# Process ID: 5768 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Mux_8_to_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 17:44:42 2022... diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xelab.pb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..115d74d Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/Compile_Options.txt b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/Compile_Options.txt new file mode 100644 index 0000000..fc81cdd --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Mux_8_to_1_behav" "xil_defaultlib.TB_Mux_8_to_1" -log "elaborate.log" diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..f8a7f3b Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_1.c b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_1.c new file mode 100644 index 0000000..027752c --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_1.c @@ -0,0 +1,114 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_44(char*, char *); +extern void execute_43(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_28(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_12(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[17] = {(funcp)execute_44, (funcp)execute_43, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_28, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_12}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Mux_8_to_1_behav/xsim.reloc", (void **)funcTab, 17); + iki_vhdl_file_variable_register(dp + 7424); + iki_vhdl_file_variable_register(dp + 7480); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Mux_8_to_1_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Mux_8_to_1_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Mux_8_to_1_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Mux_8_to_1_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Mux_8_to_1_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..5142e17 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..7795d72 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658960800 +1658989793 +37 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.dbg b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.dbg new file mode 100644 index 0000000..fd67992 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.mem b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.mem new file mode 100644 index 0000000..64600ef Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.reloc b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.reloc new file mode 100644 index 0000000..d117e17 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.rlx b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.rlx new file mode 100644 index 0000000..b7a8591 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 7479852458130008134 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Mux_8_to_1_behav xil_defaultlib.TB_Mux_8_to_1" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Mux_8_to_1_behav/xsimk.exe\" \"xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Mux_8_to_1_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.rtti b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.rtti new file mode 100644 index 0000000..26507e7 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.svtype b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.type b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.type new file mode 100644 index 0000000..d05d706 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.type differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.xdbg b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.xdbg new file mode 100644 index 0000000..905a208 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimSettings.ini b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimcrash.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimk.exe b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimk.exe new file mode 100644 index 0000000..28fdec1 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimkernel.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimkernel.log new file mode 100644 index 0000000..738ad3d --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/TB_Mux_8_to_1_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_Mux_8_to_1_behav/xsimk.exe -simmode gui -wdb TB_Mux_8_to_1_behav.wdb -simrunnum 0 -socket 62919 +Design successfully loaded +Design Loading Memory Usage: 6472 KB (Peak: 6472 KB) +Design Loading CPU Usage: 46 ms +Simulation completed +Simulation Memory Usage: 7076 KB (Peak: 7076 KB) +Simulation CPU Usage: 46 ms diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb new file mode 100644 index 0000000..01a4c6a Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb new file mode 100644 index 0000000..1abf1e1 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/mux_8way_4bit.vdb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/mux_8way_4bit.vdb new file mode 100644 index 0000000..8d7f00d Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/mux_8way_4bit.vdb differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/quad_tri_state_buffer.vdb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/quad_tri_state_buffer.vdb new file mode 100644 index 0000000..64b9d80 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/quad_tri_state_buffer.vdb differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_8_to_1.vdb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_8_to_1.vdb new file mode 100644 index 0000000..e09a69e Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/tb_mux_8_to_1.vdb differ diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..f6567b8 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,9 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/LAB10.sim/TB_Mux_8_to_1.vhd,1658769784,vhdl,,,,tb_mux_8_to_1,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/new/Decoder_3_to_8.vhd,1658769784,vhdl,,,,decoder_3_to_8,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/new/Mux_8way_4bit.vhd,1658769784,vhdl,,,,mux_8way_4bit,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd,1658864626,vhdl,,,,decoder_2_to_4,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd,1658864738,vhdl,,,,quad_tri_state_buffer,,,,,,,, diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.ini b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xvhdl.log b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xvhdl.log new file mode 100644 index 0000000..eb5b341 --- /dev/null +++ b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xvhdl.log @@ -0,0 +1,10 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/new/Mux_8way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_8way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity quad_tri_state_buffer +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Mux_8_to_1/imports/LAB10.sim/TB_Mux_8_to_1.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Mux_8_to_1 diff --git a/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..4a87cb5 Binary files /dev/null and b/LAB10.sim/TB_Mux_8_to_1/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/TB_Processor.tcl b/LAB10.sim/TB_Processor/behav/xsim/TB_Processor.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/TB_Processor.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Processor/behav/xsim/TB_Processor_behav.wdb b/LAB10.sim/TB_Processor/behav/xsim/TB_Processor_behav.wdb new file mode 100644 index 0000000..47b6c34 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/TB_Processor_behav.wdb differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/TB_Processor_vhdl.prj b/LAB10.sim/TB_Processor/behav/xsim/TB_Processor_vhdl.prj new file mode 100644 index 0000000..765b10e --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/TB_Processor_vhdl.prj @@ -0,0 +1,25 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd" \ +"../../../../LAB10.srcs/sources_1/new/AdderBit_3.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/FA.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/HA.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd" \ +"../../../../LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd" \ +"../../../../LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd" \ +"../../../../LAB10.srcs/sources_1/new/Processor.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Program_counter.vhd" \ +"../../../../LAB10.srcs/sources_1/new/Program_counter.vhd" \ +"../../../../LAB10.srcs/sources_1/new/R7_7_seg.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Reg.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Register_bank.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd" \ +"../../../../LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd" \ +"../../../../LAB10.srcs/TB_Processor/new/TB_Processor.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Processor/behav/xsim/compile.bat b/LAB10.sim/TB_Processor/behav/xsim/compile.bat new file mode 100644 index 0000000..48e86e3 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Fri Jul 29 13:46:41 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +call xvhdl --incr --relax -prj TB_Processor_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Processor/behav/xsim/compile.log b/LAB10.sim/TB_Processor/behav/xsim/compile.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Processor/behav/xsim/elaborate.bat b/LAB10.sim/TB_Processor/behav/xsim/elaborate.bat new file mode 100644 index 0000000..992a349 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Fri Jul 29 13:46:42 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Processor/behav/xsim/elaborate.log b/LAB10.sim/TB_Processor/behav/xsim/elaborate.log new file mode 100644 index 0000000..cc4381c --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/elaborate.log @@ -0,0 +1,7 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel diff --git a/LAB10.sim/TB_Processor/behav/xsim/simulate.bat b/LAB10.sim/TB_Processor/behav/xsim/simulate.bat new file mode 100644 index 0000000..c5e2f3d --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Fri Jul 29 13:46:45 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch TB_Processor.tcl -view C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/TB_Processor_behav.wcfg -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Processor/behav/xsim/simulate.log b/LAB10.sim/TB_Processor/behav/xsim/simulate.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk.jou b/LAB10.sim/TB_Processor/behav/xsim/webtalk.jou new file mode 100644 index 0000000..9857f1e --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed Jul 27 15:47:05 2022 +# Process ID: 7544 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk.log b/LAB10.sim/TB_Processor/behav/xsim/webtalk.log new file mode 100644 index 0000000..98df979 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed Jul 27 15:47:05 2022 +# Process ID: 7544 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Wed Jul 27 15:47:05 2022... diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk_22616.backup.jou b/LAB10.sim/TB_Processor/behav/xsim/webtalk_22616.backup.jou new file mode 100644 index 0000000..d1d75b9 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk_22616.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:02:03 2022 +# Process ID: 22616 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk_22616.backup.log b/LAB10.sim/TB_Processor/behav/xsim/webtalk_22616.backup.log new file mode 100644 index 0000000..8e68422 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk_22616.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:02:03 2022 +# Process ID: 22616 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 04:02:03 2022... diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk_26844.backup.jou b/LAB10.sim/TB_Processor/behav/xsim/webtalk_26844.backup.jou new file mode 100644 index 0000000..0737573 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk_26844.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:03:43 2022 +# Process ID: 26844 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk_26844.backup.log b/LAB10.sim/TB_Processor/behav/xsim/webtalk_26844.backup.log new file mode 100644 index 0000000..1d16bb4 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk_26844.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:03:43 2022 +# Process ID: 26844 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 04:03:43 2022... diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk_32252.backup.jou b/LAB10.sim/TB_Processor/behav/xsim/webtalk_32252.backup.jou new file mode 100644 index 0000000..74620fd --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk_32252.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed Jul 27 13:25:13 2022 +# Process ID: 32252 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Processor/behav/xsim/webtalk_32252.backup.log b/LAB10.sim/TB_Processor/behav/xsim/webtalk_32252.backup.log new file mode 100644 index 0000000..7e2faa0 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/webtalk_32252.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed Jul 27 13:25:13 2022 +# Process ID: 32252 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Wed Jul 27 13:25:13 2022... diff --git a/LAB10.sim/TB_Processor/behav/xsim/xelab.pb b/LAB10.sim/TB_Processor/behav/xsim/xelab.pb new file mode 100644 index 0000000..fd854a9 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/Compile_Options.txt b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/Compile_Options.txt new file mode 100644 index 0000000..88a5bcb --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Processor_behav" "xil_defaultlib.TB_Processor" -log "elaborate.log" diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..0888f9d Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_1.c b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_1.c new file mode 100644 index 0000000..70b70d4 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_1.c @@ -0,0 +1,156 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_230(char*, char *); +extern void execute_231(char*, char *); +extern void execute_228(char*, char *); +extern void execute_229(char*, char *); +extern void execute_15(char*, char *); +extern void execute_51(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_36(char*, char *); +extern void execute_53(char*, char *); +extern void execute_55(char*, char *); +extern void execute_91(char*, char *); +extern void execute_76(char*, char *); +extern void execute_129(char*, char *); +extern void execute_130(char*, char *); +extern void execute_131(char*, char *); +extern void execute_132(char*, char *); +extern void execute_169(char*, char *); +extern void execute_170(char*, char *); +extern void execute_140(char*, char *); +extern void execute_141(char*, char *); +extern void execute_135(char*, char *); +extern void execute_136(char*, char *); +extern void execute_177(char*, char *); +extern void execute_178(char*, char *); +extern void execute_179(char*, char *); +extern void execute_180(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void execute_184(char*, char *); +extern void execute_185(char*, char *); +extern void execute_186(char*, char *); +extern void execute_187(char*, char *); +extern void execute_192(char*, char *); +extern void execute_223(char*, char *); +extern void execute_227(char*, char *); +extern void execute_226(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_8(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_27(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_32(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_33(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_72(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_104(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_105(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_106(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_107(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[59] = {(funcp)execute_230, (funcp)execute_231, (funcp)execute_228, (funcp)execute_229, (funcp)execute_15, (funcp)execute_51, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_36, (funcp)execute_53, (funcp)execute_55, (funcp)execute_91, (funcp)execute_76, (funcp)execute_129, (funcp)execute_130, (funcp)execute_131, (funcp)execute_132, (funcp)execute_169, (funcp)execute_170, (funcp)execute_140, (funcp)execute_141, (funcp)execute_135, (funcp)execute_136, (funcp)execute_177, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_192, (funcp)execute_223, (funcp)execute_227, (funcp)execute_226, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_8, (funcp)transaction_27, (funcp)transaction_32, (funcp)transaction_33, (funcp)transaction_60, (funcp)transaction_72, (funcp)transaction_104, (funcp)transaction_105, (funcp)transaction_106, (funcp)transaction_107}; +const int NumRelocateId= 59; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Processor_behav/xsim.reloc", (void **)funcTab, 59); + iki_vhdl_file_variable_register(dp + 32784); + iki_vhdl_file_variable_register(dp + 32840); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Processor_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Processor_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Processor_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Processor_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Processor_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..98338da Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..4cc7ec5 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658917024 +1658908512 +84 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..2529ede --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Jul 28 12:00:19 2022" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "69c21d34-fbe6-435b-acbb-7c2162b3576f" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "f330702f431647419194c50ab3747a93" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "83" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2592 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "2" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6916_KB" -context "xsim\\usage" +webtalk_transmit -clientid 4165748720 -regid "" -xml C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.dbg b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.dbg new file mode 100644 index 0000000..789cee1 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.mem b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.mem new file mode 100644 index 0000000..67cf4fa Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.reloc b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.reloc new file mode 100644 index 0000000..9b4af35 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.rlx b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.rlx new file mode 100644 index 0000000..d06c81a --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 2212753203769638758 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Processor_behav/xsimk.exe\" \"xsim.dir/TB_Processor_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Processor_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.rtti b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.rtti new file mode 100644 index 0000000..f4dfcd5 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.svtype b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.type b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.type new file mode 100644 index 0000000..2e26693 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.type differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.xdbg b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.xdbg new file mode 100644 index 0000000..6aaaa04 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimSettings.ini b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimcrash.log b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimk.exe b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimk.exe new file mode 100644 index 0000000..6fb0b52 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimkernel.log b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimkernel.log new file mode 100644 index 0000000..3ed309b --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/TB_Processor_behav/xsimkernel.log @@ -0,0 +1,4 @@ +Running: xsim.dir/TB_Processor_behav/xsimk.exe -simmode gui -wdb TB_Processor_behav.wdb -simrunnum 0 -socket 59475 +Design successfully loaded +Design Loading Memory Usage: 6416 KB (Peak: 6416 KB) +Design Loading CPU Usage: 15 ms diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/adderbit_3.vdb b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/adderbit_3.vdb new file mode 100644 index 0000000..d034069 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/adderbit_3.vdb differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb new file mode 100644 index 0000000..2144f39 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb new file mode 100644 index 0000000..cf460c0 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb differ diff --git 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file mode 100644 index 0000000..a3170ed Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/slow_clk.vdb differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/tb_processor.vdb b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/tb_processor.vdb new file mode 100644 index 0000000..f848f52 Binary files /dev/null and b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/tb_processor.vdb differ diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..4991e73 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,24 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd,1658862379,vhdl,,,,tb_processor,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd,1658864626,vhdl,,,,decoder_2_to_4,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd,1658864616,vhdl,,,,decoder_3_to_8,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd,1658769782,vhdl,,,,fa,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd,1658769782,vhdl,,,,ha,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd,1658864778,vhdl,,,,instruction_decoder,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd,1656342906,vhdl,,,,lut_16_7,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd,1658864708,vhdl,,,,mux_8way_4bit,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd,1658918012,vhdl,,,,program_rom,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd,1658864647,vhdl,,,,reg,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd,1658864596,vhdl,,,,register_bank,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd,1658932569,vhdl,,,,slow_clk,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd,1658865266,vhdl,,,,addsubunitbit_4,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd,1658864815,vhdl,,,,adderbit_3,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd,1658864663,vhdl,,,,mux_2way_3bit,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd,1658864677,vhdl,,,,mux_2way_4bit,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Processor.vhd,1658866578,vhdl,,,,processor,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd,1658788316,vhdl,,,,program_counter,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd,1658958997,vhdl,,,,r7_7_seg,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd,1658864738,vhdl,,,,quad_tri_state_buffer,,,,,,,, diff --git a/LAB10.sim/TB_Processor/behav/xsim/xsim.ini b/LAB10.sim/TB_Processor/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Processor/behav/xsim/xvhdl.log b/LAB10.sim/TB_Processor/behav/xsim/xvhdl.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Processor/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Processor/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/LAB10.sim/TB_Processor/behav/xsim/xvhdl.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM.tcl b/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM_behav.wdb b/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM_behav.wdb new file mode 100644 index 0000000..9c5a917 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM_behav.wdb differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM_vhdl.prj b/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM_vhdl.prj new file mode 100644 index 0000000..33183f5 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/TB_Program_ROM_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/new/Program_ROM.vhd" \ +"../../../../LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/compile.bat b/LAB10.sim/TB_Program_ROM/behav/xsim/compile.bat new file mode 100644 index 0000000..4a7d9b7 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 28 04:04:34 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_Program_ROM_vhdl.prj" +call xvhdl --incr --relax -prj TB_Program_ROM_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/compile.log b/LAB10.sim/TB_Program_ROM/behav/xsim/compile.log new file mode 100644 index 0000000..7e8befe --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/compile.log @@ -0,0 +1,4 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_ROM +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Program_ROM diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/elaborate.bat b/LAB10.sim/TB_Program_ROM/behav/xsim/elaborate.bat new file mode 100644 index 0000000..d78d526 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 28 04:04:38 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Program_ROM_behav xil_defaultlib.TB_Program_ROM -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/elaborate.log b/LAB10.sim/TB_Program_ROM/behav/xsim/elaborate.log new file mode 100644 index 0000000..e0b0bec --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/elaborate.log @@ -0,0 +1,16 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Program_ROM_behav xil_defaultlib.TB_Program_ROM -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_program_rom +Built simulation snapshot TB_Program_ROM_behav diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/simulate.bat b/LAB10.sim/TB_Program_ROM/behav/xsim/simulate.bat new file mode 100644 index 0000000..a3cd460 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 28 04:04:45 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_Program_ROM_behav -key {Behavioral:TB_Program_ROM:Functional:TB_Program_ROM} -tclbatch TB_Program_ROM.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/simulate.log b/LAB10.sim/TB_Program_ROM/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.jou b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.jou new file mode 100644 index 0000000..e2e9a49 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:27 2022 +# Process ID: 28060 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log new file mode 100644 index 0000000..4a78996 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 11:59:27 2022 +# Process ID: 28060 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 11:59:27 2022... diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_28040.backup.jou b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_28040.backup.jou new file mode 100644 index 0000000..9d7fdfb --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_28040.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:07:06 2022 +# Process ID: 28040 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_28040.backup.log b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_28040.backup.log new file mode 100644 index 0000000..325eb73 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_28040.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 04:07:06 2022 +# Process ID: 28040 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 04:07:06 2022... diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_29144.backup.jou b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_29144.backup.jou new file mode 100644 index 0000000..5e8de47 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_29144.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 04:04:45 2022 +# Process ID: 29144 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_29144.backup.log b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_29144.backup.log new file mode 100644 index 0000000..609d6ab --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_29144.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 04:04:45 2022 +# Process ID: 29144 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 04:04:45 2022... diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_30252.backup.jou b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_30252.backup.jou new file mode 100644 index 0000000..ac10e3c --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_30252.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 01:42:33 2022 +# Process ID: 30252 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_30252.backup.log b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_30252.backup.log new file mode 100644 index 0000000..faae9b3 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk_30252.backup.log @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 01:42:33 2022 +# Process ID: 30252 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 01:42:33 2022... diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xelab.pb b/LAB10.sim/TB_Program_ROM/behav/xsim/xelab.pb new file mode 100644 index 0000000..64b70a4 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/Compile_Options.txt b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/Compile_Options.txt new file mode 100644 index 0000000..a1576b6 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Program_ROM_behav" "xil_defaultlib.TB_Program_ROM" -log "elaborate.log" diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..f603279 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_1.c b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_1.c new file mode 100644 index 0000000..b3ef0ec --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_1.c @@ -0,0 +1,100 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_12(char*, char *); +extern void execute_11(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[3] = {(funcp)execute_12, (funcp)execute_11, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 3; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Program_ROM_behav/xsim.reloc", (void **)funcTab, 3); + iki_vhdl_file_variable_register(dp + 2224); + iki_vhdl_file_variable_register(dp + 2280); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Program_ROM_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Program_ROM_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Program_ROM_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Program_ROM_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Program_ROM_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..219f78b Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..c58fa81 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658961282 +1658989766 +5 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.dbg b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.dbg new file mode 100644 index 0000000..bef6f21 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.mem b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.mem new file mode 100644 index 0000000..0fb8b21 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.reloc b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.reloc new file mode 100644 index 0000000..1807249 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.rlx b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.rlx new file mode 100644 index 0000000..6303ada --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 1826503117783826606 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Program_ROM_behav xil_defaultlib.TB_Program_ROM" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Program_ROM_behav/xsimk.exe\" \"xsim.dir/TB_Program_ROM_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Program_ROM_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.rtti b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.rtti new file mode 100644 index 0000000..43ab3e6 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.svtype b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.type b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.type new file mode 100644 index 0000000..e7b725f Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.type differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.xdbg b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.xdbg new file mode 100644 index 0000000..124e043 Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimSettings.ini b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimcrash.log b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimk.exe b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimk.exe new file mode 100644 index 0000000..52bd0bd Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimkernel.log b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimkernel.log new file mode 100644 index 0000000..73a4ebd --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/TB_Program_ROM_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_Program_ROM_behav/xsimk.exe -simmode gui -wdb TB_Program_ROM_behav.wdb -simrunnum 0 -socket 63047 +Design successfully loaded +Design Loading Memory Usage: 6452 KB (Peak: 6452 KB) +Design Loading CPU Usage: 46 ms +Simulation completed +Simulation Memory Usage: 7064 KB (Peak: 7064 KB) +Simulation CPU Usage: 46 ms diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/program_rom.vdb b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/program_rom.vdb new file mode 100644 index 0000000..22a092d Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/program_rom.vdb differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/tb_program_rom.vdb b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/tb_program_rom.vdb new file mode 100644 index 0000000..8c34a7b Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/tb_program_rom.vdb differ diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..ca7dbb4 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,6 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd,1658779890,vhdl,,,,tb_program_rom,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd,1658863552,vhdl,,,,program_rom,,,,,,,, diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.ini b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xvhdl.log b/LAB10.sim/TB_Program_ROM/behav/xsim/xvhdl.log new file mode 100644 index 0000000..7e8befe --- /dev/null +++ b/LAB10.sim/TB_Program_ROM/behav/xsim/xvhdl.log @@ -0,0 +1,4 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_ROM +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Program_ROM diff --git a/LAB10.sim/TB_Program_ROM/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Program_ROM/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..e4d654c Binary files /dev/null and b/LAB10.sim/TB_Program_ROM/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim.tcl b/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim_behav.wdb b/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim_behav.wdb new file mode 100644 index 0000000..4855416 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim_behav.wdb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim_vhdl.prj b/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim_vhdl.prj new file mode 100644 index 0000000..b8c43e5 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/Reg_Bank_Sim_vhdl.prj @@ -0,0 +1,10 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd" \ +"../../../../LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd" \ +"../../../../LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd" \ +"../../../../LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd" \ +"../../../../LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/compile.bat b/LAB10.sim/TB_Register_Bank/behav/xsim/compile.bat new file mode 100644 index 0000000..77db953 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 28 03:37:57 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj Reg_Bank_Sim_vhdl.prj" +call xvhdl --incr --relax -prj Reg_Bank_Sim_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/compile.log b/LAB10.sim/TB_Register_Bank/behav/xsim/compile.log new file mode 100644 index 0000000..ec8837c --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/compile.log @@ -0,0 +1,10 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg_Bank +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg_Bank_Sim diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/elaborate.bat b/LAB10.sim/TB_Register_Bank/behav/xsim/elaborate.bat new file mode 100644 index 0000000..a758875 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 28 03:38:00 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Reg_Bank_Sim_behav xil_defaultlib.Reg_Bank_Sim -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/elaborate.log b/LAB10.sim/TB_Register_Bank/behav/xsim/elaborate.log new file mode 100644 index 0000000..629ee76 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/elaborate.log @@ -0,0 +1,18 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Reg_Bank_Sim_behav xil_defaultlib.Reg_Bank_Sim -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg_Bank [reg_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.reg_bank_sim +Built simulation snapshot Reg_Bank_Sim_behav diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/simulate.bat b/LAB10.sim/TB_Register_Bank/behav/xsim/simulate.bat new file mode 100644 index 0000000..3f58ac8 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 28 03:38:06 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim Reg_Bank_Sim_behav -key {Behavioral:TB_Register_Bank:Functional:Reg_Bank_Sim} -tclbatch Reg_Bank_Sim.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/simulate.log b/LAB10.sim/TB_Register_Bank/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.jou b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.jou new file mode 100644 index 0000000..ed1ddc1 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 12:00:21 2022 +# Process ID: 17384 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log new file mode 100644 index 0000000..1df20c8 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 12:00:21 2022 +# Process ID: 17384 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 12:00:21 2022... diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_13572.backup.jou b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_13572.backup.jou new file mode 100644 index 0000000..0e13b99 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_13572.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:38:06 2022 +# Process ID: 13572 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_13572.backup.log b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_13572.backup.log new file mode 100644 index 0000000..959cca8 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_13572.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 28 03:38:06 2022 +# Process ID: 13572 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/mailt/Documents/A -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 28 03:38:06 2022... diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_52204.backup.jou b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_52204.backup.jou new file mode 100644 index 0000000..3797fc4 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_52204.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 21:32:00 2022 +# Process ID: 52204 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_52204.backup.log b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_52204.backup.log new file mode 100644 index 0000000..245ec43 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_52204.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 21:32:00 2022 +# Process ID: 52204 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 21:32:02 2022... diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_54640.backup.jou b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_54640.backup.jou new file mode 100644 index 0000000..7b21a14 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_54640.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 21:35:50 2022 +# Process ID: 54640 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_54640.backup.log b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_54640.backup.log new file mode 100644 index 0000000..3e5b1b5 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk_54640.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 21:35:50 2022 +# Process ID: 54640 +# Current directory: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/webtalk.log +# Journal file: C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/dilsh/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Mon Jul 25 21:35:52 2022... diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xelab.pb b/LAB10.sim/TB_Register_Bank/behav/xsim/xelab.pb new file mode 100644 index 0000000..d59fb7c Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/Compile_Options.txt b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/Compile_Options.txt new file mode 100644 index 0000000..5ff9867 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "Reg_Bank_Sim_behav" "xil_defaultlib.Reg_Bank_Sim" -log "elaborate.log" diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/TempBreakPointFile.txt b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_0.win64.obj b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..fd7abb7 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_1.c b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_1.c new file mode 100644 index 0000000..3fa0ada --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_1.c @@ -0,0 +1,113 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_45(char*, char *); +extern void execute_46(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_30(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[16] = {(funcp)execute_45, (funcp)execute_46, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_30, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 16; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/Reg_Bank_Sim_behav/xsim.reloc", (void **)funcTab, 16); + iki_vhdl_file_variable_register(dp + 6392); + iki_vhdl_file_variable_register(dp + 6448); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/Reg_Bank_Sim_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/Reg_Bank_Sim_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/Reg_Bank_Sim_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/Reg_Bank_Sim_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/Reg_Bank_Sim_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_1.win64.obj b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..a574b69 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..a936e19 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1658959684 +1658989820 +21 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/usage_statistics_ext_xsim.html b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..615813f --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedMon Jul 25 21:35:49 2022os_platformWIN64
product_versionXSIM v2018.2 (64-bit)project_idf330702f431647419194c50ab3747a93
project_iteration2random_id42d18b2525b056b7b3ef00b7402b363d
registration_id42d18b2525b056b7b3ef00b7402b363droute_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-10210U CPU @ 1.60GHzcpu_speed2112 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=2runtime=1 ussimulation_memory=6944_KBsimulation_time=0.03_sec
trace_waveform=true
+

+ + diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/usage_statistics_ext_xsim.xml b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..4d88e63 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.dbg b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.dbg new file mode 100644 index 0000000..ea25a92 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.dbg differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.mem b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.mem new file mode 100644 index 0000000..000423f Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.mem differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.reloc b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.reloc new file mode 100644 index 0000000..943a9ce Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.reloc differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.rlx b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.rlx new file mode 100644 index 0000000..5ac6f2b --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 875034090944236318 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Reg_Bank_Sim_behav xil_defaultlib.Reg_Bank_Sim" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx1\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/Reg_Bank_Sim_behav/xsimk.exe\" \"xsim.dir/Reg_Bank_Sim_behav/obj/xsim_0.win64.obj\" \"xsim.dir/Reg_Bank_Sim_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx1\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.rtti b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.rtti new file mode 100644 index 0000000..44825a3 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.rtti differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.svtype b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.svtype differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.type b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.type new file mode 100644 index 0000000..06ad624 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.type differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.xdbg b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.xdbg new file mode 100644 index 0000000..d626ce0 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsim.xdbg differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimSettings.ini b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimSettings.ini new file mode 100644 index 0000000..edab408 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=178 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=178 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimcrash.log b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimk.exe b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimk.exe new file mode 100644 index 0000000..2ff3e01 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimk.exe differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimkernel.log b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimkernel.log new file mode 100644 index 0000000..0e1360e --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/Reg_Bank_Sim_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/Reg_Bank_Sim_behav/xsimk.exe -simmode gui -wdb Reg_Bank_Sim_behav.wdb -simrunnum 0 -socket 62647 +Design successfully loaded +Design Loading Memory Usage: 6480 KB (Peak: 6480 KB) +Design Loading CPU Usage: 77 ms +Simulation completed +Simulation Memory Usage: 7084 KB (Peak: 7084 KB) +Simulation CPU Usage: 108 ms diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb new file mode 100644 index 0000000..fa9e81d Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/decoder_2_to_4.vdb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb new file mode 100644 index 0000000..a3d034e Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/decoder_3_to_8.vdb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg.vdb b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg.vdb new file mode 100644 index 0000000..59b3921 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg.vdb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg_bank.vdb b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg_bank.vdb new file mode 100644 index 0000000..0f83166 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg_bank.vdb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg_bank_sim.vdb b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg_bank_sim.vdb new file mode 100644 index 0000000..00da3a2 Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/reg_bank_sim.vdb differ diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..1d73792 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,9 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd,1658787810,vhdl,,,,reg_bank_sim,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd,1658769784,vhdl,,,,decoder_2_to_4,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd,1658769784,vhdl,,,,decoder_3_to_8,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd,1658769784,vhdl,,,,reg,,,,,,,, +C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd,1658769784,vhdl,,,,reg_bank,,,,,,,, diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.ini b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xvhdl.log b/LAB10.sim/TB_Register_Bank/behav/xsim/xvhdl.log new file mode 100644 index 0000000..ec8837c --- /dev/null +++ b/LAB10.sim/TB_Register_Bank/behav/xsim/xvhdl.log @@ -0,0 +1,10 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg_Bank +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg_Bank_Sim diff --git a/LAB10.sim/TB_Register_Bank/behav/xsim/xvhdl.pb b/LAB10.sim/TB_Register_Bank/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..5a414fb Binary files /dev/null and b/LAB10.sim/TB_Register_Bank/behav/xsim/xvhdl.pb differ diff --git a/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4.tcl b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_behav.wdb b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_behav.wdb new file mode 100644 index 0000000..0aa8866 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_behav.wdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj new file mode 100644 index 0000000..ccf7adc --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/imports/new/FA.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/HA.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/RCA.vhd" \ +"../../../../LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/sim_1/behav/xsim/compile.bat b/LAB10.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..53d5280 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 07 19:54:00 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj" +call xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/sim_1/behav/xsim/compile.log b/LAB10.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..9399785 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 diff --git a/LAB10.sim/sim_1/behav/xsim/elaborate.bat b/LAB10.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..383b3d4 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 07 19:54:01 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/sim_1/behav/xsim/elaborate.log b/LAB10.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..a7625cf --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,17 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_addsubunitbit_4 +Built simulation snapshot TB_AddSubUnitBit_4_behav diff --git a/LAB10.sim/sim_1/behav/xsim/simulate.bat b/LAB10.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..982f740 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 07 19:54:03 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_AddSubUnitBit_4_behav -key {Behavioral:sim_1:Functional:TB_AddSubUnitBit_4} -tclbatch TB_AddSubUnitBit_4.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/sim_1/behav/xsim/simulate.log b/LAB10.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk.jou b/LAB10.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..3b745f8 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:53:59 2022 +# Process ID: 17808 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk.log b/LAB10.sim/sim_1/behav/xsim/webtalk.log new file mode 100644 index 0000000..4091392 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:53:59 2022 +# Process ID: 17808 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "E:/Mora/Digital" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 7 19:53:59 2022... diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.jou b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.jou new file mode 100644 index 0000000..6467dfc --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:44:41 2022 +# Process ID: 15304 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.log b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.log new file mode 100644 index 0000000..7d51715 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:44:41 2022 +# Process ID: 15304 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "E:/Mora/Digital" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 7 19:44:41 2022... diff --git a/LAB10.sim/sim_1/behav/xsim/xelab.pb b/LAB10.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..3a141c3 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt new file mode 100644 index 0000000..44528b9 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_AddSubUnitBit_4_behav" "xil_defaultlib.TB_AddSubUnitBit_4" -log "elaborate.log" diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..e7dbdf5 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c new file mode 100644 index 0000000..39b938a --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_53(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_51(char*, char *); +extern void execute_52(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_53, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_51, (funcp)execute_52, (funcp)execute_22, (funcp)execute_23, (funcp)execute_17, (funcp)execute_18, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc", (void **)funcTab, 12); + iki_vhdl_file_variable_register(dp + 8152); + iki_vhdl_file_variable_register(dp + 8208); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..819ad10 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..395ad4b --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1657203280 +1657203838 +5 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..68a66eb --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Jul 7 19:56:58 2022" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "0d1c7977dd6d5955bcf230b289e9e973" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "f330702f431647419194c50ab3747a93" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 9 5900HS with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3294 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "33.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6292_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1821698081 -regid "" -xml E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.xml -html E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.html -wdm E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg new file mode 100644 index 0000000..a950127 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem new file mode 100644 index 0000000..fdde7c8 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc new file mode 100644 index 0000000..7e35504 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx new file mode 100644 index 0000000..86d237b --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 7571415711912686436 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe\" \"xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti new file mode 100644 index 0000000..cc37966 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type new file mode 100644 index 0000000..d1ab5b3 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg new file mode 100644 index 0000000..861748e Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini new file mode 100644 index 0000000..8d7c961 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=138 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=115 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=115 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimcrash.log b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe new file mode 100644 index 0000000..3455bdb Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log new file mode 100644 index 0000000..a2cfa6c --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe -simmode gui -wdb TB_AddSubUnitBit_4_behav.wdb -simrunnum 0 -socket 1999 +Design successfully loaded +Design Loading Memory Usage: 5808 KB (Peak: 5808 KB) +Design Loading CPU Usage: 0 ms +Simulation completed +Simulation Memory Usage: 6292 KB (Peak: 6292 KB) +Simulation CPU Usage: 0 ms diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb new file mode 100644 index 0000000..3617ce0 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb new file mode 100644 index 0000000..a47aa1c Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb new file mode 100644 index 0000000..1c57c6b Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb new file mode 100644 index 0000000..ed61afe Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..89d609f --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,8 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd,1657203834,vhdl,,,,tb_addsubunitbit_4,,,,,,,, +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd,1653841899,vhdl,,,,fa,,,,,,,, +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd,1653837756,vhdl,,,,ha,,,,,,,, +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/RCA.vhd,1657200684,vhdl,,,,addsubunitbit_4,,,,,,,, diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.ini b/LAB10.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/sim_1/behav/xsim/xvhdl.log b/LAB10.sim/sim_1/behav/xsim/xvhdl.log new file mode 100644 index 0000000..9399785 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 diff --git a/LAB10.sim/sim_1/behav/xsim/xvhdl.pb b/LAB10.sim/sim_1/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..849bc25 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.sim/TB_AddSubUnitBit_4.vhd b/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.sim/TB_AddSubUnitBit_4.vhd new file mode 100644 index 0000000..708ffb3 --- /dev/null +++ b/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.sim/TB_AddSubUnitBit_4.vhd @@ -0,0 +1,82 @@ +---------------------------------------------------------------------------------- +-- Company: University of Moratuwa +-- Engineer: Ginushmal Vikumkith - 200734G +-- +-- Create Date: 07/07/2022 07:13:45 PM +-- Design Name: +-- Module Name: TB_AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_AddSubUnitBit_4 is +-- Port ( ); +end TB_AddSubUnitBit_4; + +architecture Behavioral of TB_AddSubUnitBit_4 is +component AddSubUnitBit_4 + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; +-- If substraction, 1 +-- If addition 0 + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end component; + signal A,B,S : STD_LOGIC_VECTOR (3 downto 0); + signal Overflow,Zero,AddSub_Select : STD_LOGIC:='0'; +begin +UUT: AddSubUnitBit_4 + PORT MAP( + A=>A, + B=>B, + S=>S, + Overflow=>Overflow, + Zero=>Zero, + AddSub_Select=>AddSub_Select + ); +process begin +-- This program was developed by Ginushmal Vikumjith - 200734G - +-- My Index number in binary is 11 0001 0000 0001 1110 +-- Let's test 0011 - 0001= 0010 +-- 0001 + 1110 = 1111 + +--Testing 0011 - 0001= 0010 + A<="0011"; + B<="0001"; + -- because we have to subtract AddSub_Select=1 + AddSub_Select<='1'; + WAIT FOR 100ns; + +-- Testing 0001 + 1110 = 1111 + A<="0110"; + B<="1001"; + -- because we have to add AddSub_Select=0 + AddSub_Select<='0'; + WAIT; + +end process; +end Behavioral; \ No newline at end of file diff --git a/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd b/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd new file mode 100644 index 0000000..879837c --- /dev/null +++ b/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd @@ -0,0 +1,72 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/29/2022 09:50:35 PM +-- Design Name: +-- Module Name: FA - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FA is + Port ( A : in STD_LOGIC; + B : in STD_LOGIC; + C_in : in STD_LOGIC; + S : out STD_LOGIC; + C_out : out STD_LOGIC); +end FA; + +architecture Behavioral of FA is +component HA + + PORT( + A : in STD_LOGIC; + B : in STD_LOGIC; + S : out STD_LOGIC; + C : out STD_LOGIC + ); + +end component; +signal HA0_S,HA0_C,HA1_S,HA1_C: STD_LOGIC; +begin +HA_0 : HA + PORT MAP( + A=>A, + B=>B, + C=>HA0_C, + S=>HA0_S + ); + +HA_1 : HA + PORT MAP( + A=>HA0_S, + B=>C_in, + C=>HA1_C, + S=>HA1_S + ); + C_out<= HA0_C OR HA1_C; + S <= HA1_S; +end Behavioral; diff --git a/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd b/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd new file mode 100644 index 0000000..6560875 --- /dev/null +++ b/LAB10.srcs/TB_AddSubUnitBit_4/imports/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/29/2022 08:49:50 PM +-- Design Name: +-- Module Name: HA - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity HA is + Port ( A : in STD_LOGIC; + B : in STD_LOGIC; + S : out STD_LOGIC; + C : out STD_LOGIC); +end HA; + +architecture Behavioral of HA is + +begin + S <= A XOR B; + C <= A AND B; + +end Behavioral; diff --git a/LAB10.srcs/TB_AddSubUnitBit_4/imports/sim_1/AddSubUnitBit_4.vhd b/LAB10.srcs/TB_AddSubUnitBit_4/imports/sim_1/AddSubUnitBit_4.vhd new file mode 100644 index 0000000..fb89bb8 --- /dev/null +++ b/LAB10.srcs/TB_AddSubUnitBit_4/imports/sim_1/AddSubUnitBit_4.vhd @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 09:49:41 PM +-- Design Name: +-- Module Name: AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AddSubUnitBit_4 is + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end AddSubUnitBit_4; + +architecture Behavioral of AddSubUnitBit_4 is +component FA + PORT(A : in STD_LOGIC; + B : in STD_LOGIC; + C_in : in STD_LOGIC; + S : out STD_LOGIC; + C_out : out STD_LOGIC); +end component; + +SIGNAL FA0_S, FA0_C,FA1_S, FA1_C,FA2_S, FA2_C:STD_LOGIC; +SIGNAL Bi : STD_LOGIC_VECTOR (3 downto 0); +SIGNAL Si : STD_LOGIC_VECTOR (3 downto 0); + +begin + +Bi(0)<=(B(0) XOR AddSub_Select); +Bi(1)<=(B(1) XOR AddSub_Select); +Bi(2)<=(B(2) XOR AddSub_Select); +Bi(3)<=(B(3) XOR AddSub_Select); + +FA_0 : FA + PORT MAP ( + A=>A(0), + B => Bi(0), + C_in => AddSub_Select, + S => Si(0), + C_out=> FA0_C + ); + +FA_1 : FA + PORT MAP ( + A=>A(1), + B => Bi(1), + C_in => FA0_C, + S => Si(1), + C_out=> FA1_C + ); + +FA_2 : FA + PORT MAP ( + A=>A(2), + B => Bi(2), + C_in => FA1_C, + S => Si(2), + C_out=> FA2_C + ); + +FA_3 : FA + PORT MAP ( + A=>A(3), + B => Bi(3), + C_in => FA2_C, + S => Si(3), + C_out=> Overflow + ); +S<=Si; +Zero<= NOT(Si(0) OR Si(1) OR Si(2) OR Si(3)); +end Behavioral; diff --git a/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd b/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd new file mode 100644 index 0000000..6fb603f --- /dev/null +++ b/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd @@ -0,0 +1,70 @@ +---------------------------------------------------------------------------------- +-- Company: University of Moratuwa +-- Engineer: Ginushmal Vikumkith - 200734G +-- +-- Create Date: 07/07/2022 07:13:45 PM +-- Design Name: +-- Module Name: TB_AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_AdderBit_3 is +-- Port ( ); +end TB_AdderBit_3; + +architecture Behavioral of TB_AdderBit_3 is +component AdderBit_3 + Port ( PreviousAddressPC : in STD_LOGIC_VECTOR (2 downto 0); + NextAddressPC : out STD_LOGIC_VECTOR (2 downto 0); + C_OUT : out STD_LOGIC); + +end component; + signal PreviousAddressPC,NextAddressPC : STD_LOGIC_VECTOR (2 downto 0); +begin +UUT: AdderBit_3 + PORT MAP( + PreviousAddressPC=>PreviousAddressPC, + NextAddressPC=>NextAddressPC + ); +process begin +-- This program was developed by Ginushmal Vikumjith - 200734G - +-- My Index number in binary is 11 0001 0000 0001 1110 +-- Let's test 0011 - 0001= 0010 +-- 0001 + 1110 = 1111 + +--Testing 0011 - 0001= 0010 + PreviousAddressPC<="011"; + WAIT FOR 100ns; + + PreviousAddressPC<="111"; + WAIT FOR 100ns; + +-- Testing 0001 + 1110 = 1111 + PreviousAddressPC<="110"; + WAIT; + +end process; +end Behavioral; \ No newline at end of file diff --git a/LAB10.srcs/TB_Decoder_3_to_8/new/TB_Decoder_3_to_8.vhd b/LAB10.srcs/TB_Decoder_3_to_8/new/TB_Decoder_3_to_8.vhd new file mode 100644 index 0000000..22f15b6 --- /dev/null +++ b/LAB10.srcs/TB_Decoder_3_to_8/new/TB_Decoder_3_to_8.vhd @@ -0,0 +1,95 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/14/2022 06:58:35 PM +-- Design Name: +-- Module Name: TB_Decoder_3_to_8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Decoder_3_to_8 is +-- Port ( ); +end TB_Decoder_3_to_8; + +architecture Behavioral of TB_Decoder_3_to_8 is +component Decoder_3_to_8 + PORT( + I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0)); +end component; + + signal I : STD_LOGIC_VECTOR (2 downto 0); + signal EN : STD_LOGIC; + signal Y : STD_LOGIC_VECTOR (7 downto 0); + +begin +UUT: Decoder_3_to_8 + PORT MAP( + I=>I, + EN=>EN, + Y=>Y + ); + process + begin + EN<='1'; + --my index number is 200390V + --equivalent bianry number is 00 110 000 111 011 000 110 + -- setting to 110 + I<="110"; + wait for 100ns; + + --setting to 000 + I<="000"; + wait for 100ns; + + --setting to 011 + I<="011"; + wait for 100ns; + + --setting to 111 + I<="111"; + wait for 100ns; + + --other combinations are repeated + + I<="001"; + wait for 100ns; + I<="010"; + wait for 100ns; + I<="101"; + wait for 100ns; + I<="110"; + wait for 100ns; + + +-- + +-- wait; + end process; + +end Behavioral; diff --git a/LAB10.srcs/TB_Mux_2_to_1_3bit/imports/new/Mux_2_to_1_3bit.vhd b/LAB10.srcs/TB_Mux_2_to_1_3bit/imports/new/Mux_2_to_1_3bit.vhd new file mode 100644 index 0000000..e494a38 --- /dev/null +++ b/LAB10.srcs/TB_Mux_2_to_1_3bit/imports/new/Mux_2_to_1_3bit.vhd @@ -0,0 +1,48 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Pabasara Jayasekara +-- +-- Create Date: 07/25/2022 08:32:21 PM +-- Design Name: +-- Module Name: Mux_2_to_1_3bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Mux_2way_3bit is + Port ( JumpFlag : in STD_LOGIC; + EN : in STD_LOGIC; + AddressToJump : in STD_LOGIC_VECTOR (2 downto 0); + Adder_3bit_out : in STD_LOGIC_VECTOR (2 downto 0); + ToNextProgramCounter : out STD_LOGIC_VECTOR (2 downto 0)); +end Mux_2way_3bit; + +architecture Behavioral of Mux_2way_3bit is + +begin + +ToNextProgramCounter<=AddressToJump WHEN (JumpFlag='1') ELSE Adder_3bit_out; + +end Behavioral; diff --git a/LAB10.srcs/TB_Mux_2_to_1_3bit/new/TB_Mux_2_to_1_3bit.vhd b/LAB10.srcs/TB_Mux_2_to_1_3bit/new/TB_Mux_2_to_1_3bit.vhd new file mode 100644 index 0000000..8c992eb --- /dev/null +++ b/LAB10.srcs/TB_Mux_2_to_1_3bit/new/TB_Mux_2_to_1_3bit.vhd @@ -0,0 +1,105 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Person: Pabasara Jayasekara +-- +-- Create Date: 07/23/2022 10:40:58 PM +-- Design Name: +-- Module Name: TB_Mux_2_to_1_3bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Mux_2_to_1_3bit is +-- Port ( ); +end TB_Mux_2_to_1_3bit; + +architecture Behavioral of TB_Mux_2_to_1_3bit is + + +component Mux_2way_3bit + + Port ( JumpFlag : in STD_LOGIC; + AddressToJump : in STD_LOGIC_VECTOR (2 downto 0); + Adder_3bit_out : in STD_LOGIC_VECTOR (2 downto 0); + ToNextProgramCounter : out STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC); + +end component; + +signal JumpFlag, EN : STD_LOGIC; +signal AddressToJump : STD_LOGIC_VECTOR (2 downto 0); +signal Adder_3bit_out : STD_LOGIC_VECTOR (2 downto 0); +signal ToNextProgramCounter : STD_LOGIC_VECTOR (2 downto 0); + + +begin + +UUT: Mux_2way_3bit + +-- LoadSelect will select the register from D1 to D8 it's 3 bit signal +Port Map( + JumpFlag=>JumpFlag, + AddressToJump=>AddressToJump, + Adder_3bit_out=>Adder_3bit_out, + EN=>EN, + ToNextProgramCounter=>ToNextProgramCounter); + +-- This was programmed by Pabasara Jayasekara with index number 200251X +-- binary representation is 110000111000111011 +-- 110 000 111 000 111 011 + +process begin + +-- setting 4 digits from my index number for the registers +AddressToJump<="111"; +Adder_3bit_out<="011"; + +EN<='1'; +--111 +JumpFlag<='1'; +wait for 100ns; + +--011 +JumpFlag<='0'; +wait for 100ns; + + +-- setting 4 digits from my index number for the registers +AddressToJump<="000"; +Adder_3bit_out<="110"; + + +--000 +JumpFlag<='1'; +wait for 100ns; + +--110 +JumpFlag<='0'; +wait for 100ns; + +wait; + +end process; +end Behavioral; diff --git a/LAB10.srcs/TB_Mux_2_to_1_4bit/new/TB_Mux_2_to_1_4bit.vhd b/LAB10.srcs/TB_Mux_2_to_1_4bit/new/TB_Mux_2_to_1_4bit.vhd new file mode 100644 index 0000000..0460e1d --- /dev/null +++ b/LAB10.srcs/TB_Mux_2_to_1_4bit/new/TB_Mux_2_to_1_4bit.vhd @@ -0,0 +1,109 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Person: Pabasara Jayasekara +-- +-- Create Date: 07/23/2022 10:40:58 PM +-- Design Name: +-- Module Name: TB_Mux_2_to_1_4bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Mux_2_to_1_4bit is +-- Port ( ); +end TB_Mux_2_to_1_4bit; + +architecture Behavioral of TB_Mux_2_to_1_4bit is + + +component Mux_2way_4bit + + Port ( LoadSelect : in STD_LOGIC; + AddSubUnit4BitOut : in STD_LOGIC_VECTOR (3 downto 0); + ImmediateValue : in STD_LOGIC_VECTOR (3 downto 0); + -- enable signal + EN : in STD_LOGIC; + -- output + valueToRegisters : out STD_LOGIC_VECTOR (3 downto 0)); + +end component; + +signal LoadSelect : STD_LOGIC; +signal AddSubUnit4BitOut : STD_LOGIC_VECTOR (3 downto 0); +signal ImmediateValue : STD_LOGIC_VECTOR (3 downto 0); + --enable signal +signal EN : STD_LOGIC; + -- output +signal valueToRegisters : STD_LOGIC_VECTOR (3 downto 0); + +begin + +UUT: Mux_2way_4bit + +-- LoadSelect will select the register from D1 to D8 it's 3 bit signal +Port Map( + LoadSelect=>LoadSelect, + AddSubUnit4BitOut=>AddSubUnit4BitOut, + ImmediateValue=>ImmediateValue, + EN=>EN, + valueToRegisters=>valueToRegisters); + +-- This was programmed by Pabasara Jayasekara with index number 200251X +-- binary representation is 110000111000111011 +-- 11 0000 1110 0011 1011 + +process begin + +-- setting 4 digits from my index number for the registers +AddSubUnit4BitOut<="1011"; +ImmediateValue<="0011"; + +EN<='1'; +--1011 +LoadSelect<='1'; +wait for 100ns; + +--0011 +LoadSelect<='0'; +wait for 100ns; + + +-- setting 4 digits from my index number for the registers +AddSubUnit4BitOut<="1110"; +ImmediateValue<="0000"; + +EN<='1'; +--1110 +LoadSelect<='1'; +wait for 100ns; + +--0000 +LoadSelect<='0'; +wait for 100ns; + +wait; + +end process; +end Behavioral; diff --git a/LAB10.srcs/TB_Mux_8_to_1/imports/LAB10.sim/TB_Mux_8_to_1.vhd b/LAB10.srcs/TB_Mux_8_to_1/imports/LAB10.sim/TB_Mux_8_to_1.vhd new file mode 100644 index 0000000..e96cc63 --- /dev/null +++ b/LAB10.srcs/TB_Mux_8_to_1/imports/LAB10.sim/TB_Mux_8_to_1.vhd @@ -0,0 +1,177 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Person: Chamaru Amasara +-- +-- Create Date: 07/23/2022 10:40:58 PM +-- Design Name: +-- Module Name: TB_Mux_8_to_1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Mux_8_to_1 is +-- Port ( ); +end TB_Mux_8_to_1; + +architecture Behavioral of TB_Mux_8_to_1 is + + +component Mux_8way_4bit + +-- RegSel will select the register from D1 to D8 it's 3 bit signal + Port ( RegSel : in STD_LOGIC_VECTOR (2 downto 0); + + -- 8 registers + R0 : in STD_LOGIC_VECTOR (3 downto 0); + R1 : in STD_LOGIC_VECTOR (3 downto 0); + R2 : in STD_LOGIC_VECTOR (3 downto 0); + R3 : in STD_LOGIC_VECTOR (3 downto 0); + R4 : in STD_LOGIC_VECTOR (3 downto 0); + R5 : in STD_LOGIC_VECTOR (3 downto 0); + R6 : in STD_LOGIC_VECTOR (3 downto 0); + R7 : in STD_LOGIC_VECTOR (3 downto 0); + + -- enable signal + EN : in STD_LOGIC; + + -- output signal + Output : out std_logic_vector (3 downto 0)); + +end component; + + +signal RegSel : STD_LOGIC_VECTOR (2 downto 0); +signal R0, R1, R2, R3, R4, R5, R6, R7, Output : STD_LOGIC_VECTOR (3 downto 0); +signal EN: STD_LOGIC; + +begin + +UUT: Mux_8way_4bit + +-- RegSel will select the register from D1 to D8 it's 3 bit signal +Port Map( + RegSel=>RegSel, + -- 8 registers + R0=>R0, + R1=>R1, + R2=>R2, + R3=>R3, + R4=>R4, + R5=>R5, + R6=>R6, + R7=>R7, + + -- enable signal + EN=>En, + -- output signal + Output=>Output); +-- This was programmed by Chamaru Amasara with index number 200390V +-- binary representation is 110000111011000110 +-- 11 0000 1110 1100 0110 + +process begin +R0<="0000"; +R1<="0001"; +R2<="0010"; +R3<="0011"; +R4<="0100"; +R5<="0101"; +R6<="0110"; +R7<="0111"; + +--Set Enable=1 +EN<='1'; + +-- This was programmed by Chamaru Amasara with index number 200390V +-- binary representation is 110000111011000110 +-- 110 000 111 011 000 110 + +-- RegSel=111 Selecting Register 7 +RegSel<="000"; +wait for 100ns; + + +-- RegSel=111 Selecting Register 7 +RegSel<="001"; +wait for 100ns; + + +-- RegSel=111 Selecting Register 7 +RegSel<="010"; +wait for 100ns; + + +-- RegSel=111 Selecting Register 7 +RegSel<="011"; +wait for 100ns; + +-- RegSel=111 Selecting Register 7 +RegSel<="100"; +wait for 100ns; + +-- RegSel=111 Selecting Register 7 +RegSel<="101"; +wait for 100ns; + +-- RegSel=111 Selecting Register 7 +RegSel<="110"; +wait for 100ns; + +-- RegSel=111 Selecting Register 7 +RegSel<="111"; +wait for 100ns; + +-- RegSel=111 Selecting Register 7 +RegSel<="000"; +wait for 100ns; + +-- RegSel=111 Selecting Register 7 +RegSel<="000"; +wait for 100ns; + + + + + + +-- RegSel=111 Selecting Register 7 +RegSel<="111"; +wait for 100ns; + +-- RegSel=000 Selecting Register 0 +RegSel<="000"; +wait for 100ns; + +-- RegSel=011 Selecting Register 3 +RegSel<="011"; +wait for 100ns; + +-- RegSel=110 Selecting Register 6 +RegSel<="110"; +wait; + + +end process; +end Behavioral; diff --git a/LAB10.srcs/TB_Mux_8_to_1/imports/new/Decoder_3_to_8.vhd b/LAB10.srcs/TB_Mux_8_to_1/imports/new/Decoder_3_to_8.vhd new file mode 100644 index 0000000..d200860 --- /dev/null +++ b/LAB10.srcs/TB_Mux_8_to_1/imports/new/Decoder_3_to_8.vhd @@ -0,0 +1,76 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/14/2022 06:50:11 PM +-- Design Name: +-- Module Name: Decoder_3_to_8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Decoder_3_to_8 is + Port ( I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0)); +end Decoder_3_to_8; + +architecture Behavioral of Decoder_3_to_8 is +component Decoder_2_to_4 + Port ( I : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + + signal I0,I1 : STD_LOGIC_VECTOR (1 downto 0); + signal Y0,Y1 : STD_LOGIC_VECTOR (3 downto 0); + signal en0,en1, I2 : STD_LOGIC; + + +begin + +Decoder_2_to_4_0: Decoder_2_to_4 + PORT MAP( + I => I0, + EN => en0, + Y => Y0 + ); + +Decoder_2_to_4_1: Decoder_2_to_4 + PORT MAP( + I => I1, + EN => en1, + Y => Y1 + ); + + en0 <= NOT(I(2)) AND EN; + en1 <= I(2) AND EN; + I0 <= I(1 downto 0); + I1 <= I(1 downto 0); + I2 <= I(2); + Y(3 downto 0) <= Y0; + Y(7 downto 4) <= Y1; + +end Behavioral; diff --git a/LAB10.srcs/TB_Mux_8_to_1/imports/new/Mux_8way_4bit.vhd b/LAB10.srcs/TB_Mux_8_to_1/imports/new/Mux_8way_4bit.vhd new file mode 100644 index 0000000..dd85d98 --- /dev/null +++ b/LAB10.srcs/TB_Mux_8_to_1/imports/new/Mux_8way_4bit.vhd @@ -0,0 +1,130 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 03:21:23 PM +-- Design Name: +-- Module Name: Mux_2way_4bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Mux_8way_4bit is + +-- RegSel will select the register from D1 to D8 it's 3 bit signal + Port ( RegSel : in STD_LOGIC_VECTOR (2 downto 0); + + -- 8 registers + R0 : in STD_LOGIC_VECTOR (3 downto 0); + R1 : in STD_LOGIC_VECTOR (3 downto 0); + R2 : in STD_LOGIC_VECTOR (3 downto 0); + R3 : in STD_LOGIC_VECTOR (3 downto 0); + R4 : in STD_LOGIC_VECTOR (3 downto 0); + R5 : in STD_LOGIC_VECTOR (3 downto 0); + R6 : in STD_LOGIC_VECTOR (3 downto 0); + R7 : in STD_LOGIC_VECTOR (3 downto 0); + + -- enable signal + EN : in STD_LOGIC; + + -- output signal + Output : out std_logic_vector (3 downto 0)); +end Mux_8way_4bit; + +architecture Behavioral of Mux_8way_4bit is + +component Decoder_3_to_8 + +port ( I : in STD_LOGIC_VECTOR (2 downto 0); + Y : out STD_LOGIC_VECTOR (7 downto 0); + EN : in STD_LOGIC); +end component; + +component quad_tri_state_buffer +Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + +SIGNAL common_bus : std_logic_vector (3 downto 0); +SIGNAL RegSel_var : std_logic_vector(7 downto 0); +begin + +Decoder_3_to_8_0 : Decoder_3_to_8 + port map ( + I(2 downto 0) => RegSel(2 downto 0), + EN => '1', + Y(7 downto 0) => RegSel_var(7 downto 0)); + +quad_tri_state_buffer_0 : quad_tri_state_buffer +port map( +EN => RegSel_var(0), +A => R0, +Y => common_bus); + +quad_tri_state_buffer_1 : quad_tri_state_buffer +port map( +EN => RegSel_var(1), +A => R1, +Y => common_bus); + +quad_tri_state_buffer_2 : quad_tri_state_buffer +port map( +EN => RegSel_var(2), +A => R2, +Y => common_bus); + +quad_tri_state_buffer_3 : quad_tri_state_buffer +port map( +EN => RegSel_var(3), +A => R3, +Y => common_bus); + +quad_tri_state_buffer_4 : quad_tri_state_buffer +port map( +EN => RegSel_var(4), +A => R4, +Y => common_bus); + +quad_tri_state_buffer_5 : quad_tri_state_buffer +port map( +EN => RegSel_var(5), +A => R5, +Y => common_bus); + +quad_tri_state_buffer_6 : quad_tri_state_buffer +port map( +EN => RegSel_var(6), +A => R6, +Y => common_bus); + +quad_tri_state_buffer_7 : quad_tri_state_buffer +port map( +EN => RegSel_var(7), +A => R7, +Y => common_bus); +Output <= common_bus; + +end Behavioral; \ No newline at end of file diff --git a/LAB10.srcs/TB_Processor/new/TB_Processor.vhd b/LAB10.srcs/TB_Processor/new/TB_Processor.vhd new file mode 100644 index 0000000..53a59cc --- /dev/null +++ b/LAB10.srcs/TB_Processor/new/TB_Processor.vhd @@ -0,0 +1,72 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/26/2022 01:50:17 AM +-- Design Name: +-- Module Name: TB_Processor - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Processor is + +end TB_Processor; + + +architecture Behavioral of TB_Processor is +component Processor + Port ( Clk_In : in STD_LOGIC; + Reset : in STD_LOGIC; + OverFlow : out std_logic; + Zero : out std_logic); +end component; +signal Clk:STD_LOGIC:='0'; +signal Reset, Overflow, Zero: std_logic; +begin +UUT: Processor +PORT MAP( + Clk_In=>Clk, + Reset=>Reset, + OverFlow=>OverFlow, + Zero=>Zero +); +process +begin +wait for 4ns; +Clk<=not(Clk); +end process; + +process +begin +Reset<='1'; +wait for 100ns; + +Reset<='0'; +wait; + +end process; + +end Behavioral; diff --git a/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd b/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd new file mode 100644 index 0000000..bc3fce4 --- /dev/null +++ b/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd @@ -0,0 +1,84 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Person: Dilshan Rakshitha +-- +-- Create Date: 07/23/2022 10:40:58 PM +-- Design Name: +-- Module Name: TB_Program_ROM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Program_ROM is +-- Port ( ); +end TB_Program_ROM; + +architecture Behavioral of TB_Program_ROM is + + +component Program_ROM + + Port ( Memory_Select : in STD_LOGIC_VECTOR (2 downto 0); + Instruction_Bus : out STD_LOGIC_VECTOR (11 downto 0)); + +end component; + +signal Memory_Select : STD_LOGIC_VECTOR (2 downto 0); +signal Instruction_Bus : STD_LOGIC_VECTOR (11 downto 0); + + +begin + +UUT: Program_ROM + + +Port Map( + Memory_Select=>Memory_Select, + Instruction_Bus=>Instruction_Bus); + + +process begin +Memory_Select<="000"; +wait for 100ns; +Memory_Select<="001"; +wait for 100ns; +Memory_Select<="010"; +wait for 100ns; +Memory_Select<="011"; +wait for 100ns; +Memory_Select<="100"; +wait for 100ns; +Memory_Select<="101"; +wait for 100ns; +Memory_Select<="110"; +wait for 100ns; +Memory_Select<="111"; +wait; + + + + +end process; +end Behavioral; \ No newline at end of file diff --git a/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd b/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd new file mode 100644 index 0000000..9f4ef8d --- /dev/null +++ b/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd @@ -0,0 +1,97 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 11:45:10 AM +-- Design Name: +-- Module Name: Reg_Bank_Sim - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg_Bank_Sim is +-- Port ( ); +end Reg_Bank_Sim; + +architecture Behavioral of Reg_Bank_Sim is +component Reg_Bank + Port ( Clk : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Reg_0_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_1_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_2_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_3_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_4_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_5_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_6_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_7_out : out STD_LOGIC_VECTOR (3 downto 0) + ); +end component; +signal Clk : STD_LOGIC:= '0'; +signal Reset : STD_LOGIC; +signal Data_in,Reg_0_out,Reg_1_out,Reg_2_out,Reg_3_out,Reg_4_out,Reg_5_out,Reg_6_out,Reg_7_out : STD_LOGIC_VECTOR (3 downto 0); +signal Reg_Enable : STD_LOGIC_VECTOR (2 downto 0); +begin + UUT :Reg_Bank + PORT MAP( + Clk=>Clk, + Data_in=>Data_in, + Reg_Enable=>Reg_Enable, + Reset=>Reset, + Reg_0_out=>Reg_0_out, + Reg_1_out=>Reg_1_out, + Reg_2_out=>Reg_2_out, + Reg_3_out=>Reg_3_out, + Reg_4_out=>Reg_4_out, + Reg_5_out=>Reg_5_out, + Reg_6_out=>Reg_6_out, + Reg_7_out=>Reg_7_out + ); + + process + begin + wait for 20ns; + Clk <= Not (Clk); + end process; + + process begin + Reset<='1'; + wait for 30ns; + Reset<='0'; + + Reg_Enable<="001"; + Data_in<="0111"; + wait for 100ns; + + Reg_Enable<="010"; + Data_in<="1011"; + wait; + + + end process; + +end Behavioral; diff --git a/LAB10.srcs/TB_Register_Bank/imports/TB_Register_Bank/Reg_Bank_Sim.vhd b/LAB10.srcs/TB_Register_Bank/imports/TB_Register_Bank/Reg_Bank_Sim.vhd new file mode 100644 index 0000000..9f4ef8d --- /dev/null +++ b/LAB10.srcs/TB_Register_Bank/imports/TB_Register_Bank/Reg_Bank_Sim.vhd @@ -0,0 +1,97 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 11:45:10 AM +-- Design Name: +-- Module Name: Reg_Bank_Sim - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg_Bank_Sim is +-- Port ( ); +end Reg_Bank_Sim; + +architecture Behavioral of Reg_Bank_Sim is +component Reg_Bank + Port ( Clk : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Reg_0_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_1_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_2_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_3_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_4_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_5_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_6_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_7_out : out STD_LOGIC_VECTOR (3 downto 0) + ); +end component; +signal Clk : STD_LOGIC:= '0'; +signal Reset : STD_LOGIC; +signal Data_in,Reg_0_out,Reg_1_out,Reg_2_out,Reg_3_out,Reg_4_out,Reg_5_out,Reg_6_out,Reg_7_out : STD_LOGIC_VECTOR (3 downto 0); +signal Reg_Enable : STD_LOGIC_VECTOR (2 downto 0); +begin + UUT :Reg_Bank + PORT MAP( + Clk=>Clk, + Data_in=>Data_in, + Reg_Enable=>Reg_Enable, + Reset=>Reset, + Reg_0_out=>Reg_0_out, + Reg_1_out=>Reg_1_out, + Reg_2_out=>Reg_2_out, + Reg_3_out=>Reg_3_out, + Reg_4_out=>Reg_4_out, + Reg_5_out=>Reg_5_out, + Reg_6_out=>Reg_6_out, + Reg_7_out=>Reg_7_out + ); + + process + begin + wait for 20ns; + Clk <= Not (Clk); + end process; + + process begin + Reset<='1'; + wait for 30ns; + Reset<='0'; + + Reg_Enable<="001"; + Data_in<="0111"; + wait for 100ns; + + Reg_Enable<="010"; + Data_in<="1011"; + wait; + + + end process; + +end Behavioral; diff --git a/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd b/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd new file mode 100644 index 0000000..44baac2 --- /dev/null +++ b/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd @@ -0,0 +1,48 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 01:52:13 PM +-- Design Name: +-- Module Name: Decoder_2_to_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Decoder_2_to_4 is + Port ( I : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end Decoder_2_to_4; + +architecture Behavioral of Decoder_2_to_4 is + +begin +Y(0) <= NOT(I(0)) AND NOT(I(1)) AND EN; +Y(1) <= I(0) AND NOT(I(1)) AND EN; +Y(2) <= NOT(I(0)) AND I(1) AND EN; +Y(3) <= I(0) AND I(1) AND EN; + +end Behavioral; diff --git a/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd b/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd new file mode 100644 index 0000000..9d988c9 --- /dev/null +++ b/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd @@ -0,0 +1,71 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 03:08:55 PM +-- Design Name: +-- Module Name: Decoder_3_to_8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Decoder_3_to_8 is + Port ( I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0)); +end Decoder_3_to_8; + +architecture Behavioral of Decoder_3_to_8 is +component Decoder_2_to_4 + port( + I : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0) + ); +end component; +signal I0, I1 : std_logic_vector(1 downto 0); +signal Y0, Y1 : std_logic_vector(3 downto 0); +signal en0, en1, I2 : std_logic; +begin +Decoder_2_to_4_0:Decoder_2_to_4 + port map( + I => I0, + EN => en0, + Y => Y0 + ); +Decoder_2_to_4_1 :Decoder_2_to_4 + port map( + I => I1, + En => en1, + Y => Y1 + ); +en0 <= NOT(I(2)) AND EN; +en1 <= I(2) AND EN; +I0 <= I(1 downto 0); +I1 <= I(1 downto 0); +I2 <= I(2); +Y(3 downto 0) <= Y0; +Y(7 downto 4) <= Y1; +end Behavioral; diff --git a/LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd b/LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd new file mode 100644 index 0000000..ee55a31 --- /dev/null +++ b/LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/16/2022 02:34:25 PM +-- Design Name: +-- Module Name: Reg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg is + Port ( D : in STD_LOGIC_VECTOR (3 downto 0); + En : in STD_LOGIC; + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR (3 downto 0)); +end Reg; + +architecture Behavioral of Reg is + +begin + process(Clk) + begin + if (rising_edge(Clk)) then -- respond when clock rises + if (Reset = '1') then -- reset the D flip flop + Q <= "0000"; + else + if (En = '1') then -- Enable should be set + Q <= D; + end if; + end if; + + end if; + end process; +end Behavioral; diff --git a/LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd b/LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd new file mode 100644 index 0000000..e76841d --- /dev/null +++ b/LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd @@ -0,0 +1,137 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 10:07:37 AM +-- Design Name: +-- Module Name: Reg_Bank - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg_Bank is + Port ( Clk : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Reg_0_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_1_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_2_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_3_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_4_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_5_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_6_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_7_out : out STD_LOGIC_VECTOR (3 downto 0) + ); +end Reg_Bank; + +architecture Behavioral of Reg_Bank is +component Reg + Port ( D : in STD_LOGIC_VECTOR (3 downto 0); + En : in STD_LOGIC; + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + +component Decoder_3_to_8 + Port ( I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0)); +end component; +signal R_Y : STD_LOGIC_VECTOR (7 downto 0); +begin + Decoder_3_to_8_0 : Decoder_3_to_8 + PORT MAP ( + I=>Reg_Enable, + EN => '1', + Y => R_Y + ); + Register_0 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(0), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_0_out + ); + Register_1 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(1), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_1_out + ); + Register_2 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(2), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_2_out + ); + Register_3 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(3), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_3_out + ); + Register_4 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(4), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_4_out + ); + Register_5 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(5), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_5_out + ); + Register_6 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(6), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_6_out + ); + Register_7 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(7), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_7_out + ); + +end Behavioral; diff --git a/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc b/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc new file mode 100644 index 0000000..8dbb954 --- /dev/null +++ b/LAB10.srcs/constrs_1/imports/Lab Sessions/Basys3Labs.xdc @@ -0,0 +1,295 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property PACKAGE_PIN W5 [get_ports Clk_In] + set_property IOSTANDARD LVCMOS33 [get_ports Clk_In] + create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports Clk_In] + +## Switches +#set_property PACKAGE_PIN V17 [get_ports {sw[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +#set_property PACKAGE_PIN V16 [get_ports {sw[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +#set_property PACKAGE_PIN W16 [get_ports {sw[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +#set_property PACKAGE_PIN W17 [get_ports {sw[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +#set_property PACKAGE_PIN W15 [get_ports {sw[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +#set_property PACKAGE_PIN V15 [get_ports {sw[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +#set_property PACKAGE_PIN W14 [get_ports {sw[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +#set_property PACKAGE_PIN W13 [get_ports {sw[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +#set_property PACKAGE_PIN V2 [get_ports {sw[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +#set_property PACKAGE_PIN T3 [get_ports {sw[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +#set_property PACKAGE_PIN T2 [get_ports {sw[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +#set_property PACKAGE_PIN R3 [get_ports {sw[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +#set_property PACKAGE_PIN W2 [get_ports {sw[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +#set_property PACKAGE_PIN U1 [get_ports {sw[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +#set_property PACKAGE_PIN T1 [get_ports {sw[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +#set_property PACKAGE_PIN R2 [get_ports {sw[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + +## LEDs +set_property PACKAGE_PIN U16 [get_ports {R7_out[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {R7_out[0]}] +set_property PACKAGE_PIN E19 [get_ports {R7_out[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {R7_out[1]}] +set_property PACKAGE_PIN U19 [get_ports {R7_out[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {R7_out[2]}] +set_property PACKAGE_PIN V19 [get_ports {R7_out[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {R7_out[3]}] +#set_property PACKAGE_PIN W18 [get_ports {led[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +#set_property PACKAGE_PIN U15 [get_ports {led[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +#set_property PACKAGE_PIN U14 [get_ports {led[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +#set_property PACKAGE_PIN V14 [get_ports {led[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +#set_property PACKAGE_PIN V13 [get_ports {led[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +#set_property PACKAGE_PIN V3 [get_ports {led[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +#set_property PACKAGE_PIN W3 [get_ports {led[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +#set_property PACKAGE_PIN U3 [get_ports {led[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +#set_property PACKAGE_PIN P3 [get_ports {led[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +#set_property PACKAGE_PIN N3 [get_ports {led[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +set_property PACKAGE_PIN P1 [get_ports {Zero}] + set_property IOSTANDARD LVCMOS33 [get_ports {Zero}] +set_property PACKAGE_PIN L1 [get_ports {OverFlow}] + set_property IOSTANDARD LVCMOS33 [get_ports {OverFlow}] + + +##7 segment display +set_property PACKAGE_PIN W7 [get_ports {S_7Seg_out[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {S_7Seg_out[0]}] +set_property PACKAGE_PIN W6 [get_ports {S_7Seg_out[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {S_7Seg_out[1]}] +set_property PACKAGE_PIN U8 [get_ports {S_7Seg_out[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {S_7Seg_out[2]}] +set_property PACKAGE_PIN V8 [get_ports {S_7Seg_out[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {S_7Seg_out[3]}] +set_property PACKAGE_PIN U5 [get_ports {S_7Seg_out[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {S_7Seg_out[4]}] +set_property PACKAGE_PIN V5 [get_ports {S_7Seg_out[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {S_7Seg_out[5]}] +set_property PACKAGE_PIN U7 [get_ports {S_7Seg_out[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {S_7Seg_out[6]}] + +#set_property PACKAGE_PIN V7 [get_ports dp] + #set_property IOSTANDARD LVCMOS33 [get_ports dp] + +set_property PACKAGE_PIN U2 [get_ports {anode_out[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode_out[0]}] +set_property PACKAGE_PIN U4 [get_ports {anode_out[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode_out[1]}] +set_property PACKAGE_PIN V4 [get_ports {anode_out[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode_out[2]}] +set_property PACKAGE_PIN W4 [get_ports {anode_out[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode_out[3]}] + + +##Buttons +set_property PACKAGE_PIN U18 [get_ports Reset] + set_property IOSTANDARD LVCMOS33 [get_ports Reset] +#set_property PACKAGE_PIN T18 [get_ports btnU] + #set_property IOSTANDARD LVCMOS33 [get_ports btnU] +#set_property PACKAGE_PIN W19 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +#set_property PACKAGE_PIN T17 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +#set_property PACKAGE_PIN U17 [get_ports btnD] + #set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Sch name = JA1 +#set_property PACKAGE_PIN J1 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Sch name = JA2 +#set_property PACKAGE_PIN L2 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Sch name = JA3 +#set_property PACKAGE_PIN J2 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Sch name = JA4 +#set_property PACKAGE_PIN G2 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Sch name = JA7 +#set_property PACKAGE_PIN H1 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Sch name = JA8 +#set_property PACKAGE_PIN K2 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Sch name = JA9 +#set_property PACKAGE_PIN H2 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Sch name = JA10 +#set_property PACKAGE_PIN G3 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Sch name = JB1 +#set_property PACKAGE_PIN A14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Sch name = JB2 +#set_property PACKAGE_PIN A16 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Sch name = JB3 +#set_property PACKAGE_PIN B15 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Sch name = JB4 +#set_property PACKAGE_PIN B16 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Sch name = JB7 +#set_property PACKAGE_PIN A15 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Sch name = JB8 +#set_property PACKAGE_PIN A17 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Sch name = JB9 +#set_property PACKAGE_PIN C15 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Sch name = JB10 +#set_property PACKAGE_PIN C16 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Sch name = JC1 +#set_property PACKAGE_PIN K17 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Sch name = JC2 +#set_property PACKAGE_PIN M18 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Sch name = JC3 +#set_property PACKAGE_PIN N17 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Sch name = JC4 +#set_property PACKAGE_PIN P18 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Sch name = JC7 +#set_property PACKAGE_PIN L17 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Sch name = JC8 +#set_property PACKAGE_PIN M19 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Sch name = JC9 +#set_property PACKAGE_PIN P17 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Sch name = JC10 +#set_property PACKAGE_PIN R18 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + +##Pmod Header JXADC +##Sch name = XA1_P +#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Sch name = XA2_P +#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Sch name = XA3_P +#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Sch name = XA4_P +#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Sch name = XA1_N +#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Sch name = XA2_N +#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Sch name = XA3_N +#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Sch name = XA4_N +#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +#set_property PACKAGE_PIN P19 [get_ports Hsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +#set_property PACKAGE_PIN R19 [get_ports Vsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + +##USB-RS232 Interface +#set_property PACKAGE_PIN B18 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +#set_property PACKAGE_PIN A18 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] + + +##USB HID (PS/2) +#set_property PACKAGE_PIN C17 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +#set_property PACKAGE_PIN B17 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +#set_property PACKAGE_PIN K19 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + diff --git a/LAB10.srcs/sim_1/AddSubUnitBit_4.vhd b/LAB10.srcs/sim_1/AddSubUnitBit_4.vhd new file mode 100644 index 0000000..fb89bb8 --- /dev/null +++ b/LAB10.srcs/sim_1/AddSubUnitBit_4.vhd @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 09:49:41 PM +-- Design Name: +-- Module Name: AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AddSubUnitBit_4 is + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end AddSubUnitBit_4; + +architecture Behavioral of AddSubUnitBit_4 is +component FA + PORT(A : in STD_LOGIC; + B : in STD_LOGIC; + C_in : in STD_LOGIC; + S : out STD_LOGIC; + C_out : out STD_LOGIC); +end component; + +SIGNAL FA0_S, FA0_C,FA1_S, FA1_C,FA2_S, FA2_C:STD_LOGIC; +SIGNAL Bi : STD_LOGIC_VECTOR (3 downto 0); +SIGNAL Si : STD_LOGIC_VECTOR (3 downto 0); + +begin + +Bi(0)<=(B(0) XOR AddSub_Select); +Bi(1)<=(B(1) XOR AddSub_Select); +Bi(2)<=(B(2) XOR AddSub_Select); +Bi(3)<=(B(3) XOR AddSub_Select); + +FA_0 : FA + PORT MAP ( + A=>A(0), + B => Bi(0), + C_in => AddSub_Select, + S => Si(0), + C_out=> FA0_C + ); + +FA_1 : FA + PORT MAP ( + A=>A(1), + B => Bi(1), + C_in => FA0_C, + S => Si(1), + C_out=> FA1_C + ); + +FA_2 : FA + PORT MAP ( + A=>A(2), + B => Bi(2), + C_in => FA1_C, + S => Si(2), + C_out=> FA2_C + ); + +FA_3 : FA + PORT MAP ( + A=>A(3), + B => Bi(3), + C_in => FA2_C, + S => Si(3), + C_out=> Overflow + ); +S<=Si; +Zero<= NOT(Si(0) OR Si(1) OR Si(2) OR Si(3)); +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/Reg_Bank_Sim.vhd b/LAB10.srcs/sim_1/new/Reg_Bank_Sim.vhd new file mode 100644 index 0000000..4d2e940 --- /dev/null +++ b/LAB10.srcs/sim_1/new/Reg_Bank_Sim.vhd @@ -0,0 +1,91 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 11:45:10 AM +-- Design Name: +-- Module Name: Reg_Bank_Sim - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg_Bank_Sim is +-- Port ( ); +end Reg_Bank_Sim; + +architecture Behavioral of Reg_Bank_Sim is +component Reg_Bank + Port ( Clk : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Reg_0_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_1_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_2_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_3_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_4_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_5_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_6_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_7_out : out STD_LOGIC_VECTOR (3 downto 0) + ); +end component; +signal Clk : STD_LOGIC:= '0'; +signal Reset : STD_LOGIC; +signal Data_in,Reg_0_out,Reg_1_out,Reg_2_out,Reg_3_out,Reg_4_out,Reg_5_out,Reg_6_out,Reg_7_out : STD_LOGIC_VECTOR (3 downto 0); +signal Reg_Enable : STD_LOGIC_VECTOR (2 downto 0); +begin + UUT :Reg_Bank + PORT MAP( + Clk=>Clk, + Data_in=>Data_in, + Reg_Enable=>Reg_Enable, + Reset=>Reset, + Reg_0_out=>Reg_0_out, + Reg_1_out=>Reg_1_out, + Reg_2_out=>Reg_2_out, + Reg_3_out=>Reg_3_out, + Reg_4_out=>Reg_4_out, + Reg_5_out=>Reg_5_out, + Reg_6_out=>Reg_6_out, + Reg_7_out=>Reg_7_out + ); + + process + begin + wait for 20ns; + Clk <= Not (Clk); + end process; + + process begin + Reset<='1'; + wait for 30ns; + Reset<='0'; + + Reg_Enable<="001"; + Data_in<="0111"; + + end process; + +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd b/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd new file mode 100644 index 0000000..c87df43 --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd @@ -0,0 +1,82 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/07/2022 07:13:45 PM +-- Design Name: +-- Module Name: TB_AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_AddSubUnitBit_4 is +-- Port ( ); +end TB_AddSubUnitBit_4; + +architecture Behavioral of TB_AddSubUnitBit_4 is +component AddSubUnitBit_4 + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end component; + signal A,B,S : STD_LOGIC_VECTOR (3 downto 0); + signal Overflow,Zero,AddSub_Select : STD_LOGIC:='0'; +begin +UUT: AddSubUnitBit_4 + PORT MAP( + A=>A, + B=>B, + S=>S, + Overflow=>Overflow, + Zero=>Zero, + AddSub_Select=>AddSub_Select + ); +process begin + + A<="0110"; + B<="1001"; + AddSub_Select<='0'; + WAIT FOR 100ns; + + A<="0110"; + B<="1001"; + AddSub_Select<='1'; + WAIT FOR 100ns; + + A<="1111"; + B<="0001"; + AddSub_Select<='0'; + WAIT FOR 100ns; + + A<="1111"; + B<="0001"; + AddSub_Select<='1'; + WAIT; + +end process; +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_AdderBit_3.vhd b/LAB10.srcs/sim_1/new/TB_AdderBit_3.vhd new file mode 100644 index 0000000..321a21e --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_AdderBit_3.vhd @@ -0,0 +1,43 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/26/2022 01:45:41 AM +-- Design Name: +-- Module Name: TB_AdderBit_3 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_AdderBit_3 is +-- Port ( ); +end TB_AdderBit_3; + +architecture Behavioral of TB_AdderBit_3 is + +begin + + +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_Decoder_3_to_8.vhd b/LAB10.srcs/sim_1/new/TB_Decoder_3_to_8.vhd new file mode 100644 index 0000000..3d7e59d --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_Decoder_3_to_8.vhd @@ -0,0 +1,43 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/25/2022 07:20:05 PM +-- Design Name: +-- Module Name: TB_Decoder_3_to_8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Decoder_3_to_8 is +-- Port ( ); +end TB_Decoder_3_to_8; + +architecture Behavioral of TB_Decoder_3_to_8 is + +begin + + +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_Mux_2_to_1_3bit.vhd b/LAB10.srcs/sim_1/new/TB_Mux_2_to_1_3bit.vhd new file mode 100644 index 0000000..9b11f36 --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_Mux_2_to_1_3bit.vhd @@ -0,0 +1,43 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/25/2022 08:22:05 PM +-- Design Name: +-- Module Name: TB_Mux_2_to_1_3bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Mux_2_to_1_3bit is +-- Port ( ); +end TB_Mux_2_to_1_3bit; + +architecture Behavioral of TB_Mux_2_to_1_3bit is + +begin + + +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_Mux_2_to_1_4bit.vhd b/LAB10.srcs/sim_1/new/TB_Mux_2_to_1_4bit.vhd new file mode 100644 index 0000000..c1ca5f4 --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_Mux_2_to_1_4bit.vhd @@ -0,0 +1,43 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/25/2022 07:47:33 PM +-- Design Name: +-- Module Name: TB_Mux_2_to_1_4bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Mux_2_to_1_4bit is +-- Port ( ); +end TB_Mux_2_to_1_4bit; + +architecture Behavioral of TB_Mux_2_to_1_4bit is + +begin + + +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_Processor.vhd b/LAB10.srcs/sim_1/new/TB_Processor.vhd new file mode 100644 index 0000000..962c634 --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_Processor.vhd @@ -0,0 +1,43 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/26/2022 03:39:53 AM +-- Design Name: +-- Module Name: TB_Processor - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Processor is +-- Port ( ); +end TB_Processor; + +architecture Behavioral of TB_Processor is + +begin + + +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_Program_ROM.vhd b/LAB10.srcs/sim_1/new/TB_Program_ROM.vhd new file mode 100644 index 0000000..75d9c01 --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_Program_ROM.vhd @@ -0,0 +1,43 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/26/2022 01:40:40 AM +-- Design Name: +-- Module Name: TB_Program_ROM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Program_ROM is +-- Port ( ); +end TB_Program_ROM; + +architecture Behavioral of TB_Program_ROM is + +begin + + +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd b/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd index 59afa49..44baac2 100644 --- a/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd +++ b/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd @@ -2,7 +2,7 @@ -- Company: -- Engineer: -- --- Create Date: 06/02/2022 01:46:52 PM +-- Create Date: 06/02/2022 01:52:13 PM -- Design Name: -- Module Name: Decoder_2_to_4 - Behavioral -- Project Name: @@ -45,5 +45,4 @@ Y(1) <= I(0) AND NOT(I(1)) AND EN; Y(2) <= NOT(I(0)) AND I(1) AND EN; Y(3) <= I(0) AND I(1) AND EN; - end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd b/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd index a1ee633..9d988c9 100644 --- a/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd +++ b/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd @@ -2,7 +2,7 @@ -- Company: -- Engineer: -- --- Create Date: 06/02/2022 02:20:39 PM +-- Create Date: 06/02/2022 03:08:55 PM -- Design Name: -- Module Name: Decoder_3_to_8 - Behavioral -- Project Name: @@ -38,35 +38,34 @@ entity Decoder_3_to_8 is end Decoder_3_to_8; architecture Behavioral of Decoder_3_to_8 is - component Decoder_2_to_4 - PORT( - I: in STD_LOGIC_VECTOR; - EN: in STD_LOGIC; - Y: out STD_LOGIC_VECTOR - ); - end component; - signal EN0,EN1,I0,I1,I2 : STD_LOGIC; - --signal Y0,Y1 : STD_LOGIC_VECTOR (3 downto 0); - +component Decoder_2_to_4 + port( + I : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0) + ); +end component; +signal I0, I1 : std_logic_vector(1 downto 0); +signal Y0, Y1 : std_logic_vector(3 downto 0); +signal en0, en1, I2 : std_logic; begin -Decoder_2_to_4_0 :Decoder_2_to_4 - PORT MAP( - I(0) => I0, - I(1) => I1, - EN => EN0, - Y => Y(3 downto 0) +Decoder_2_to_4_0:Decoder_2_to_4 + port map( + I => I0, + EN => en0, + Y => Y0 ); Decoder_2_to_4_1 :Decoder_2_to_4 - PORT MAP( - I(0) => I0, - I(1)=> i1, - en => en1, - y => y(7 DOWNTO 4)); - - I0 <= I(0); - I1 <= I(1); - EN0 <= not(I(2)) AND EN; - EN1 <= I(2)AND EN; - - + port map( + I => I1, + En => en1, + Y => Y1 + ); +en0 <= NOT(I(2)) AND EN; +en1 <= I(2) AND EN; +I0 <= I(1 downto 0); +I1 <= I(1 downto 0); +I2 <= I(2); +Y(3 downto 0) <= Y0; +Y(7 downto 4) <= Y1; end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd b/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd new file mode 100644 index 0000000..aebe966 --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd @@ -0,0 +1,132 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 03:35:24 PM +-- Design Name: +-- Module Name: Instruction_Decoder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Instruction_Decoder is + Port ( Instruction_Bus : in STD_LOGIC_VECTOR (11 downto 0); + Reg_Check_for_Jump : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : out STD_LOGIC_VECTOR (2 downto 0); + Load_Select : out STD_LOGIC; + Immediate_value : out STD_LOGIC_VECTOR (3 downto 0); + Register_select_01 : out STD_LOGIC_VECTOR (2 downto 0); + Register_select_02 : out STD_LOGIC_VECTOR (2 downto 0); + ADD_SUB_Select : out STD_LOGIC; + Jump_Flag : out STD_LOGIC; + Address_to_jump : out STD_LOGIC_VECTOR (2 downto 0)); +end Instruction_Decoder; + +architecture Behavioral of Instruction_Decoder is + +component Decoder_2_to_4 + Port ( I : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + Signal MOVI,ADD,NEG,JZR : STD_LOGIC; + Signal StatusOfReg : STD_LOGIC; + + begin + + Decoder_2_to_4_0 : Decoder_2_to_4 + port map( + I(0) => Instruction_Bus(10), + I(1) => Instruction_Bus(11), + EN => '1', + Y(0)=> ADD, + Y(1) => NEG, + Y(2) => MOVI, + Y(3) => JZR); +-- If load_Select = 1 addsubunit will be selected if load_Select = 0 immediate value will be selected +Load_Select <= ADD OR NEG; +ADD_SUB_Select <= NEG; +Jump_Flag <= JZR AND (NOT(Reg_Check_for_Jump(0) OR Reg_Check_for_Jump(1) OR Reg_Check_for_Jump(2) OR Reg_Check_for_Jump(3) ) ); +StatusOfReg <= MOVI OR ADD OR NEG; + +--Reg_Enable <= Instruction_Bus(9 downto 7) WHEN StatusOfReg='1' ELSE "000"; + +Reg_Enable(0) <= StatusOfReg AND Instruction_Bus(7); +Reg_Enable(1) <= StatusOfReg AND Instruction_Bus(8); +Reg_Enable(2) <= StatusOfReg AND Instruction_Bus(9); + +Address_to_jump <= Instruction_Bus(2 downto 0); +Immediate_value <= Instruction_Bus(3 downto 0); + +--needed only in addition negation? +Register_select_02 <= Instruction_Bus(9 downto 7); +Register_select_01 <= Instruction_Bus(6 downto 4); + +end Behavioral; + +-- +--signal Instruction_Select : STD_LOGIC_VECTOR (1 downto 0); +--begin + +--getting the num for Selecting the instruction +--Instruction_Select<=Instruction_Bus(11 downto 10); +--process begin +--case Instruction_Select is --Selecting the instruction +-- when "00"=> + --Add values in registers Ra and Rb and store the result in Ra +-- Register_select_01<=Instruction_Bus(9 downto 7); +-- Register_select_02<=Instruction_Bus(6 downto 4); +-- ADD_SUB_Select<='0'; +-- Load_Select<='1'; --if 1 selecty the output of 4 bit addsub, if 0 select imediate value +-- Reg_Enable<=Instruction_Bus(9 downto 7); + +-- when "01"=> + --2's complement of registers R +-- Register_select_01<="000"; +-- Register_select_02<=Instruction_Bus(9 downto 7); +-- ADD_SUB_Select<='1'; +-- Load_Select<='1'; +-- Reg_Enable<=Instruction_Bus(9 downto 7); + + +-- when "10"=> + --Move immediate value d to register R +-- Immediate_value<=Instruction_Bus(3 downto 0); +-- Load_Select<='0'; +-- Reg_Enable<=Instruction_Bus(9 downto 7); + +-- when "11"=> +-- Register_select_01<=Instruction_Bus(9 downto 7); +-- if(Reg_Check_for_Jump="0000") then +-- Jump_Flag<='1'; +-- Address_to_jump<=Instruction_Bus(2 downto 0); +-- else +-- Jump_Flag<='0'; +-- end if; +--end case; +--wait; +--end process; +--end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd b/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd new file mode 100644 index 0000000..560d432 --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/LUT_16_7.vhd @@ -0,0 +1,64 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/27/2022 07:21:29 AM +-- Design Name: +-- Module Name: LUT_16_7 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity LUT_16_7 is + Port ( address : in STD_LOGIC_VECTOR (3 downto 0); + data : out STD_LOGIC_VECTOR (6 downto 0)); +end LUT_16_7; + +architecture Behavioral of LUT_16_7 is +type rom_type is array (0 to 15) of std_logic_vector(6 downto 0); + signal sevenSegment_ROM : rom_type := ( + "1000000", + "1111001", + "0100100", + "0110000", + "0011001", + "0010010", + "0000010", + "1111000", + "0000000", + "0010000", + "0001000", + "0000011", + "1000110", + "0100001", + "0000110", + "0001110" + ); + +begin +data <= sevenSegment_ROM(to_integer(unsigned(address))); + +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Mux_8_to_1.vhd b/LAB10.srcs/sources_1/imports/new/Mux_8_to_1.vhd index 0ac98e9..fa3cf65 100644 --- a/LAB10.srcs/sources_1/imports/new/Mux_8_to_1.vhd +++ b/LAB10.srcs/sources_1/imports/new/Mux_8_to_1.vhd @@ -32,40 +32,19 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity Mux_2way_3bit is - Port ( S : in STD_LOGIC_VECTOR (2 downto 0); - D : in STD_LOGIC_VECTOR (7 downto 0); + Port ( JumpFlag : in STD_LOGIC; + Adder3BitOut : in STD_LOGIC_VECTOR (2 downto 0); + AddressToJump : in STD_LOGIC_VECTOR (2 downto 0); + -- enable signal EN : in STD_LOGIC; - Y : out STD_LOGIC); + -- output + Output : out STD_LOGIC_VECTOR (2 downto 0)); end Mux_2way_3bit; architecture Behavioral of Mux_2way_3bit is - component Decoder_3_to_8 - Port(I: in STD_LOGIC_VECTOR; - EN: in STD_LOGIC; - Y: out STD_LOGIC_VECTOR - ); - - - end component; - signal DY : STD_LOGIC_VECTOR (7 downto 0); + begin - Decoder_3_to_8_0 : Decoder_3_to_8 - PORT MAP ( - I=>S, - EN => EN, - Y => DY - ); - - Y <= EN AND ((D(0) AND DY(0)) - OR (D(1) AND DY(1)) - OR (D(2) AND DY(2)) - OR (D(3) AND DY(3)) - OR (D(4) AND DY(4)) - OR (D(5) AND DY(5)) - OR (D(6) AND DY(6)) - OR (D(7) AND DY(7))); - - +Output <= Adder3BitOut WHEN (JumpFlag='0') ELSE AddressToJump; end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd b/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd new file mode 100644 index 0000000..b25d147 --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd @@ -0,0 +1,134 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 03:21:23 PM +-- Design Name: +-- Module Name: Mux_2way_4bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Mux_8way_4bit is + +-- RegSel will select the register from D1 to D8 it's 3 bit signal + Port ( RegSel : in STD_LOGIC_VECTOR (2 downto 0); + + -- 8 registers + R0 : in STD_LOGIC_VECTOR (3 downto 0); + R1 : in STD_LOGIC_VECTOR (3 downto 0); + R2 : in STD_LOGIC_VECTOR (3 downto 0); + R3 : in STD_LOGIC_VECTOR (3 downto 0); + R4 : in STD_LOGIC_VECTOR (3 downto 0); + R5 : in STD_LOGIC_VECTOR (3 downto 0); + R6 : in STD_LOGIC_VECTOR (3 downto 0); + R7 : in STD_LOGIC_VECTOR (3 downto 0); + + -- enable signal + EN : in STD_LOGIC; + + -- output signal + Output : out std_logic_vector (3 downto 0)); +end Mux_8way_4bit; + +architecture Behavioral of Mux_8way_4bit is + +--adding decoder +component Decoder_3_to_8 +port ( I : in STD_LOGIC_VECTOR (2 downto 0); + Y : out STD_LOGIC_VECTOR (7 downto 0); + EN : in STD_LOGIC); +end component; + +--adding tri state buffer +component quad_tri_state_buffer +Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + + +SIGNAL common_bus : std_logic_vector (3 downto 0); +SIGNAL RegSel_var : std_logic_vector(7 downto 0); + + +begin + +Decoder_3_to_8_0 : Decoder_3_to_8 + port map ( + I(2 downto 0) => RegSel(2 downto 0), + EN => '1', + Y(7 downto 0) => RegSel_var(7 downto 0)); + +quad_tri_state_buffer_0 : quad_tri_state_buffer +port map( +EN => RegSel_var(0), +A => R0, +Y => common_bus); + +quad_tri_state_buffer_1 : quad_tri_state_buffer +port map( +EN => RegSel_var(1), +A => R1, +Y => common_bus); + +quad_tri_state_buffer_2 : quad_tri_state_buffer +port map( +EN => RegSel_var(2), +A => R2, +Y => common_bus); + +quad_tri_state_buffer_3 : quad_tri_state_buffer +port map( +EN => RegSel_var(3), +A => R3, +Y => common_bus); + +quad_tri_state_buffer_4 : quad_tri_state_buffer +port map( +EN => RegSel_var(4), +A => R4, +Y => common_bus); + +quad_tri_state_buffer_5 : quad_tri_state_buffer +port map( +EN => RegSel_var(5), +A => R5, +Y => common_bus); + +quad_tri_state_buffer_6 : quad_tri_state_buffer +port map( +EN => RegSel_var(6), +A => R6, +Y => common_bus); + +quad_tri_state_buffer_7 : quad_tri_state_buffer +port map( +EN => RegSel_var(7), +A => R7, +Y => common_bus); +Output <= common_bus; + +end Behavioral; \ No newline at end of file diff --git a/LAB10.srcs/sources_1/imports/new/Program_ROM.vhd b/LAB10.srcs/sources_1/imports/new/Program_ROM.vhd new file mode 100644 index 0000000..5974ae0 --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/Program_ROM.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 02:41:04 PM +-- Design Name: +-- Module Name: Program_ROM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Program_ROM is + Port ( Memory_Select : in STD_LOGIC_VECTOR (2 downto 0); + Instruction_Bus : out STD_LOGIC_VECTOR (11 downto 0)); +end Program_ROM; + +architecture Behavioral of Program_ROM is +type rom_type is array (0 to 7) of std_logic_vector(11 downto 0); +signal sevenSegment_ROM : rom_type := ( + "100010001010", -- 0 + "100100000001", -- 1 + "010100000000", -- 2 + "000010100000", -- 3 + "110010000111", -- 4 + "110000000011", -- 5 + "111111111111", -- 6 + "111111111111"-- 7 + ,"111111111111"-- 8 + ); + +begin + +Instruction_Bus <= sevenSegment_ROM(to_integer(unsigned(Memory_Select))); + + + +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Program_counter.vhd b/LAB10.srcs/sources_1/imports/new/Program_counter.vhd new file mode 100644 index 0000000..b9d2e5e --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/Program_counter.vhd @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 02:41:04 PM +-- Design Name: +-- Module Name: Program_ROM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Program_ROM is + Port ( Memory_Select : in STD_LOGIC_VECTOR (2 downto 0); + Instruction_Bus : out STD_LOGIC_VECTOR (11 downto 0)); +end Program_ROM; + +architecture Behavioral of Program_ROM is +type rom_type is array (0 to 7) of std_logic_vector(11 downto 0); +signal sevenSegment_ROM : rom_type := ( +--"101110001010", -- 0 +--"100100000001", -- 1 +--"010100000000", -- 2 +--"001110100000", -- 3 +--"111110000111", -- 4 +--"110000000011", -- 5 +--"111111111111", -- 6 +--"111111111111" -- 7 + "100100000010", -- 1 - Move 2 to R2 + "100110000011", -- 2 - Move 3 to R3 + "101110000001", -- 3 - Move 1 to R1 + "001110100000", -- 4 - R7<=R7+R2 + "001110110000", -- 5 - R7<=R7+R3 + "110000000110", -- 6 - Jump to instruction 6 (If R0 is 0) + "110000000101", -- 7 - Jump to instruction 5 (If R0 is 0) + "110000000101" -- 7 + + ); + +begin + +Instruction_Bus <= sevenSegment_ROM(to_integer(unsigned(Memory_Select))); + + + +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/RCA.vhd b/LAB10.srcs/sources_1/imports/new/RCA.vhd index 3fc9154..fb89bb8 100644 --- a/LAB10.srcs/sources_1/imports/new/RCA.vhd +++ b/LAB10.srcs/sources_1/imports/new/RCA.vhd @@ -32,20 +32,12 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity AddSubUnitBit_4 is - Port ( A0 : in STD_LOGIC; - A1 : in STD_LOGIC; - A2 : in STD_LOGIC; - A3 : in STD_LOGIC; - B0 : in STD_LOGIC; - B1 : in STD_LOGIC; - B2 : in STD_LOGIC; - B3 : in STD_LOGIC; - C_in : in STD_LOGIC; - S0 : out STD_LOGIC; - S1 : out STD_LOGIC; - S2 : out STD_LOGIC; - S3 : out STD_LOGIC; - C_out : out STD_LOGIC); + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); end AddSubUnitBit_4; architecture Behavioral of AddSubUnitBit_4 is @@ -58,43 +50,51 @@ component FA end component; SIGNAL FA0_S, FA0_C,FA1_S, FA1_C,FA2_S, FA2_C:STD_LOGIC; +SIGNAL Bi : STD_LOGIC_VECTOR (3 downto 0); +SIGNAL Si : STD_LOGIC_VECTOR (3 downto 0); begin +Bi(0)<=(B(0) XOR AddSub_Select); +Bi(1)<=(B(1) XOR AddSub_Select); +Bi(2)<=(B(2) XOR AddSub_Select); +Bi(3)<=(B(3) XOR AddSub_Select); + FA_0 : FA PORT MAP ( - A=>A0, - B => B0, - C_in => '0', - S => S0, + A=>A(0), + B => Bi(0), + C_in => AddSub_Select, + S => Si(0), C_out=> FA0_C ); FA_1 : FA PORT MAP ( -A=>A1, -B => B1, -C_in => FA0_C, -S => S1, -C_out=> FA1_C -); + A=>A(1), + B => Bi(1), + C_in => FA0_C, + S => Si(1), + C_out=> FA1_C + ); FA_2 : FA PORT MAP ( -A=>A2, -B => B2, -C_in => FA1_C, -S => S2, -C_out=> FA2_C -); + A=>A(2), + B => Bi(2), + C_in => FA1_C, + S => Si(2), + C_out=> FA2_C + ); FA_3 : FA PORT MAP ( -A=>A3, -B => B3, -C_in => FA2_C, -S => S3, -C_out=> C_out -); - + A=>A(3), + B => Bi(3), + C_in => FA2_C, + S => Si(3), + C_out=> Overflow + ); +S<=Si; +Zero<= NOT(Si(0) OR Si(1) OR Si(2) OR Si(3)); end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/RCA_4.vhd b/LAB10.srcs/sources_1/imports/new/RCA_4.vhd new file mode 100644 index 0000000..b3db622 --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/RCA_4.vhd @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/31/2022 01:17:12 PM +-- Design Name: +-- Module Name: RCA_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RCA_4 is + Port ( A0 : in STD_LOGIC; + A1 : in STD_LOGIC; + A2 : in STD_LOGIC; + A3 : in STD_LOGIC; + B0 : in STD_LOGIC; + B1 : in STD_LOGIC; + B2 : in STD_LOGIC; + B3 : in STD_LOGIC; + C_in : in STD_LOGIC; + S0 : out STD_LOGIC; + S1 : out STD_LOGIC; + S2 : out STD_LOGIC; + S3 : out STD_LOGIC; + C_out : out STD_LOGIC); +end RCA_4; + +architecture Behavioral of RCA_4 is +component FA + port( + A : in STD_LOGIC; + B : in STD_LOGIC; + C_in : in STD_LOGIC; + S : out STD_LOGIC; + C_out : out STD_LOGIC); +end component; +signal FA0_S, FA0_C, FA1_S, FA1_C, FA2_S, FA2_C, FA3_S, FA3_C : std_logic; +begin +FA_0 : FA + port map( + A => A0, + B => B0, + C_in => C_in, + S => FA0_S, + C_out => FA0_C); + +FA_1 : FA + port map( + A => A1, + B => B1, + C_in => FA0_C, + S => FA1_S, + C_out => FA1_C); + +FA_2 : FA + port map( + A => A2, + B => B2, + C_in => FA1_C, + S =>FA2_S, + C_out => FA2_C); + +FA_3 : FA + port map( + A => A3, + B => B3, + C_in => FA2_C, + S => FA3_S, + C_out => FA3_C); + +S0 <= FA0_S; +S1 <= FA1_S; +S2 <= FA2_S; +S3 <= FA3_S; +C_out <= FA3_C; + +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Reg.vhd b/LAB10.srcs/sources_1/imports/new/Reg.vhd index 5289a27..ee55a31 100644 --- a/LAB10.srcs/sources_1/imports/new/Reg.vhd +++ b/LAB10.srcs/sources_1/imports/new/Reg.vhd @@ -34,6 +34,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity Reg is Port ( D : in STD_LOGIC_VECTOR (3 downto 0); En : in STD_LOGIC; + Reset : in STD_LOGIC; Clk : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end Reg; @@ -44,9 +45,14 @@ begin process(Clk) begin if (rising_edge(Clk)) then -- respond when clock rises - if (En = '1') then -- Enable should be set - Q <= D; - end if; + if (Reset = '1') then -- reset the D flip flop + Q <= "0000"; + else + if (En = '1') then -- Enable should be set + Q <= D; + end if; + end if; + end if; end process; end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Register_bank.vhd b/LAB10.srcs/sources_1/imports/new/Register_bank.vhd new file mode 100644 index 0000000..6a88a74 --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/Register_bank.vhd @@ -0,0 +1,141 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/10/2022 12:40:31 PM +-- Design Name: +-- Module Name: Register_bank - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Register_bank is + Port ( + Clk: in std_logic; + Reg_en : in std_logic_vector (2 downto 0); + D : in std_logic_vector (3 downto 0); + -- 8 registers + R0 : out STD_LOGIC_VECTOR (3 downto 0); + R1 : out STD_LOGIC_VECTOR (3 downto 0); + R2 : out STD_LOGIC_VECTOR (3 downto 0); + R3 : out STD_LOGIC_VECTOR (3 downto 0); + R4 : out STD_LOGIC_VECTOR (3 downto 0); + R5 : out STD_LOGIC_VECTOR (3 downto 0); + R6 : out STD_LOGIC_VECTOR (3 downto 0); + R7 : out STD_LOGIC_VECTOR (3 downto 0); + Reset : in STD_LOGIC + ); +end Register_bank; + +architecture Behavioral of Register_bank is +component Reg + Port ( D : in STD_LOGIC_VECTOR (3 downto 0); + En : in STD_LOGIC; + Clk : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR (3 downto 0); + Reset : in STD_LOGIC); +end component; +component Decoder_3_to_8 + port ( + I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0) + ); +end component; +signal D0 : std_logic_vector (3 downto 0); +signal En : std_logic_vector(7 downto 0); +begin +Decoder_3_to_8_0 : Decoder_3_to_8 + port map( + EN => '1', + I => Reg_en, + Y => En + ); +R01 : Reg + port map( + D => D0, + Q => R0, + En => En(0), + Reset=>Reset, + Clk => Clk + ); +R11 : Reg + port map( + D => D, + Q => R1, + En => En(1), + Reset=>Reset, + Clk => Clk + ); +R21 : Reg + port map( + D => D, + Q => R2, + En => En(2), + Reset=>Reset, + Clk => Clk + ); +R31 : Reg + port map( + D => D, + Q =>R3, + En => En(3), + Reset=>Reset, + Clk => Clk + ); +R41 : Reg + port map( + D => D, + Q => R4, + En => En(4), + Reset=>Reset, + Clk => Clk + ); +R51 : Reg + port map( + D => D, + Q => R5, + En => En(5), + Reset=>Reset, + Clk => Clk + ); +R61 : Reg + port map( + D => D, + Q => R6, + En => En(6), + Reset=>Reset, + Clk => Clk + ); +R71 : Reg + port map( + D => D, + Q =>R7, + En => En(7), + Reset=>Reset, + Clk => Clk + ); +D0 <= "0000"; +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd b/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd index c67d63f..ca9d187 100644 --- a/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd +++ b/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd @@ -2,7 +2,7 @@ -- Company: -- Engineer: -- --- Create Date: 06/09/2022 02:47:54 PM +-- Create Date: 06/18/2022 04:56:08 AM -- Design Name: -- Module Name: Slow_Clk - Behavioral -- Project Name: @@ -37,22 +37,23 @@ entity Slow_Clk is end Slow_Clk; architecture Behavioral of Slow_Clk is -signal count : integer := 1; -signal clk_status : STD_LOGIC := '0'; -begin +signal count:integer:=1; +signal Clk_status:std_logic:='0'; +begin process (Clk_in) begin if (rising_edge(Clk_in)) then - count <= count +1; - if (count = 5) then - clk_status <= not clk_status; - Clk_out <= clk_status; - count <= 1; + count<=count+1; + if (count=100000000) then + --if (count=1) then + + Clk_status<=not Clk_status; + Clk_out<=Clk_status; + count<=1; end if; end if; end process; - end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd b/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd new file mode 100644 index 0000000..d9f9c77 --- /dev/null +++ b/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 09:49:41 PM +-- Design Name: +-- Module Name: AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity AddSubUnitBit_4 is + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end AddSubUnitBit_4; + +architecture Behavioral of AddSubUnitBit_4 is +component FA + PORT(A : in STD_LOGIC; + B : in STD_LOGIC; + C_in : in STD_LOGIC; + S : out STD_LOGIC; + C_out : out STD_LOGIC); +end component; + +SIGNAL FA0_C, FA1_C, FA2_C:STD_LOGIC; +SIGNAL Bi : STD_LOGIC_VECTOR (3 downto 0); +SIGNAL Si : STD_LOGIC_VECTOR (3 downto 0); + +begin + +Bi(0)<=(B(0) XOR AddSub_Select); +Bi(1)<=(B(1) XOR AddSub_Select); +Bi(2)<=(B(2) XOR AddSub_Select); +Bi(3)<=(B(3) XOR AddSub_Select); + +FA_0 : FA + PORT MAP ( + A=>A(0), + B => Bi(0), + C_in => AddSub_Select, + S => Si(0), + C_out=> FA0_C + ); + +FA_1 : FA + PORT MAP ( + A=>A(1), + B => Bi(1), + C_in => FA0_C, + S => Si(1), + C_out=> FA1_C + ); + +FA_2 : FA + PORT MAP ( + A=>A(2), + B => Bi(2), + C_in => FA1_C, + S => Si(2), + C_out=> FA2_C + ); + +FA_3 : FA + PORT MAP ( + A=>A(3), + B => Bi(3), + C_in => FA2_C, + S => Si(3), + C_out=> Overflow + ); +S<=Si; +Zero<= NOT(Si(0) OR Si(1) OR Si(2) OR Si(3)); +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/AdderBit_3.vhd b/LAB10.srcs/sources_1/new/AdderBit_3.vhd new file mode 100644 index 0000000..9ded0de --- /dev/null +++ b/LAB10.srcs/sources_1/new/AdderBit_3.vhd @@ -0,0 +1,86 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.06.2022 13:10:47 +-- Design Name: +-- Module Name: RCA - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +-- 3 bit adder + +entity AdderBit_3 is + Port ( PreviousAddressPC : in STD_LOGIC_VECTOR (2 downto 0); + NextAddressPC : out STD_LOGIC_VECTOR (2 downto 0); + C_OUT : out STD_LOGIC); +end AdderBit_3; + +architecture Behavioral of AdderBit_3 is + +component FA + port ( + A: in std_logic; + B: in std_logic; + C_in: in std_logic; + S: out std_logic; + C_out: out std_logic); +end component; + +SIGNAL FA0_C, FA1_C, FA2_C, FA3_C : std_logic; + + +begin + + FA_0 : FA + port map ( + A => PreviousAddressPC(0), + -- B is 1 because we are adding 001 always + B => '1', + C_in => '0', + S => NextAddressPC(0), + C_Out => FA0_C); + FA_1 : FA + port map ( + A => PreviousAddressPC(1), + -- B is 0 because we are adding 001 always + B => '0', + C_in => FA0_C, + S => NextAddressPC(1), + C_Out => FA1_C); + FA_2 : FA + port map ( + A => PreviousAddressPC(2), + -- B is 0 because we are adding 001 always + B => '0', + C_in => FA1_C, + S => NextAddressPC(2), + C_Out => FA2_C); + + + +end Behavioral; \ No newline at end of file diff --git a/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd b/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd new file mode 100644 index 0000000..aebe966 --- /dev/null +++ b/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd @@ -0,0 +1,132 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 03:35:24 PM +-- Design Name: +-- Module Name: Instruction_Decoder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Instruction_Decoder is + Port ( Instruction_Bus : in STD_LOGIC_VECTOR (11 downto 0); + Reg_Check_for_Jump : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : out STD_LOGIC_VECTOR (2 downto 0); + Load_Select : out STD_LOGIC; + Immediate_value : out STD_LOGIC_VECTOR (3 downto 0); + Register_select_01 : out STD_LOGIC_VECTOR (2 downto 0); + Register_select_02 : out STD_LOGIC_VECTOR (2 downto 0); + ADD_SUB_Select : out STD_LOGIC; + Jump_Flag : out STD_LOGIC; + Address_to_jump : out STD_LOGIC_VECTOR (2 downto 0)); +end Instruction_Decoder; + +architecture Behavioral of Instruction_Decoder is + +component Decoder_2_to_4 + Port ( I : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); + end component; + + Signal MOVI,ADD,NEG,JZR : STD_LOGIC; + Signal StatusOfReg : STD_LOGIC; + + begin + + Decoder_2_to_4_0 : Decoder_2_to_4 + port map( + I(0) => Instruction_Bus(10), + I(1) => Instruction_Bus(11), + EN => '1', + Y(0)=> ADD, + Y(1) => NEG, + Y(2) => MOVI, + Y(3) => JZR); +-- If load_Select = 1 addsubunit will be selected if load_Select = 0 immediate value will be selected +Load_Select <= ADD OR NEG; +ADD_SUB_Select <= NEG; +Jump_Flag <= JZR AND (NOT(Reg_Check_for_Jump(0) OR Reg_Check_for_Jump(1) OR Reg_Check_for_Jump(2) OR Reg_Check_for_Jump(3) ) ); +StatusOfReg <= MOVI OR ADD OR NEG; + +--Reg_Enable <= Instruction_Bus(9 downto 7) WHEN StatusOfReg='1' ELSE "000"; + +Reg_Enable(0) <= StatusOfReg AND Instruction_Bus(7); +Reg_Enable(1) <= StatusOfReg AND Instruction_Bus(8); +Reg_Enable(2) <= StatusOfReg AND Instruction_Bus(9); + +Address_to_jump <= Instruction_Bus(2 downto 0); +Immediate_value <= Instruction_Bus(3 downto 0); + +--needed only in addition negation? +Register_select_02 <= Instruction_Bus(9 downto 7); +Register_select_01 <= Instruction_Bus(6 downto 4); + +end Behavioral; + +-- +--signal Instruction_Select : STD_LOGIC_VECTOR (1 downto 0); +--begin + +--getting the num for Selecting the instruction +--Instruction_Select<=Instruction_Bus(11 downto 10); +--process begin +--case Instruction_Select is --Selecting the instruction +-- when "00"=> + --Add values in registers Ra and Rb and store the result in Ra +-- Register_select_01<=Instruction_Bus(9 downto 7); +-- Register_select_02<=Instruction_Bus(6 downto 4); +-- ADD_SUB_Select<='0'; +-- Load_Select<='1'; --if 1 selecty the output of 4 bit addsub, if 0 select imediate value +-- Reg_Enable<=Instruction_Bus(9 downto 7); + +-- when "01"=> + --2's complement of registers R +-- Register_select_01<="000"; +-- Register_select_02<=Instruction_Bus(9 downto 7); +-- ADD_SUB_Select<='1'; +-- Load_Select<='1'; +-- Reg_Enable<=Instruction_Bus(9 downto 7); + + +-- when "10"=> + --Move immediate value d to register R +-- Immediate_value<=Instruction_Bus(3 downto 0); +-- Load_Select<='0'; +-- Reg_Enable<=Instruction_Bus(9 downto 7); + +-- when "11"=> +-- Register_select_01<=Instruction_Bus(9 downto 7); +-- if(Reg_Check_for_Jump="0000") then +-- Jump_Flag<='1'; +-- Address_to_jump<=Instruction_Bus(2 downto 0); +-- else +-- Jump_Flag<='0'; +-- end if; +--end case; +--wait; +--end process; +--end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd b/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd new file mode 100644 index 0000000..e494a38 --- /dev/null +++ b/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd @@ -0,0 +1,48 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Pabasara Jayasekara +-- +-- Create Date: 07/25/2022 08:32:21 PM +-- Design Name: +-- Module Name: Mux_2_to_1_3bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Mux_2way_3bit is + Port ( JumpFlag : in STD_LOGIC; + EN : in STD_LOGIC; + AddressToJump : in STD_LOGIC_VECTOR (2 downto 0); + Adder_3bit_out : in STD_LOGIC_VECTOR (2 downto 0); + ToNextProgramCounter : out STD_LOGIC_VECTOR (2 downto 0)); +end Mux_2way_3bit; + +architecture Behavioral of Mux_2way_3bit is + +begin + +ToNextProgramCounter<=AddressToJump WHEN (JumpFlag='1') ELSE Adder_3bit_out; + +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd b/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd new file mode 100644 index 0000000..3626c48 --- /dev/null +++ b/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd @@ -0,0 +1,49 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 03:21:23 PM +-- Design Name: +-- Module Name: Mux_2way_3bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Mux_2way_4bit is + Port ( LoadSelect : in STD_LOGIC; + AddSubUnit4BitOut : in STD_LOGIC_VECTOR (3 downto 0); + ImmediateValue : in STD_LOGIC_VECTOR (3 downto 0); + -- enable signal + EN : in STD_LOGIC; + -- output + valueToRegisters : out STD_LOGIC_VECTOR (3 downto 0)); +end Mux_2way_4bit; + +architecture Behavioral of Mux_2way_4bit is +begin + +valueToRegisters <= AddSubUnit4BitOut WHEN (LoadSelect='1') ELSE ImmediateValue; + +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Mux_8way_4bit.vhd b/LAB10.srcs/sources_1/new/Mux_8way_4bit.vhd index 18a07ec..b25d147 100644 --- a/LAB10.srcs/sources_1/new/Mux_8way_4bit.vhd +++ b/LAB10.srcs/sources_1/new/Mux_8way_4bit.vhd @@ -31,41 +31,104 @@ use IEEE.STD_LOGIC_1164.ALL; --library UNISIM; --use UNISIM.VComponents.all; -entity Mux_8way_4bit is - Port ( S : in STD_LOGIC_VECTOR (2 downto 0); - D : in STD_LOGIC_VECTOR (7 downto 0); +entity Mux_8way_4bit is + +-- RegSel will select the register from D1 to D8 it's 3 bit signal + Port ( RegSel : in STD_LOGIC_VECTOR (2 downto 0); + + -- 8 registers + R0 : in STD_LOGIC_VECTOR (3 downto 0); + R1 : in STD_LOGIC_VECTOR (3 downto 0); + R2 : in STD_LOGIC_VECTOR (3 downto 0); + R3 : in STD_LOGIC_VECTOR (3 downto 0); + R4 : in STD_LOGIC_VECTOR (3 downto 0); + R5 : in STD_LOGIC_VECTOR (3 downto 0); + R6 : in STD_LOGIC_VECTOR (3 downto 0); + R7 : in STD_LOGIC_VECTOR (3 downto 0); + + -- enable signal EN : in STD_LOGIC; - Y : out STD_LOGIC); + + -- output signal + Output : out std_logic_vector (3 downto 0)); end Mux_8way_4bit; architecture Behavioral of Mux_8way_4bit is - component Decoder_3_to_8 - Port(I: in STD_LOGIC_VECTOR; - EN: in STD_LOGIC; - Y: out STD_LOGIC_VECTOR - ); - - - end component; - signal DY : STD_LOGIC_VECTOR (7 downto 0); + +--adding decoder +component Decoder_3_to_8 +port ( I : in STD_LOGIC_VECTOR (2 downto 0); + Y : out STD_LOGIC_VECTOR (7 downto 0); + EN : in STD_LOGIC); +end component; + +--adding tri state buffer +component quad_tri_state_buffer +Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + + +SIGNAL common_bus : std_logic_vector (3 downto 0); +SIGNAL RegSel_var : std_logic_vector(7 downto 0); + + begin - Decoder_3_to_8_0 : Decoder_3_to_8 - PORT MAP ( - I=>S, - EN => EN, - Y => DY - ); - - Y <= EN AND ((D(0) AND DY(0)) - OR (D(1) AND DY(1)) - OR (D(2) AND DY(2)) - OR (D(3) AND DY(3)) - OR (D(4) AND DY(4)) - OR (D(5) AND DY(5)) - OR (D(6) AND DY(6)) - OR (D(7) AND DY(7))); - - - - -end Behavioral; + +Decoder_3_to_8_0 : Decoder_3_to_8 + port map ( + I(2 downto 0) => RegSel(2 downto 0), + EN => '1', + Y(7 downto 0) => RegSel_var(7 downto 0)); + +quad_tri_state_buffer_0 : quad_tri_state_buffer +port map( +EN => RegSel_var(0), +A => R0, +Y => common_bus); + +quad_tri_state_buffer_1 : quad_tri_state_buffer +port map( +EN => RegSel_var(1), +A => R1, +Y => common_bus); + +quad_tri_state_buffer_2 : quad_tri_state_buffer +port map( +EN => RegSel_var(2), +A => R2, +Y => common_bus); + +quad_tri_state_buffer_3 : quad_tri_state_buffer +port map( +EN => RegSel_var(3), +A => R3, +Y => common_bus); + +quad_tri_state_buffer_4 : quad_tri_state_buffer +port map( +EN => RegSel_var(4), +A => R4, +Y => common_bus); + +quad_tri_state_buffer_5 : quad_tri_state_buffer +port map( +EN => RegSel_var(5), +A => R5, +Y => common_bus); + +quad_tri_state_buffer_6 : quad_tri_state_buffer +port map( +EN => RegSel_var(6), +A => R6, +Y => common_bus); + +quad_tri_state_buffer_7 : quad_tri_state_buffer +port map( +EN => RegSel_var(7), +A => R7, +Y => common_bus); +Output <= common_bus; + +end Behavioral; \ No newline at end of file diff --git a/LAB10.srcs/sources_1/new/Processor.vhd b/LAB10.srcs/sources_1/new/Processor.vhd new file mode 100644 index 0000000..2d4e15c --- /dev/null +++ b/LAB10.srcs/sources_1/new/Processor.vhd @@ -0,0 +1,382 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/26/2022 01:50:17 AM +-- Design Name: +-- Module Name: Processor - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Processor is + Port ( Clk_In : in STD_LOGIC; + Reset : in STD_LOGIC; + OverFlow : out std_logic; + Zero : out std_logic; + S_7Seg_out: out std_logic_vector(6 downto 0); + R7_out: out std_logic_vector(3 downto 0); + anode_out: out std_logic_vector(3 downto 0)); + +end Processor; + +architecture Behavioral of Processor is + +component R7_7_seg + Port ( + R7 : in std_logic_vector (3 downto 0); + S_7Seg : out std_logic_vector (6 downto 0); + anode : out std_logic_vector (3 downto 0) + ); +end component; + +component Register_bank + Port ( + Clk: in STD_LOGIC; + Reg_en : in std_logic_vector (2 downto 0); + D : in std_logic_vector (3 downto 0); + -- 8 registers + R0 : out STD_LOGIC_VECTOR (3 downto 0); + R1 : out STD_LOGIC_VECTOR (3 downto 0); + R2 : out STD_LOGIC_VECTOR (3 downto 0); + R3 : out STD_LOGIC_VECTOR (3 downto 0); + R4 : out STD_LOGIC_VECTOR (3 downto 0); + R5 : out STD_LOGIC_VECTOR (3 downto 0); + R6 : out STD_LOGIC_VECTOR (3 downto 0); + R7 : out STD_LOGIC_VECTOR (3 downto 0); + Reset : in STD_LOGIC + ); +end component; + + +component Mux_2way_3bit is + Port ( JumpFlag : in STD_LOGIC; + EN : in STD_LOGIC; + AddressToJump : in STD_LOGIC_VECTOR (2 downto 0); + Adder_3bit_out : in STD_LOGIC_VECTOR (2 downto 0); + ToNextProgramCounter : out STD_LOGIC_VECTOR (2 downto 0)); +end component; + + + +component Mux_2way_4bit is + Port ( LoadSelect : in STD_LOGIC; + AddSubUnit4BitOut : in STD_LOGIC_VECTOR (3 downto 0); + ImmediateValue : in STD_LOGIC_VECTOR (3 downto 0); + -- enable signal + EN : in STD_LOGIC; + -- output + valueToRegisters : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + +component Mux_8way_4bit is + +-- RegSel will select the register from D1 to D8 it's 3 bit signal + Port ( RegSel : in STD_LOGIC_VECTOR (2 downto 0); + + -- 8 registers + R0 : in STD_LOGIC_VECTOR (3 downto 0); + R1 : in STD_LOGIC_VECTOR (3 downto 0); + R2 : in STD_LOGIC_VECTOR (3 downto 0); + R3 : in STD_LOGIC_VECTOR (3 downto 0); + R4 : in STD_LOGIC_VECTOR (3 downto 0); + R5 : in STD_LOGIC_VECTOR (3 downto 0); + R6 : in STD_LOGIC_VECTOR (3 downto 0); + R7 : in STD_LOGIC_VECTOR (3 downto 0); + + -- enable signal + EN : in STD_LOGIC; + + -- output signal + Output : out std_logic_vector (3 downto 0)); +end component; + +component AddSubUnitBit_4 is + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end component; + +component Instruction_Decoder is + Port ( Instruction_Bus : in STD_LOGIC_VECTOR (11 downto 0); + Reg_Check_for_Jump : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : out STD_LOGIC_VECTOR (2 downto 0); + Load_Select : out STD_LOGIC; + Immediate_value : out STD_LOGIC_VECTOR (3 downto 0); + Register_select_01 : out STD_LOGIC_VECTOR (2 downto 0); + Register_select_02 : out STD_LOGIC_VECTOR (2 downto 0); + ADD_SUB_Select : out STD_LOGIC; + Jump_Flag : out STD_LOGIC; + Address_to_jump : out STD_LOGIC_VECTOR (2 downto 0)); +end component; + +component Program_ROM + Port ( Memory_Select : in STD_LOGIC_VECTOR (2 downto 0); + Instruction_Bus : out STD_LOGIC_VECTOR (11 downto 0)); +end component; + +component AdderBit_3 is + Port ( PreviousAddressPC : in STD_LOGIC_VECTOR (2 downto 0); + NextAddressPC : out STD_LOGIC_VECTOR (2 downto 0); + C_OUT : out STD_LOGIC); +end component; + + +component Program_counter is + Port ( Mux_2way3_bit_out : in STD_LOGIC_VECTOR (2 downto 0); + En : in STD_LOGIC; + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + MemorySelect : out STD_LOGIC_VECTOR (2 downto 0)); +end component; + +--slow clock added +component Slow_Clk is + Port ( Clk_in : in STD_LOGIC; + Clk_out : out STD_LOGIC); +end component; + + +--clock signals added +signal Clk_slow:STD_LOGIC; +signal Clk: STD_LOGIC; +--register bank signals +signal Reg_en : std_logic_vector (2 downto 0); + + + + signal LoadSelect : STD_LOGIC; + signal AddSubUnit4BitOut : STD_LOGIC_VECTOR (3 downto 0); + signal ImmediateValue : STD_LOGIC_VECTOR (3 downto 0); + -- enable signal + signal EN : STD_LOGIC; +-- output + signal valueToRegisters: STD_LOGIC_VECTOR (3 downto 0); + + + + + + + + -- 8 registers + signal R0 : STD_LOGIC_VECTOR (3 downto 0); + signal R1 : STD_LOGIC_VECTOR (3 downto 0); + signal R2 : STD_LOGIC_VECTOR (3 downto 0); + signal R3 : STD_LOGIC_VECTOR (3 downto 0); + signal R4 : STD_LOGIC_VECTOR (3 downto 0); + signal R5 : STD_LOGIC_VECTOR (3 downto 0); + signal R6 : STD_LOGIC_VECTOR (3 downto 0); + signal R7 : STD_LOGIC_VECTOR (3 downto 0); + + + + -- output signal + signal Output: std_logic_vector (3 downto 0); + + + + signal A : STD_LOGIC_VECTOR (3 downto 0); + signal B : STD_LOGIC_VECTOR (3 downto 0); + signal AddSub_Select : STD_LOGIC; + + + + signal Instruction_Bus : STD_LOGIC_VECTOR (11 downto 0); + signal Reg_Check_for_Jump : STD_LOGIC_VECTOR (3 downto 0); + signal Reg_Enable: STD_LOGIC_VECTOR (2 downto 0); + signal Load_Select: STD_LOGIC; + signal Immediate_value: STD_LOGIC_VECTOR (3 downto 0); + signal Register_select_01: STD_LOGIC_VECTOR (2 downto 0); + signal Register_select_02: STD_LOGIC_VECTOR (2 downto 0); + signal ADD_SUB_Select: STD_LOGIC; + signal Jump_Flag: STD_LOGIC; + signal Address_to_jump: STD_LOGIC_VECTOR (2 downto 0); + + + + signal Memory_Select : STD_LOGIC_VECTOR (2 downto 0):="000"; + + + signal PreviousAddressPC : STD_LOGIC_VECTOR (2 downto 0); + signal NextAddressPC: STD_LOGIC_VECTOR (2 downto 0); + signal C_OUT: STD_LOGIC; + + + + + signal Mux_2way3_bit_out : STD_LOGIC_VECTOR (2 downto 0); + signal MemorySelect: STD_LOGIC_VECTOR (2 downto 0); + + signal JumpFlag : STD_LOGIC; + signal AddressToJump : STD_LOGIC_VECTOR (2 downto 0); + signal Adder_3bit_out : STD_LOGIC_VECTOR (2 downto 0); + signal ToNextProgramCounter : STD_LOGIC_VECTOR (2 downto 0); + + + +begin + Slow_Clk0:Slow_Clk +PORT MAP( + Clk_in=>Clk_In, + Clk_out=>Clk); + + Register_bank0: Register_bank + Port MAP ( + Clk=>Clk, + Reg_en =>Reg_Enable, + D =>valueToRegisters, + Reset=>Reset, + R0=>R0, + R1=>R1, + R2=>R2, + R3=>R3, + R4=>R4, + R5=>R5, + R6=>R6, + R7=>R7 + ); + + + + Mux_2way_3bit0: Mux_2way_3bit + Port MAP( JumpFlag =>Jump_Flag, + EN =>EN, + AddressToJump =>Address_to_jump, + Adder_3bit_out =>NextAddressPC, + ToNextProgramCounter =>ToNextProgramCounter); + + + + + Mux_2way_4bit0: Mux_2way_4bit + Port MAP(LoadSelect =>Load_Select, + AddSubUnit4BitOut =>AddSubUnit4BitOut, + ImmediateValue =>Immediate_value, + -- enable signal + EN =>EN, + -- output + valueToRegisters =>valueToRegisters); + + Mux_8way_4bit1: Mux_8way_4bit + + -- RegSel will select the register from D1 to D8 it's 3 bit signal + Port MAP(RegSel =>Register_select_01, + + -- 8 registers + R0 =>R0, + R1 =>R1, + R2 =>R2, + R3 =>R3, + R4 =>R4, + R5 =>R5, + R6 =>R6, + R7 =>R7, + + -- enable signal + EN =>EN, + + -- output signal - wam paththe input eka - register check for jump + Output =>A); + + Mux_8way_4bit2: Mux_8way_4bit + + -- RegSel will select the register from D1 to D8 it's 3 bit signal + Port MAP(RegSel =>Register_select_02, + + -- 8 registers + R0 =>R0, + R1 =>R1, + R2 =>R2, + R3 =>R3, + R4 =>R4, + R5 =>R5, + R6 =>R6, + R7 =>R7, + + -- enable signal + EN =>EN, + + -- output signal dakune mux input + Output =>B); + + + AddSubUnitBit_40: AddSubUnitBit_4 + Port MAP( + --wam paththe input eka - register check for jump + A =>A, + --dakune mux input eka - + B =>B, + AddSub_Select =>ADD_SUB_Select, + S =>AddSubUnit4BitOut , + Overflow =>Overflow, + Zero =>Zero); + + + Instruction_Decoder0: Instruction_Decoder + Port MAP(Instruction_Bus =>Instruction_Bus, + Reg_Check_for_Jump =>B, + Reg_Enable =>Reg_Enable, + Load_Select =>Load_Select, + Immediate_value =>Immediate_value, + Register_select_01 =>Register_select_01, + Register_select_02 =>Register_select_02, + ADD_SUB_Select =>ADD_SUB_Select, + Jump_Flag =>Jump_Flag, + Address_to_jump =>Address_to_jump); + + + Program_ROM0: Program_ROM + Port MAP(Memory_Select =>MemorySelect, + Instruction_Bus =>Instruction_Bus); + + + AdderBit_30: AdderBit_3 + Port MAP(PreviousAddressPC =>MemorySelect, + NextAddressPC =>NextAddressPC, + C_OUT =>C_OUT); + + + + Program_counter0: Program_counter + Port MAP(Mux_2way3_bit_out =>ToNextProgramCounter, + En =>En, + Reset =>Reset, + Clk =>Clk, + MemorySelect =>MemorySelect); + + R7_7_seg_0: R7_7_seg + Port map( + R7=>R7, + S_7Seg=>S_7Seg_out, + anode=>anode_out + ); + + EN<='1'; + R7_out<=R7; +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Program_ROM.vhd b/LAB10.srcs/sources_1/new/Program_ROM.vhd new file mode 100644 index 0000000..f38d81b --- /dev/null +++ b/LAB10.srcs/sources_1/new/Program_ROM.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 02:41:04 PM +-- Design Name: +-- Module Name: Program_ROM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Program_ROM is + Port ( Memory_Select : in STD_LOGIC_VECTOR (2 downto 0); + Instruction_Bus : out STD_LOGIC_VECTOR (11 downto 0)); +end Program_ROM; + +architecture Behavioral of Program_ROM is +type rom_type is array (0 to 7) of std_logic_vector(11 downto 0); +signal sevenSegment_ROM : rom_type := ( + "100010001010", -- 0 + "100100000001", -- 1 + "010100000000", -- 2 + "000010100000", -- 3 + "110010000111", -- 4 + "110000000011", -- 5 + "111111111111", -- 6 + "111111111111" -- 7 + -- ,"111111111111" -- 7 + ); + +begin + +Instruction_Bus <= sevenSegment_ROM(to_integer(unsigned(Memory_Select))); + + + +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Program_counter.vhd b/LAB10.srcs/sources_1/new/Program_counter.vhd new file mode 100644 index 0000000..802f374 --- /dev/null +++ b/LAB10.srcs/sources_1/new/Program_counter.vhd @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/16/2022 02:34:25 PM +-- Design Name: +-- Module Name: Reg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Program_counter is + Port ( Mux_2way3_bit_out : in STD_LOGIC_VECTOR (2 downto 0); + En : in STD_LOGIC; + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + MemorySelect : out STD_LOGIC_VECTOR (2 downto 0)); +end Program_counter; + +architecture Behavioral of Program_counter is + +begin + process(Clk) + begin + if (rising_edge(Clk)) then -- respond when clock rises + if (Reset = '1') then -- reset the D flip flop + MemorySelect <= "000"; + else + if (En = '1') then -- Enable should be set + MemorySelect <= Mux_2way3_bit_out; + end if; + end if; + + end if; + end process; +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/R7_7_seg.vhd b/LAB10.srcs/sources_1/new/R7_7_seg.vhd new file mode 100644 index 0000000..3d8bb94 --- /dev/null +++ b/LAB10.srcs/sources_1/new/R7_7_seg.vhd @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/27/2022 12:03:11 AM +-- Design Name: +-- Module Name: R7_7_seg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity R7_7_seg is + Port ( + R7 : in std_logic_vector (3 downto 0); + S_7Seg : out std_logic_vector (6 downto 0); + anode : out std_logic_vector (3 downto 0) + ); +end R7_7_seg; + +architecture Behavioral of R7_7_seg is + +component LUT_16_7 + port( + address : in STD_LOGIC_VECTOR (3 downto 0); + data : out STD_LOGIC_VECTOR (6 downto 0) + ); +end component; + +begin +LUT_16_7_0 : LUT_16_7 +port map( + address=>R7, + data=>S_7Seg +); +anode<="1110"; +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Reg_Bank.vhd b/LAB10.srcs/sources_1/new/Reg_Bank.vhd new file mode 100644 index 0000000..e76841d --- /dev/null +++ b/LAB10.srcs/sources_1/new/Reg_Bank.vhd @@ -0,0 +1,137 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 10:07:37 AM +-- Design Name: +-- Module Name: Reg_Bank - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg_Bank is + Port ( Clk : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Reg_0_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_1_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_2_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_3_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_4_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_5_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_6_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_7_out : out STD_LOGIC_VECTOR (3 downto 0) + ); +end Reg_Bank; + +architecture Behavioral of Reg_Bank is +component Reg + Port ( D : in STD_LOGIC_VECTOR (3 downto 0); + En : in STD_LOGIC; + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + +component Decoder_3_to_8 + Port ( I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0)); +end component; +signal R_Y : STD_LOGIC_VECTOR (7 downto 0); +begin + Decoder_3_to_8_0 : Decoder_3_to_8 + PORT MAP ( + I=>Reg_Enable, + EN => '1', + Y => R_Y + ); + Register_0 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(0), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_0_out + ); + Register_1 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(1), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_1_out + ); + Register_2 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(2), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_2_out + ); + Register_3 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(3), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_3_out + ); + Register_4 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(4), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_4_out + ); + Register_5 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(5), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_5_out + ); + Register_6 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(6), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_6_out + ); + Register_7 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(7), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_7_out + ); + +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd b/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd new file mode 100644 index 0000000..27c2412 --- /dev/null +++ b/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd @@ -0,0 +1,45 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/25/2022 06:24:12 PM +-- Design Name: +-- Module Name: quad_tri_state_buffer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity quad_tri_state_buffer is + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end quad_tri_state_buffer; + +architecture Behavioral of quad_tri_state_buffer is + +begin +Y <= A WHEN EN='1' ELSE "ZZZZ"; + +end Behavioral; diff --git a/LAB10.xpr b/LAB10.xpr index ebb9246..360861a 100644 --- a/LAB10.xpr +++ b/LAB10.xpr @@ -3,7 +3,7 @@ - + diff --git a/TB_Processor_behav.wcfg b/TB_Processor_behav.wcfg new file mode 100644 index 0000000..1dcaf2d --- /dev/null +++ b/TB_Processor_behav.wcfg @@ -0,0 +1,176 @@ + + + + + + + + + + + + + + + + + + + + + + + Clk + Clk + + + Reset + Reset + + + Overflow + Overflow + + + Zero + Zero + + + Clk_in + Clk_in + + + Clk_out + Clk_out + + + Instruction_Bus[11:0] + Instruction_Bus[11:0] + + + + MemorySelect[2:0] + MemorySelect[2:0] + + + R0[3:0] + R0[3:0] + + + R1[3:0] + R1[3:0] + + + R2[3:0] + R2[3:0] + + + R3[3:0] + R3[3:0] + + + R4[3:0] + R4[3:0] + + + R5[3:0] + R5[3:0] + + + R6[3:0] + R6[3:0] + + + R7[3:0] + R7[3:0] + + + A[3:0] + A[3:0] + + + B[3:0] + B[3:0] + + + Output[3:0] + Output[3:0] + + + Output[3:0] + Output[3:0] + + + Register_select_01[2:0] + Register_select_01[2:0] + + + Register_select_02[2:0] + Register_select_02[2:0] + + + A[3:0] + A[3:0] + + + B[3:0] + B[3:0] + + + AddSub_Select + AddSub_Select + + + S[3:0] + S[3:0] + + + Overflow + Overflow + + + Zero + Zero + + + FA0_C + FA0_C + + + FA1_C + FA1_C + + + FA2_C + FA2_C + + + Bi[3:0] + Bi[3:0] + + + Si[3:0] + Si[3:0] + + + AddSub_Select + AddSub_Select + + + S[3:0] + S[3:0] + + + LoadSelect + LoadSelect + + + S_7Seg[6:0] + S_7Seg[6:0] + + + + S_7Seg_out[6:0] + S_7Seg_out[6:0] + + diff --git a/jump/Decoder_2_to_4.vhd b/jump/Decoder_2_to_4.vhd new file mode 100644 index 0000000..d229bb6 --- /dev/null +++ b/jump/Decoder_2_to_4.vhd @@ -0,0 +1,48 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10.06.2022 01:31:28 +-- Design Name: +-- Module Name: Decoder_2_to_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Decoder_2_to_4 is + Port ( I : in STD_LOGIC_VECTOR (1 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (3 downto 0)); +end Decoder_2_to_4; + +architecture Behavioral of Decoder_2_to_4 is + +begin +Y(0)<= NOT(I(0)) AND NOT(I(1)) AND EN; +Y(1)<= I(0) AND NOT(I(1)) AND EN; +Y(2)<= NOT(I(0)) AND I(1) AND EN; +Y(3)<= I(0) AND I(1) AND EN; + +end Behavioral; diff --git a/jump/Decoder_3_to_8.vhd b/jump/Decoder_3_to_8.vhd new file mode 100644 index 0000000..7bf0c52 --- /dev/null +++ b/jump/Decoder_3_to_8.vhd @@ -0,0 +1,72 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/02/2022 02:20:39 PM +-- Design Name: +-- Module Name: Decoder_3_to_8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Decoder_3_to_8 is + Port ( I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0)); +end Decoder_3_to_8; + +architecture Behavioral of Decoder_3_to_8 is + component Decoder_2_to_4 + PORT( + I: in STD_LOGIC_VECTOR; + EN: in STD_LOGIC; + Y: out STD_LOGIC_VECTOR + ); + end component; + signal EN0,EN1,I0,I1,I2 : STD_LOGIC; + --signal Y0,Y1 : STD_LOGIC_VECTOR (3 downto 0); + +begin +Decoder_2_to_4_0 :Decoder_2_to_4 + PORT MAP( + I(0) => I0, + I(1) => I1, + EN => EN0, + Y => Y(3 downto 0) + ); +Decoder_2_to_4_1 :Decoder_2_to_4 + PORT MAP( + I(0) => I0, + I(1)=> i1, + en => en1, + y => y(7 DOWNTO 4)); + + I0 <= I(0); + I1 <= I(1); + EN0 <= not(I(2)) AND EN; + EN1 <= I(2)AND EN; + + +end Behavioral; \ No newline at end of file diff --git a/vivado.jou b/vivado.jou new file mode 100644 index 0000000..532194f --- /dev/null +++ b/vivado.jou @@ -0,0 +1,21 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed Jul 27 00:01:08 2022 +# Process ID: 62920 +# Current directory: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent54044 C:\Users\dilsh\LAB10_New_New\LAB10_Dilshan_New\LAB10\LAB10.xpr +# Log file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/vivado.log +# Journal file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.xpr +update_compile_order -fileset sources_1 +add_files -norecurse -scan_for_includes C:/Users/dilsh/Lab7/Lab7.srcs/sources_1/new/LUT_16_7.vhd +import_files -norecurse C:/Users/dilsh/Lab7/Lab7.srcs/sources_1/new/LUT_16_7.vhd +update_compile_order -fileset sources_1 +close [ open C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd w ] +add_files C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 diff --git a/vivado.log b/vivado.log new file mode 100644 index 0000000..51e0b20 --- /dev/null +++ b/vivado.log @@ -0,0 +1,30 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Wed Jul 27 00:01:08 2022 +# Process ID: 62920 +# Current directory: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent54044 C:\Users\dilsh\LAB10_New_New\LAB10_Dilshan_New\LAB10\LAB10.xpr +# Log file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/vivado.log +# Journal file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.xpr +CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/dilsh/TB_Processor_behav.wcfg'. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 812.930 ; gain = 132.188 +update_compile_order -fileset sources_1 +add_files -norecurse -scan_for_includes C:/Users/dilsh/Lab7/Lab7.srcs/sources_1/new/LUT_16_7.vhd +import_files -norecurse C:/Users/dilsh/Lab7/Lab7.srcs/sources_1/new/LUT_16_7.vhd +update_compile_order -fileset sources_1 +close [ open C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd w ] +add_files C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/R7_7_seg.vhd +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 +exit +INFO: [Common 17-206] Exiting Vivado at Wed Jul 27 00:25:20 2022... diff --git a/vivado_14828.backup.jou b/vivado_14828.backup.jou new file mode 100644 index 0000000..f9eebdb --- /dev/null +++ b/vivado_14828.backup.jou @@ -0,0 +1,38 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:12:55 2022 +# Process ID: 14828 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19844 E:\Mora\Digital Design and Computer Organization\Vivado Lab Projects\LAB10\LAB10\LAB10.xpr +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/vivado.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.xpr} +update_compile_order -fileset sources_1 +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +set_property SOURCE_SET sources_1 [get_filesets sim_1] +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +file mkdir {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new} +close [ open {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd} w ] +add_files -fileset sim_1 {{E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd}} +update_compile_order -fileset sim_1 +# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. +set_property source_mgmt_mode None [current_project] +set_property top TB_AddSubUnitBit_4 [get_filesets sim_1] +set_property top_lib xil_defaultlib [get_filesets sim_1] +# Re-enabling previously disabled source management mode. +set_property source_mgmt_mode All [current_project] +update_compile_order -fileset sim_1 +launch_simulation +source TB_AddSubUnitBit_4.tcl +close_sim +launch_simulation +source TB_AddSubUnitBit_4.tcl +close_sim diff --git a/vivado_14828.backup.log b/vivado_14828.backup.log new file mode 100644 index 0000000..f0f9c6d --- /dev/null +++ b/vivado_14828.backup.log @@ -0,0 +1,168 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:12:55 2022 +# Process ID: 14828 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19844 E:\Mora\Digital Design and Computer Organization\Vivado Lab Projects\LAB10\LAB10\LAB10.xpr +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/vivado.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.xpr} +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +update_compile_order -fileset sources_1 +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +can't create directory "E:/Mora/Digital": file already exists +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +can't create directory "E:/Mora/Digital": file already exists +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +can't create directory "E:/Mora/Digital": file already exists +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +can't create directory "E:/Mora/Digital": file already exists +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +can't create directory "E:/Mora/Digital": file already exists +set_property SOURCE_SET sources_1 [get_filesets sim_1] +file mkdir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new +can't create directory "E:/Mora/Digital": file already exists +file mkdir {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new} +close [ open {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd} w ] +add_files -fileset sim_1 {{E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd}} +update_compile_order -fileset sim_1 +set_property top TB_AddSubUnitBit_4 [get_filesets sim_1] +set_property top_lib xil_defaultlib [get_filesets sim_1] +update_compile_order -fileset sim_1 +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_AddSubUnitBit_4' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity FA +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity HA +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/RCA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AddSubUnitBit_4 +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_addsubunitbit_4 +Built simulation snapshot TB_AddSubUnitBit_4_behav + +****** Webtalk v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source E:/Mora/Digital -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "E:/Mora/Digital" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 7 19:44:41 2022... +INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_AddSubUnitBit_4_behav -key {Behavioral:sim_1:Functional:TB_AddSubUnitBit_4} -tclbatch {TB_AddSubUnitBit_4.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_AddSubUnitBit_4.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_AddSubUnitBit_4_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 921.695 ; gain = 11.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation +INFO: [Vivado 12-5682] Launching behavioral simulation in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_AddSubUnitBit_4' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +"xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_addsubunitbit_4 +Built simulation snapshot TB_AddSubUnitBit_4_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_AddSubUnitBit_4_behav -key {Behavioral:sim_1:Functional:TB_AddSubUnitBit_4} -tclbatch {TB_AddSubUnitBit_4.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_AddSubUnitBit_4.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_AddSubUnitBit_4_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Thu Jul 7 19:57:01 2022... diff --git a/vivado_21044.backup.jou b/vivado_21044.backup.jou new file mode 100644 index 0000000..2136001 --- /dev/null +++ b/vivado_21044.backup.jou @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:10:06 2022 +# Process ID: 21044 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1644 E:\Mora\Digital Design and Computer Organization\Vivado Lab Projects\LAB10\LAB10\LAB10.xpr +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/vivado.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.xpr} +update_compile_order -fileset sources_1 +current_fileset -simset [ get_filesets sim_1 ] +delete_fileset sim_2 +file delete -force {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_2} diff --git a/vivado_21044.backup.log b/vivado_21044.backup.log new file mode 100644 index 0000000..b869465 --- /dev/null +++ b/vivado_21044.backup.log @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:10:06 2022 +# Process ID: 21044 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1644 E:\Mora\Digital Design and Computer Organization\Vivado Lab Projects\LAB10\LAB10\LAB10.xpr +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/vivado.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.xpr} +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +update_compile_order -fileset sources_1 +current_fileset -simset [ get_filesets sim_1 ] +delete_fileset sim_2 +file delete -force {E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_2} +exit +INFO: [Common 17-206] Exiting Vivado at Thu Jul 7 19:12:45 2022... diff --git a/vivado_22444.backup.jou b/vivado_22444.backup.jou new file mode 100644 index 0000000..c7c13bb Binary files /dev/null and b/vivado_22444.backup.jou differ diff --git a/vivado_22444.backup.log b/vivado_22444.backup.log new file mode 100644 index 0000000..c01fc33 --- /dev/null +++ b/vivado_22444.backup.log @@ -0,0 +1,394 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 12:09:33 2022 +# Process ID: 22444 +# Current directory: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent58428 C:\Users\dilsh\LAB10_New_New\LAB10_Dilshan_New\LAB10\LAB10.xpr +# Log file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/vivado.log +# Journal file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.xpr +CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/dilsh/TB_Processor_behav.wcfg'. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 804.512 ; gain = 119.574 +update_compile_order -fileset sources_1 +exit +INFO: [Common 17-206] Exiting Vivado alaunch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 906.352 ; gain = 12.594 +update_compile_order -fileset TB_Processor +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_ROM +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 920.562 ; gain = 0.000 +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/AddSubUnitBit_40}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/AddSubUnitBit_40/AddSub_Select}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/AddSubUnitBit_40/S}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Mux_2way_4bit0/LoadSelect}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Processor +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +update_compile_order -fileset TB_Processor +update_compile_order -fileset TB_Processor +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_ROM +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Tue Jul 26 12:28:44 2022... diff --git a/vivado_25568.backup.jou b/vivado_25568.backup.jou new file mode 100644 index 0000000..1f57c87 --- /dev/null +++ b/vivado_25568.backup.jou @@ -0,0 +1,137 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 23:46:37 2022 +# Process ID: 25568 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18532 C:\Users\mailt\Documents\A UoM\3. Computer Organization and Digital Design\Lab Sessions\LAB10_New_New\LAB10_Dilshan_New\LAB10\LAB10.xpr +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/vivado.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.xpr} +update_compile_order -fileset sources_1 +launch_simulation -simset TB_Instruction_decoder +launch_simulation -simset TB_Instruction_decoder +source TB_Instruction_Decoder.tcl +set_property SOURCE_SET {} [get_filesets TB_Instruction_decoder] +add_files -fileset TB_Instruction_decoder -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd}} +update_compile_order -fileset TB_Instruction_decoder +close_sim +launch_simulation -simset TB_Instruction_decoder +source TB_Instruction_Decoder.tcl +close_sim +launch_simulation -simset TB_Instruction_decoder +source TB_Instruction_Decoder.tcl +close_sim +launch_simulation -simset TB_Instruction_decoder +source TB_Instruction_Decoder.tcl +close_sim +launch_simulation -simset TB_Instruction_decoder +source TB_Instruction_Decoder.tcl +close_sim +launch_simulation -simset TB_Instruction_decoder +source TB_Instruction_Decoder.tcl +create_fileset -simset TB_Program_ROM +set_property SOURCE_SET {} [get_filesets TB_Program_ROM] +file mkdir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Program_ROM/new} +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd} w ] +add_files -fileset TB_Program_ROM {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd}} +update_compile_order -fileset TB_Program_ROM +update_compile_order -fileset TB_Program_ROM +set_property SOURCE_SET {} [get_filesets TB_Program_ROM] +add_files -fileset TB_Program_ROM -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd}} +current_fileset -simset [ get_filesets TB_Program_ROM ] +update_compile_order -fileset TB_Program_ROM +launch_simulation -simset TB_Program_ROM +source TB_Program_ROM.tcl +create_fileset -simset TB_AdderBit_3 +set_property SOURCE_SET {} [get_filesets TB_AdderBit_3] +file mkdir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_AdderBit_3/new} +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd} w ] +add_files -fileset TB_AdderBit_3 {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd}} +current_fileset -simset [ get_filesets TB_AdderBit_3 ] +update_compile_order -fileset TB_AdderBit_3 +update_compile_order -fileset TB_AdderBit_3 +set_property SOURCE_SET {} [get_filesets TB_AdderBit_3] +add_files -fileset TB_AdderBit_3 -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd}} +update_compile_order -fileset TB_AdderBit_3 +set_property SOURCE_SET {} [get_filesets TB_AdderBit_3] +add_files -fileset TB_AdderBit_3 -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd}} +update_compile_order -fileset TB_AdderBit_3 +launch_simulation -simset TB_AdderBit_3 +source TB_AdderBit_3.tcl +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd} w ] +add_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} +update_compile_order -fileset sources_1 +# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. +set_property source_mgmt_mode None [current_project] +set_property top Processor [current_fileset] +# Re-enabling previously disabled source management mode. +set_property source_mgmt_mode All [current_project] +update_compile_order -fileset sources_1 +add_files -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB05/LAB05.srcs/sources_1/new/Slow_Clk.vhd}} +import_files -force -norecurse {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB05/LAB05.srcs/sources_1/new/Slow_Clk.vhd}} +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 +create_fileset -simset TB_Processor +set_property SOURCE_SET {} [get_filesets TB_Processor] +file mkdir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new} +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd} w ] +add_files -fileset TB_Processor {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd}} +update_compile_order -fileset TB_Processor +current_fileset -simset [ get_filesets TB_Processor ] +update_compile_order -fileset TB_Processor +set_property SOURCE_SET {} [get_filesets TB_Processor] +add_files -fileset TB_Processor -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} +update_compile_order -fileset TB_Processor +update_files -from_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} -to_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} -filesets [get_filesets *] +set_property SOURCE_SET sources_1 [get_filesets TB_Processor] +add_files -fileset TB_Processor -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_8way_4bit.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Reg_Bank.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd}} +update_compile_order -fileset TB_Processor +set_property SOURCE_SET sources_1 [get_filesets TB_Register_Bank] +add_files -fileset TB_Register_Bank -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd}} +import_files -fileset TB_Register_Bank -norecurse {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd}} +update_compile_order -fileset TB_Register_Bank +update_compile_order -fileset TB_Register_Bank +update_files -from_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd}} -to_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10GW/LAB10.srcs/sim_1/Reg_Bank_Sim.vhd}} -filesets [get_filesets *] +# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. +set_property source_mgmt_mode None [current_project] +set_property top Reg_Bank_Sim [get_filesets TB_Register_Bank] +set_property top_lib xil_defaultlib [get_filesets TB_Register_Bank] +# Re-enabling previously disabled source management mode. +set_property source_mgmt_mode All [current_project] +current_fileset -simset [ get_filesets TB_Register_Bank ] +update_compile_order -fileset TB_Register_Bank +launch_simulation -simset TB_Register_Bank +source Reg_Bank_Sim.tcl +current_fileset -simset [ get_filesets TB_Processor ] +launch_simulation -simset TB_Processor +update_compile_order -fileset TB_Processor +launch_simulation -simset TB_Processor +update_compile_order -fileset TB_Processor +launch_simulation -simset TB_Processor +source TB_Processor.tcl +update_compile_order -fileset TB_Processor +current_wave_config {Untitled 10} +add_wave {{/TB_Processor/UUT/R7}} +current_wave_config {Untitled 10} +add_wave {{/TB_Processor/UUT/Instruction_Bus}} +save_wave_config {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg} +add_files -fileset TB_Processor -norecurse {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg}} +set_property xsim.view {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg}} [get_filesets TB_Processor] +close_sim +launch_simulation -simset TB_Processor +open_wave_config {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg} +source TB_Processor.tcl +close_sim +current_sim simulation_9 +close_sim +current_sim simulation_8 +close_sim +current_sim simulation_7 +close_sim +close_sim diff --git a/vivado_25568.backup.log b/vivado_25568.backup.log new file mode 100644 index 0000000..a511d6e --- /dev/null +++ b/vivado_25568.backup.log @@ -0,0 +1,897 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 23:46:37 2022 +# Process ID: 25568 +# Current directory: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18532 C:\Users\mailt\Documents\A UoM\3. Computer Organization and Digital Design\Lab Sessions\LAB10_New_New\LAB10_Dilshan_New\LAB10\LAB10.xpr +# Log file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/vivado.log +# Journal file: C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.xpr} +INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. +Current project path is 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10' +INFO: [Project 1-313] Project file moved from 'C:/Users/Nadun kumarasinghe/Downloads/LAB10_Dilshan_New/LAB10' since last save. +CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10GW/LAB10.srcs/sim_1/Reg_Bank_Sim.vhd', nor could it be found using path 'C:/Users/Nadun kumarasinghe/Downloads/LAB10GW/LAB10.srcs/sim_1/Reg_Bank_Sim.vhd'. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx1/Vivado/2018.2/data/ip'. +open_project: Time (s): cpu = 00:00:37 ; elapsed = 00:00:20 . Memory (MB): peak = 913.844 ; gain = 164.246 +update_compile_order -fileset sources_1 +launch_simulation -simset TB_Instruction_decoder +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Instruction_decoder' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Instruction_Decoder' in fileset 'TB_Instruction_decoder'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Instruction_decoder'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +"xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Instruction_Decoder +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +ERROR: [VRFC 10-2335] case statement does not cover all choices. 'others' clause is needed [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd:54] +ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_instruction_decoder in library work failed. +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-99] Step results log file:'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.log' +ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim/elaborate.log' file for more information. +ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. +ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. +launch_simulation -simset TB_Instruction_decoder +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Instruction_decoder' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Instruction_Decoder' in fileset 'TB_Instruction_decoder'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Instruction_decoder'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +"xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-122] decoder_2_to_4 remains a black-box since it has no binding entity [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd:60] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_instruction_decoder +Built simulation snapshot TB_Instruction_Decoder_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Instruction_Decoder_behav -key {Behavioral:TB_Instruction_decoder:Functional:TB_Instruction_Decoder} -tclbatch {TB_Instruction_Decoder.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Instruction_Decoder.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Instruction_Decoder_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1042.555 ; gain = 13.043 +set_property SOURCE_SET {} [get_filesets TB_Instruction_decoder] +add_files -fileset TB_Instruction_decoder -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd}} +update_compile_order -fileset TB_Instruction_decoder +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Instruction_decoder +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Instruction_decoder' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Instruction_Decoder' in fileset 'TB_Instruction_decoder'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Instruction_decoder'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +"xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_instruction_decoder +Built simulation snapshot TB_Instruction_Decoder_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Instruction_Decoder_behav -key {Behavioral:TB_Instruction_decoder:Functional:TB_Instruction_Decoder} -tclbatch {TB_Instruction_Decoder.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Instruction_Decoder.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Instruction_Decoder_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1060.605 ; gain = 2.598 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Instruction_decoder +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Instruction_decoder' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Instruction_Decoder' in fileset 'TB_Instruction_decoder'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Instruction_decoder'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +"xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Instruction_Decoder +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_instruction_decoder +Built simulation snapshot TB_Instruction_Decoder_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Instruction_Decoder_behav -key {Behavioral:TB_Instruction_decoder:Functional:TB_Instruction_Decoder} -tclbatch {TB_Instruction_Decoder.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Instruction_Decoder.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Instruction_Decoder_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1065.348 ; gain = 0.594 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Instruction_decoder +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Instruction_decoder' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Instruction_Decoder' in fileset 'TB_Instruction_decoder'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Instruction_decoder'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +"xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Instruction_Decoder +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_instruction_decoder +Built simulation snapshot TB_Instruction_Decoder_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Instruction_Decoder_behav -key {Behavioral:TB_Instruction_decoder:Functional:TB_Instruction_Decoder} -tclbatch {TB_Instruction_Decoder.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Instruction_Decoder.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Instruction_Decoder_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1067.746 ; gain = 0.609 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Instruction_decoder +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Instruction_decoder' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Instruction_Decoder' in fileset 'TB_Instruction_decoder'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Instruction_decoder'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +"xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_instruction_decoder +Built simulation snapshot TB_Instruction_Decoder_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Instruction_Decoder_behav -key {Behavioral:TB_Instruction_decoder:Functional:TB_Instruction_Decoder} -tclbatch {TB_Instruction_Decoder.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Instruction_Decoder.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Instruction_Decoder_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1076.145 ; gain = 1.004 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Instruction_decoder +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Instruction_decoder' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Instruction_Decoder' in fileset 'TB_Instruction_decoder'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Instruction_decoder'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +"xvhdl --incr --relax -prj TB_Instruction_Decoder_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Instruction_Decoder_behav xil_defaultlib.TB_Instruction_Decoder -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_instruction_decoder +Built simulation snapshot TB_Instruction_Decoder_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Instruction_decoder/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Instruction_Decoder_behav -key {Behavioral:TB_Instruction_decoder:Functional:TB_Instruction_Decoder} -tclbatch {TB_Instruction_Decoder.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Instruction_Decoder.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Instruction_Decoder_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1080.805 ; gain = 0.000 +create_fileset -simset TB_Program_ROM +set_property SOURCE_SET {} [get_filesets TB_Program_ROM] +file mkdir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Program_ROM/new} +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd} w ] +add_files -fileset TB_Program_ROM {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd}} +update_compile_order -fileset TB_Program_ROM +update_compile_order -fileset TB_Program_ROM +set_property SOURCE_SET {} [get_filesets TB_Program_ROM] +add_files -fileset TB_Program_ROM -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd}} +current_fileset -simset [ get_filesets TB_Program_ROM ] +update_compile_order -fileset TB_Program_ROM +launch_simulation -simset TB_Program_ROM +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Program_ROM' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Program_ROM' in fileset 'TB_Program_ROM'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Program_ROM'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim' +"xvhdl --incr --relax -prj TB_Program_ROM_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_ROM +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Program_ROM/new/TB_Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Program_ROM +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Program_ROM_behav xil_defaultlib.TB_Program_ROM -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_program_rom +Built simulation snapshot TB_Program_ROM_behav + +****** Webtalk v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 01:42:33 2022... +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Program_ROM/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Program_ROM_behav -key {Behavioral:TB_Program_ROM:Functional:TB_Program_ROM} -tclbatch {TB_Program_ROM.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Program_ROM.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Program_ROM_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1099.578 ; gain = 8.223 +create_fileset -simset TB_AdderBit_3 +set_property SOURCE_SET {} [get_filesets TB_AdderBit_3] +file mkdir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_AdderBit_3/new} +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd} w ] +add_files -fileset TB_AdderBit_3 {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd}} +current_fileset -simset [ get_filesets TB_AdderBit_3 ] +update_compile_order -fileset TB_AdderBit_3 +update_compile_order -fileset TB_AdderBit_3 +set_property SOURCE_SET {} [get_filesets TB_AdderBit_3] +add_files -fileset TB_AdderBit_3 -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd}} +update_compile_order -fileset TB_AdderBit_3 +set_property SOURCE_SET {} [get_filesets TB_AdderBit_3] +add_files -fileset TB_AdderBit_3 -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd}} +update_compile_order -fileset TB_AdderBit_3 +launch_simulation -simset TB_AdderBit_3 +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_AdderBit_3' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_AdderBit_3' in fileset 'TB_AdderBit_3'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_AdderBit_3'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim' +"xvhdl --incr --relax -prj TB_AdderBit_3_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AdderBit_3 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity FA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity HA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_AdderBit_3/new/TB_AdderBit_3.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AdderBit_3 +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AdderBit_3_behav xil_defaultlib.TB_AdderBit_3 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_adderbit_3 +Built simulation snapshot TB_AdderBit_3_behav + +****** Webtalk v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 01:47:03 2022... +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_AdderBit_3/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_AdderBit_3_behav -key {Behavioral:TB_AdderBit_3:Functional:TB_AdderBit_3} -tclbatch {TB_AdderBit_3.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_AdderBit_3.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_AdderBit_3_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:09 . Memory (MB): peak = 1112.160 ; gain = 7.953 +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd} w ] +add_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} +update_compile_order -fileset sources_1 +set_property top Processor [current_fileset] +update_compile_order -fileset sources_1 +add_files -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB05/LAB05.srcs/sources_1/new/Slow_Clk.vhd}} +import_files -force -norecurse {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB05/LAB05.srcs/sources_1/new/Slow_Clk.vhd}} +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 +update_compile_order -fileset sources_1 +create_fileset -simset TB_Processor +set_property SOURCE_SET {} [get_filesets TB_Processor] +file mkdir {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new} +close [ open {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd} w ] +add_files -fileset TB_Processor {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd}} +update_compile_order -fileset TB_Processor +current_fileset -simset [ get_filesets TB_Processor ] +update_compile_order -fileset TB_Processor +set_property SOURCE_SET {} [get_filesets TB_Processor] +add_files -fileset TB_Processor -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} +update_compile_order -fileset TB_Processor +update_files -from_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} -to_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd}} -filesets [get_filesets *] +ERROR: [Vivado 12-3481] Cannot replace a file with itself: 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd' +set_property SOURCE_SET sources_1 [get_filesets TB_Processor] +add_files -fileset TB_Processor -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_8way_4bit.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Program_ROM.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Reg_Bank.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Program_counter.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd} {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd}} +WARNING: [filemgmt 56-12] File 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd' cannot be added to the project because it already exists in the project, skipping this file +update_compile_order -fileset TB_Processor +set_property SOURCE_SET sources_1 [get_filesets TB_Register_Bank] +add_files -fileset TB_Register_Bank -norecurse -scan_for_includes {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd}} +import_files -fileset TB_Register_Bank -norecurse {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd}} +update_compile_order -fileset TB_Register_Bank +update_compile_order -fileset TB_Register_Bank +update_files -from_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd}} -to_files {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10GW/LAB10.srcs/sim_1/Reg_Bank_Sim.vhd}} -filesets [get_filesets *] +INFO: [filemgmt 20-762] Replacing file 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10GW/LAB10.srcs/sim_1/Reg_Bank_Sim.vhd' with file 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd'. +set_property top Reg_Bank_Sim [get_filesets TB_Register_Bank] +set_property top_lib xil_defaultlib [get_filesets TB_Register_Bank] +current_fileset -simset [ get_filesets TB_Register_Bank ] +update_compile_order -fileset TB_Register_Bank +launch_simulation -simset TB_Register_Bank +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Register_Bank' +INFO: [SIM-utils-54] Inspecting design source files for 'Reg_Bank_Sim' in fileset 'TB_Register_Bank'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Register_Bank'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim' +"xvhdl --incr --relax -prj Reg_Bank_Sim_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/imports/new/Reg_Bank.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg_Bank +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Register_Bank/Reg_Bank_Sim.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg_Bank_Sim +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Reg_Bank_Sim_behav xil_defaultlib.Reg_Bank_Sim -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg_Bank [reg_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.reg_bank_sim +Built simulation snapshot Reg_Bank_Sim_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Register_Bank/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "Reg_Bank_Sim_behav -key {Behavioral:TB_Register_Bank:Functional:Reg_Bank_Sim} -tclbatch {Reg_Bank_Sim.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source Reg_Bank_Sim.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'Reg_Bank_Sim_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1154.383 ; gain = 7.816 +current_fileset -simset [ get_filesets TB_Processor ] +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AddSubUnitBit_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AdderBit_3 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity FA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity HA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_3bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_8way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_8way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Processor +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_ROM +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_counter +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Register_bank +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Slow_Clk +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity quad_tri_state_buffer +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Processor +INFO: [USF-XSim-69] 'compile' step finished in '4' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:88] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:89] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:90] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:91] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:92] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:93] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:94] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:95] +ERROR: [VRFC 10-718] formal port does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch. [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd:101] +ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_processor in library work failed. +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-99] Step results log file:'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/elaborate.log' +ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/elaborate.log' file for more information. +ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. +launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1157.195 ; gain = 0.000 +ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. +update_compile_order -fileset TB_Processor +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_8way_4bit +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +ERROR: [VRFC 10-664] expression has 4 elements ; expected 3 [C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd:49] +ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_processor in library work failed. +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-99] Step results log file:'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/elaborate.log' +ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim/elaborate.log' file for more information. +ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. +ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. +update_compile_order -fileset TB_Processor +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_counter +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav + +****** Webtalk v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source C:/Users/mailt/Documents/A -notrace +invalid command name "Common" + while executing +"Common 17-165" + invoked from within +"ERROR: [Common 17-165] Too many positional options when parsing 'Sessions/LAB02/LAB02.hw/webtalk/labtool_webtalk.log', please type 'webtalk -help' for..." + (file "C:/Users/mailt/Documents/A" line 1) +INFO: [Common 17-206] Exiting Webtalk at Tue Jul 26 04:02:03 2022... +INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1169.066 ; gain = 8.672 +update_compile_order -fileset TB_Processor +current_wave_config {Untitled 10} +Untitled 10 +add_wave {{/TB_Processor/UUT/R7}} +current_wave_config {Untitled 10} +Untitled 10 +add_wave {{/TB_Processor/UUT/Instruction_Bus}} +save_wave_config {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg} +add_files -fileset TB_Processor -norecurse {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg}} +set_property xsim.view {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg}} [get_filesets TB_Processor] +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx1/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {{C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg}} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config {C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg} +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1173.617 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +close_sim: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1174.875 ; gain = 0.000 +current_sim simulation_9 +close_sim +INFO: [Simtcl 6-16] Simulation closed +close_sim: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1174.875 ; gain = 0.000 +current_sim simulation_8 +close_sim +INFO: [Simtcl 6-16] Simulation closed +close_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1174.875 ; gain = 0.000 +current_sim simulation_7 +close_sim +INFO: [Simtcl 6-16] Simulation closed +close_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1174.875 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Tue Jul 26 04:07:10 2022... diff --git a/vivado_35136.backup.jou b/vivado_35136.backup.jou new file mode 100644 index 0000000..661d6f4 --- /dev/null +++ b/vivado_35136.backup.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 16:21:45 2022 +# Process ID: 35136 +# Current directory: C:/Users/dilsh/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1684 C:\Users\dilsh\LAB10\LAB10.xpr +# Log file: C:/Users/dilsh/LAB10/vivado.log +# Journal file: C:/Users/dilsh/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/dilsh/LAB10/LAB10.xpr +update_compile_order -fileset sources_1 diff --git a/vivado_35136.backup.log b/vivado_35136.backup.log new file mode 100644 index 0000000..9851fd8 --- /dev/null +++ b/vivado_35136.backup.log @@ -0,0 +1,22 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Mon Jul 25 16:21:45 2022 +# Process ID: 35136 +# Current directory: C:/Users/dilsh/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1684 C:\Users\dilsh\LAB10\LAB10.xpr +# Log file: C:/Users/dilsh/LAB10/vivado.log +# Journal file: C:/Users/dilsh/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/dilsh/LAB10/LAB10.xpr +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 848.602 ; gain = 112.082 +update_compile_order -fileset sources_1 +exit +INFO: [Common 17-206] Exiting Vivado at Mon Jul 25 16:23:08 2022... diff --git a/vivado_56012.backup.jou b/vivado_56012.backup.jou new file mode 100644 index 0000000..ee5666e --- /dev/null +++ b/vivado_56012.backup.jou @@ -0,0 +1,88 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 10:36:17 2022 +# Process ID: 56012 +# Current directory: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9268 C:\Users\dilsh\LAB10_New_New\LAB10_Dilshan_New\LAB10\LAB10.xpr +# Log file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/vivado.log +# Journal file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.xpr +update_compile_order -fileset sources_1 +launch_simulation -simset TB_Processor +source TB_Processor.tcl +current_wave_config {Untitled 1} +add_wave {{/TB_Processor/UUT/Slow_Clk0/Clk_in}} +current_wave_config {Untitled 1} +add_wave {{/TB_Processor/UUT/Slow_Clk0/Clk_out}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +add_files -fileset TB_Processor -norecurse C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +set_property xsim.view {C:/Users/dilsh/TB_Processor_behav.wcfg C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} [get_filesets TB_Processor] +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Instruction_Decoder0/Instruction_Bus}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Program_counter0/MemorySelect}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R0}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R1}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R2}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R3}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R4}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R5}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R6}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/Register_bank0/R7}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/AddSubUnitBit_40/A}} +current_wave_config {TB_Processor_behav.wcfg} +add_wave {{/TB_Processor/UUT/AddSubUnitBit_40/B}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +launch_simulation -simset TB_Processor +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +close_sim diff --git a/vivado_56012.backup.log b/vivado_56012.backup.log new file mode 100644 index 0000000..6cfef22 --- /dev/null +++ b/vivado_56012.backup.log @@ -0,0 +1,694 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jul 26 10:36:17 2022 +# Process ID: 56012 +# Current directory: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9268 C:\Users\dilsh\LAB10_New_New\LAB10_Dilshan_New\LAB10\LAB10.xpr +# Log file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/vivado.log +# Journal file: C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10\vivado.jou +#----------------------------------------------------------- +start_gui +open_project C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.xpr +INFO: [Project 1-313] Project file moved from 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/LAB10_New_New/LAB10_Dilshan_New/LAB10' since last save. +CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/dilsh/TB_Processor_behav.wcfg', nor could it be found using path 'C:/Users/mailt/Documents/A UoM/3. Computer Organization and Digital Design/Lab Sessions/TB_Processor_behav.wcfg'. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 854.121 ; gain = 129.570 +update_compile_order -fileset sources_1 +exit +INFO: [Common 17-206] Exiting Vivado at Tue Jul 26 11:27:23 2022... +ehavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/sim_1/AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AddSubUnitBit_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/AdderBit_3.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity AdderBit_3 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_2_to_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_2_to_4 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Decoder_3_to_8.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Decoder_3_to_8 +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity FA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity HA +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Instruction_Decoder.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Instruction_Decoder +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2_to_1_3bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_3bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Mux_2way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_2way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Mux_8way_4bit.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Mux_8way_4bit +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Processor +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_ROM.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_ROM +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Program_counter.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Program_counter +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Reg.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Reg +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Register_bank.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Register_bank +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/imports/new/Slow_Clk.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Slow_Clk +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/quad_tri_state_buffer.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity quad_tri_state_buffer +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Processor +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 896.934 ; gain = 15.586 +current_wave_config {Untitled 1} +Untitled 1 +add_wave {{/TB_Processor/UUT/Slow_Clk0/Clk_in}} +current_wave_config {Untitled 1} +Untitled 1 +add_wave {{/TB_Processor/UUT/Slow_Clk0/Clk_out}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +add_files -fileset TB_Processor -norecurse C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +set_property xsim.view {C:/Users/dilsh/TB_Processor_behav.wcfg C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} [get_filesets TB_Processor] +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Processor +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Instruction_Decoder0/Instruction_Bus}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Program_counter0/MemorySelect}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Processor +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 935.379 ; gain = 0.000 +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/TB_Processor/new/TB_Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_Processor +INFO: [USF-XSim-69] 'compile' step finished in '2' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R0}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R1}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R2}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R3}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R4}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R5}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R6}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/Register_bank0/R7}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.srcs/sources_1/new/Processor.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity Processor +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture behavioral of entity xil_defaultlib.Slow_Clk [slow_clk_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_2_to_4 [decoder_2_to_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Decoder_3_to_8 [decoder_3_to_8_default] +Compiling architecture behavioral of entity xil_defaultlib.Reg [reg_default] +Compiling architecture behavioral of entity xil_defaultlib.Register_bank [register_bank_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_3bit [mux_2way_3bit_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_2way_4bit [mux_2way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.quad_tri_state_buffer [quad_tri_state_buffer_default] +Compiling architecture behavioral of entity xil_defaultlib.Mux_8way_4bit [mux_8way_4bit_default] +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.Instruction_Decoder [instruction_decoder_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_ROM [program_rom_default] +Compiling architecture behavioral of entity xil_defaultlib.AdderBit_3 [adderbit_3_default] +Compiling architecture behavioral of entity xil_defaultlib.Program_counter [program_counter_default] +Compiling architecture behavioral of entity xil_defaultlib.Processor [processor_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_processor +Built simulation snapshot TB_Processor_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/AddSubUnitBit_40/A}} +current_wave_config {TB_Processor_behav.wcfg} +TB_Processor_behav.wcfg +add_wave {{/TB_Processor/UUT/AddSubUnitBit_40/B}} +save_wave_config {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} +close_sim +INFO: [Simtcl 6-16] Simulation closed +launch_simulation -simset TB_Processor +INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [SIM-utils-51] Simulation object is 'TB_Processor' +INFO: [SIM-utils-54] Inspecting design source files for 'TB_Processor' in fileset 'TB_Processor'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'TB_Processor'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +"xvhdl --incr --relax -prj TB_Processor_vhdl.prj" +INFO: [USF-XSim-69] 'compile' step finished in '1' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Processor_behav xil_defaultlib.TB_Processor -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds +INFO: [USF-XSim-4] XSim::Simulate design +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/dilsh/TB_Processor_behav.wcfg +INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/LAB10.sim/TB_Processor/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "TB_Processor_behav -key {Behavioral:TB_Processor:Functional:TB_Processor} -tclbatch {TB_Processor.tcl} -view {C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Vivado Simulator 2018.2 +Time resolution is 1 ps +open_wave_config C:/Users/dilsh/LAB10_New_New/LAB10_Dilshan_New/LAB10/TB_Processor_behav.wcfg +source TB_Processor.tcl +# set curr_wave [current_wave_config] +# if { [string length $curr_wave] == 0 } { +# if { [llength [get_objects]] > 0} { +# add_wave / +# set_property needs_save false [current_wave_config] +# } else { +# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +# } +# } +# run 1000ns +INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_Processor_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for 1000ns +close_sim +INFO: [Simtcl 6-16] Simulation closed +exit +INFO: [Common 17-206] Exiting Vivado at Tue Jul 26 11:25:57 2022... diff --git a/vivado_pid21044.zip b/vivado_pid21044.zip new file mode 100644 index 0000000..fad18d0 Binary files /dev/null and b/vivado_pid21044.zip differ