diff --git a/LAB10.cache/wt/gui_handlers.wdf b/LAB10.cache/wt/gui_handlers.wdf index fb06efa..51b6035 100644 --- a/LAB10.cache/wt/gui_handlers.wdf +++ b/LAB10.cache/wt/gui_handlers.wdf @@ -1,18 +1,51 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3235:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626f61726463686f6f7365725f626f6172645f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f646566696e655f6d6f64756c65735f616e645f737065636966795f696f5f706f727473:313236:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3635:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:323635:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f7265706c6163655f74657874:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:38:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f666974:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f7265706c6163655f74657874:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3231:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6d616b655f6163746976655f73696d736574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f7265736574:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:38:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f7365727461626c655f7372635f63686f6f7365725f7461626c65:38:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:737263636f6e666c6963746469616c6f675f646f6e745f6f76657277726974655f6578697374696e675f66696c6573:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:32:00:00 -eof:3624100816 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f636f7079:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f7061737465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:3137:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f66696c65735f62656c6f775f746f5f746869735f73696d756c6174696f6e5f736574:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f616374697665:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f7365727461626c655f7372635f63686f6f7365725f7461626c65:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:737263636f6e666c6963746469616c6f675f646f6e745f6f76657277726974655f6578697374696e675f66696c6573:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:36:00:00 +eof:947203416 diff --git a/LAB10.cache/wt/java_command_handlers.wdf b/LAB10.cache/wt/java_command_handlers.wdf index b73281e..0a0316e 100644 --- a/LAB10.cache/wt/java_command_handlers.wdf +++ b/LAB10.cache/wt/java_command_handlers.wdf @@ -1,4 +1,10 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:38:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3231:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616b6561637469766573696d736574:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 -eof:265469477 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:31:00:00 +eof:3245377049 diff --git a/LAB10.cache/wt/project.wpc b/LAB10.cache/wt/project.wpc index 6888ede..a9e4162 100644 --- a/LAB10.cache/wt/project.wpc +++ b/LAB10.cache/wt/project.wpc @@ -1,3 +1,7 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:2 +<<<<<<< Updated upstream +6d6f64655f636f756e7465727c4755494d6f6465:6 +======= +6d6f64655f636f756e7465727c4755494d6f6465:11 +>>>>>>> Stashed changes eof: diff --git a/LAB10.cache/wt/synthesis.wdf b/LAB10.cache/wt/synthesis.wdf new file mode 100644 index 0000000..6fe35be --- /dev/null +++ b/LAB10.cache/wt/synthesis.wdf @@ -0,0 +1,36 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:72746c5f31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:5b7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +eof:4154258739 diff --git a/LAB10.cache/wt/webtalk_pa.xml b/LAB10.cache/wt/webtalk_pa.xml index fc79d2c..03ececa 100644 --- a/LAB10.cache/wt/webtalk_pa.xml +++ b/LAB10.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,31 +17,70 @@ This means code written to parse this file will need to be revisited each subseq - + + + + + + + - + + + + + + + + + - + + - - - + + + + + + + + + + + + + + + + + - - - - - - + + + + + + + + + + + + + + + + - + - +
diff --git a/LAB10.cache/wt/xsim.wdf b/LAB10.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/LAB10.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/LAB10.ip_user_files/README.txt b/LAB10.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/LAB10.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4.tcl b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_behav.wdb b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_behav.wdb new file mode 100644 index 0000000..0aa8866 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_behav.wdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj new file mode 100644 index 0000000..ccf7adc --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/TB_AddSubUnitBit_4_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../LAB10.srcs/sources_1/imports/new/FA.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/HA.vhd" \ +"../../../../LAB10.srcs/sources_1/imports/new/RCA.vhd" \ +"../../../../LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB10.sim/sim_1/behav/xsim/compile.bat b/LAB10.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..53d5280 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Thu Jul 07 19:54:00 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj" +call xvhdl --incr --relax -prj TB_AddSubUnitBit_4_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/sim_1/behav/xsim/compile.log b/LAB10.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..9399785 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 diff --git a/LAB10.sim/sim_1/behav/xsim/elaborate.bat b/LAB10.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..383b3d4 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Thu Jul 07 19:54:01 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/sim_1/behav/xsim/elaborate.log b/LAB10.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..a7625cf --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,17 @@ +Vivado Simulator 2018.2 +Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4 -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling architecture behavioral of entity xil_defaultlib.HA [ha_default] +Compiling architecture behavioral of entity xil_defaultlib.FA [fa_default] +Compiling architecture behavioral of entity xil_defaultlib.AddSubUnitBit_4 [addsubunitbit_4_default] +Compiling architecture behavioral of entity xil_defaultlib.tb_addsubunitbit_4 +Built simulation snapshot TB_AddSubUnitBit_4_behav diff --git a/LAB10.sim/sim_1/behav/xsim/simulate.bat b/LAB10.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..982f740 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2018.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Thu Jul 07 19:54:03 +0530 2022 +REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +REM +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim TB_AddSubUnitBit_4_behav -key {Behavioral:sim_1:Functional:TB_AddSubUnitBit_4} -tclbatch TB_AddSubUnitBit_4.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB10.sim/sim_1/behav/xsim/simulate.log b/LAB10.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..2cc3412 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2018.2 +Time resolution is 1 ps diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk.jou b/LAB10.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..3b745f8 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:53:59 2022 +# Process ID: 17808 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk.log b/LAB10.sim/sim_1/behav/xsim/webtalk.log new file mode 100644 index 0000000..4091392 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:53:59 2022 +# Process ID: 17808 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "E:/Mora/Digital" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 7 19:53:59 2022... diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.jou b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.jou new file mode 100644 index 0000000..6467dfc --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:44:41 2022 +# Process ID: 15304 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace diff --git a/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.log b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.log new file mode 100644 index 0000000..7d51715 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/webtalk_15304.backup.log @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Thu Jul 7 19:44:41 2022 +# Process ID: 15304 +# Current directory: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/Mora/Digital -notrace +invalid command name "%" + while executing +"% Total % Received % Xferd Average Speed Time Time Time Current" + (file "E:/Mora/Digital" line 1) +INFO: [Common 17-206] Exiting Webtalk at Thu Jul 7 19:44:41 2022... diff --git a/LAB10.sim/sim_1/behav/xsim/xelab.pb b/LAB10.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..3a141c3 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt new file mode 100644 index 0000000..44528b9 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "f330702f431647419194c50ab3747a93" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_AddSubUnitBit_4_behav" "xil_defaultlib.TB_AddSubUnitBit_4" -log "elaborate.log" diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..e7dbdf5 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c new file mode 100644 index 0000000..39b938a --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_53(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_51(char*, char *); +extern void execute_52(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_53, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_51, (funcp)execute_52, (funcp)execute_22, (funcp)execute_23, (funcp)execute_17, (funcp)execute_18, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc", (void **)funcTab, 12); + iki_vhdl_file_variable_register(dp + 8152); + iki_vhdl_file_variable_register(dp + 8208); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..819ad10 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..395ad4b --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1657203280 +1657203838 +5 +1 +f330702f431647419194c50ab3747a93 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..68a66eb --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Jul 7 19:56:58 2022" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "0d1c7977dd6d5955bcf230b289e9e973" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "f330702f431647419194c50ab3747a93" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 9 5900HS with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3294 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "33.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6292_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1821698081 -regid "" -xml E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.xml -html E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.html -wdm E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg new file mode 100644 index 0000000..a950127 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.dbg differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem new file mode 100644 index 0000000..fdde7c8 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.mem differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc new file mode 100644 index 0000000..7e35504 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.reloc differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx new file mode 100644 index 0000000..86d237b --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 7571415711912686436 , + ccp_crc : 0 , + cmdline : " -wto f330702f431647419194c50ab3747a93 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_AddSubUnitBit_4_behav xil_defaultlib.TB_AddSubUnitBit_4" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe\" \"xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_AddSubUnitBit_4_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti new file mode 100644 index 0000000..cc37966 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.rtti differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.svtype differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type new file mode 100644 index 0000000..d1ab5b3 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.type differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg new file mode 100644 index 0000000..861748e Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsim.xdbg differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini new file mode 100644 index 0000000..8d7c961 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=138 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=115 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=115 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimcrash.log b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe new file mode 100644 index 0000000..3455bdb Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log new file mode 100644 index 0000000..a2cfa6c --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/TB_AddSubUnitBit_4_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/TB_AddSubUnitBit_4_behav/xsimk.exe -simmode gui -wdb TB_AddSubUnitBit_4_behav.wdb -simrunnum 0 -socket 1999 +Design successfully loaded +Design Loading Memory Usage: 5808 KB (Peak: 5808 KB) +Design Loading CPU Usage: 0 ms +Simulation completed +Simulation Memory Usage: 6292 KB (Peak: 6292 KB) +Simulation CPU Usage: 0 ms diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb new file mode 100644 index 0000000..3617ce0 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/addsubunitbit_4.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb new file mode 100644 index 0000000..a47aa1c Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fa.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb new file mode 100644 index 0000000..1c57c6b Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ha.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb new file mode 100644 index 0000000..ed61afe Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_addsubunitbit_4.vdb differ diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..89d609f --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,8 @@ +0.6 +2018.2 +Jun 14 2018 +20:41:02 +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd,1657203834,vhdl,,,,tb_addsubunitbit_4,,,,,,,, +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/FA.vhd,1653841899,vhdl,,,,fa,,,,,,,, +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/HA.vhd,1653837756,vhdl,,,,ha,,,,,,,, +E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sources_1/imports/new/RCA.vhd,1657200684,vhdl,,,,addsubunitbit_4,,,,,,,, diff --git a/LAB10.sim/sim_1/behav/xsim/xsim.ini b/LAB10.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB10.sim/sim_1/behav/xsim/xvhdl.log b/LAB10.sim/sim_1/behav/xsim/xvhdl.log new file mode 100644 index 0000000..9399785 --- /dev/null +++ b/LAB10.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "E:/Mora/Digital Design and Computer Organization/Vivado Lab Projects/LAB10/LAB10/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd" into library xil_defaultlib +INFO: [VRFC 10-307] analyzing entity TB_AddSubUnitBit_4 diff --git a/LAB10.sim/sim_1/behav/xsim/xvhdl.pb b/LAB10.sim/sim_1/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..849bc25 Binary files /dev/null and b/LAB10.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/LAB10.srcs/sim_1/new/Reg_Bank_Sim.vhd b/LAB10.srcs/sim_1/new/Reg_Bank_Sim.vhd new file mode 100644 index 0000000..4d2e940 --- /dev/null +++ b/LAB10.srcs/sim_1/new/Reg_Bank_Sim.vhd @@ -0,0 +1,91 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 11:45:10 AM +-- Design Name: +-- Module Name: Reg_Bank_Sim - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg_Bank_Sim is +-- Port ( ); +end Reg_Bank_Sim; + +architecture Behavioral of Reg_Bank_Sim is +component Reg_Bank + Port ( Clk : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Reg_0_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_1_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_2_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_3_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_4_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_5_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_6_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_7_out : out STD_LOGIC_VECTOR (3 downto 0) + ); +end component; +signal Clk : STD_LOGIC:= '0'; +signal Reset : STD_LOGIC; +signal Data_in,Reg_0_out,Reg_1_out,Reg_2_out,Reg_3_out,Reg_4_out,Reg_5_out,Reg_6_out,Reg_7_out : STD_LOGIC_VECTOR (3 downto 0); +signal Reg_Enable : STD_LOGIC_VECTOR (2 downto 0); +begin + UUT :Reg_Bank + PORT MAP( + Clk=>Clk, + Data_in=>Data_in, + Reg_Enable=>Reg_Enable, + Reset=>Reset, + Reg_0_out=>Reg_0_out, + Reg_1_out=>Reg_1_out, + Reg_2_out=>Reg_2_out, + Reg_3_out=>Reg_3_out, + Reg_4_out=>Reg_4_out, + Reg_5_out=>Reg_5_out, + Reg_6_out=>Reg_6_out, + Reg_7_out=>Reg_7_out + ); + + process + begin + wait for 20ns; + Clk <= Not (Clk); + end process; + + process begin + Reset<='1'; + wait for 30ns; + Reset<='0'; + + Reg_Enable<="001"; + Data_in<="0111"; + + end process; + +end Behavioral; diff --git a/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd b/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd new file mode 100644 index 0000000..c87df43 --- /dev/null +++ b/LAB10.srcs/sim_1/new/TB_AddSubUnitBit_4.vhd @@ -0,0 +1,82 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/07/2022 07:13:45 PM +-- Design Name: +-- Module Name: TB_AddSubUnitBit_4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_AddSubUnitBit_4 is +-- Port ( ); +end TB_AddSubUnitBit_4; + +architecture Behavioral of TB_AddSubUnitBit_4 is +component AddSubUnitBit_4 + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); +end component; + signal A,B,S : STD_LOGIC_VECTOR (3 downto 0); + signal Overflow,Zero,AddSub_Select : STD_LOGIC:='0'; +begin +UUT: AddSubUnitBit_4 + PORT MAP( + A=>A, + B=>B, + S=>S, + Overflow=>Overflow, + Zero=>Zero, + AddSub_Select=>AddSub_Select + ); +process begin + + A<="0110"; + B<="1001"; + AddSub_Select<='0'; + WAIT FOR 100ns; + + A<="0110"; + B<="1001"; + AddSub_Select<='1'; + WAIT FOR 100ns; + + A<="1111"; + B<="0001"; + AddSub_Select<='0'; + WAIT FOR 100ns; + + A<="1111"; + B<="0001"; + AddSub_Select<='1'; + WAIT; + +end process; +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/RCA.vhd b/LAB10.srcs/sources_1/imports/new/RCA.vhd index 3fc9154..fb89bb8 100644 --- a/LAB10.srcs/sources_1/imports/new/RCA.vhd +++ b/LAB10.srcs/sources_1/imports/new/RCA.vhd @@ -32,20 +32,12 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity AddSubUnitBit_4 is - Port ( A0 : in STD_LOGIC; - A1 : in STD_LOGIC; - A2 : in STD_LOGIC; - A3 : in STD_LOGIC; - B0 : in STD_LOGIC; - B1 : in STD_LOGIC; - B2 : in STD_LOGIC; - B3 : in STD_LOGIC; - C_in : in STD_LOGIC; - S0 : out STD_LOGIC; - S1 : out STD_LOGIC; - S2 : out STD_LOGIC; - S3 : out STD_LOGIC; - C_out : out STD_LOGIC); + Port ( A : in STD_LOGIC_VECTOR (3 downto 0); + B : in STD_LOGIC_VECTOR (3 downto 0); + AddSub_Select : in STD_LOGIC; + S : out STD_LOGIC_VECTOR (3 downto 0); + Overflow : out STD_LOGIC; + Zero : out STD_LOGIC); end AddSubUnitBit_4; architecture Behavioral of AddSubUnitBit_4 is @@ -58,43 +50,51 @@ component FA end component; SIGNAL FA0_S, FA0_C,FA1_S, FA1_C,FA2_S, FA2_C:STD_LOGIC; +SIGNAL Bi : STD_LOGIC_VECTOR (3 downto 0); +SIGNAL Si : STD_LOGIC_VECTOR (3 downto 0); begin +Bi(0)<=(B(0) XOR AddSub_Select); +Bi(1)<=(B(1) XOR AddSub_Select); +Bi(2)<=(B(2) XOR AddSub_Select); +Bi(3)<=(B(3) XOR AddSub_Select); + FA_0 : FA PORT MAP ( - A=>A0, - B => B0, - C_in => '0', - S => S0, + A=>A(0), + B => Bi(0), + C_in => AddSub_Select, + S => Si(0), C_out=> FA0_C ); FA_1 : FA PORT MAP ( -A=>A1, -B => B1, -C_in => FA0_C, -S => S1, -C_out=> FA1_C -); + A=>A(1), + B => Bi(1), + C_in => FA0_C, + S => Si(1), + C_out=> FA1_C + ); FA_2 : FA PORT MAP ( -A=>A2, -B => B2, -C_in => FA1_C, -S => S2, -C_out=> FA2_C -); + A=>A(2), + B => Bi(2), + C_in => FA1_C, + S => Si(2), + C_out=> FA2_C + ); FA_3 : FA PORT MAP ( -A=>A3, -B => B3, -C_in => FA2_C, -S => S3, -C_out=> C_out -); - + A=>A(3), + B => Bi(3), + C_in => FA2_C, + S => Si(3), + C_out=> Overflow + ); +S<=Si; +Zero<= NOT(Si(0) OR Si(1) OR Si(2) OR Si(3)); end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/RCA_4.vhd b/LAB10.srcs/sources_1/imports/new/RCA_4.vhd new file mode 100644 index 0000000..2b4f23b --- /dev/null +++ b/LAB10.srcs/sources_1/imports/new/RCA_4.vhd @@ -0,0 +1,88 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09.06.2022 13:10:47 +-- Design Name: +-- Module Name: RCA - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +-- 3 bit adder + +entity RCA_3 is + Port ( PreviousAddressPC : in STD_LOGIC_VECTOR (2 downto 0); + C_IN : in STD_LOGIC; + NextAddressPC : out STD_LOGIC_VECTOR (2 downto 0); + C_OUT : out STD_LOGIC); +end RCA_3; + +architecture Behavioral of RCA_3 is + +component FA + port ( + A: in std_logic; + B: in std_logic; + C_in: in std_logic; + S: out std_logic; + C_out: out std_logic); +end component; + +SIGNAL FA0_C, FA1_C, FA2_C, FA3_C : std_logic; + + +begin + + FA_0 : FA + port map ( + A => PreviousAddressPC(0), + + -- B is 1 because we are adding 001 always + B => '1', + C_in => c_in, + S => NextAddressPC(0), + C_Out => FA0_C); + FA_1 : FA + port map ( + A => PreviousAddressPC(1), + -- B is 0 because we are adding 001 always + B => '0', + C_in => FA0_C, + S => NextAddressPC(1), + C_Out => FA1_C); + FA_2 : FA + port map ( + A => PreviousAddressPC(2), + -- B is 0 because we are adding 001 always + B => '0', + C_in => FA1_C, + S => NextAddressPC(2), + C_Out => FA2_C); + + + +end Behavioral; diff --git a/LAB10.srcs/sources_1/imports/new/Reg.vhd b/LAB10.srcs/sources_1/imports/new/Reg.vhd index 5289a27..ee55a31 100644 --- a/LAB10.srcs/sources_1/imports/new/Reg.vhd +++ b/LAB10.srcs/sources_1/imports/new/Reg.vhd @@ -34,6 +34,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity Reg is Port ( D : in STD_LOGIC_VECTOR (3 downto 0); En : in STD_LOGIC; + Reset : in STD_LOGIC; Clk : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end Reg; @@ -44,9 +45,14 @@ begin process(Clk) begin if (rising_edge(Clk)) then -- respond when clock rises - if (En = '1') then -- Enable should be set - Q <= D; - end if; + if (Reset = '1') then -- reset the D flip flop + Q <= "0000"; + else + if (En = '1') then -- Enable should be set + Q <= D; + end if; + end if; + end if; end process; end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd b/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd new file mode 100644 index 0000000..86af573 --- /dev/null +++ b/LAB10.srcs/sources_1/new/Instruction_Decoder.vhd @@ -0,0 +1,90 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 03:35:24 PM +-- Design Name: +-- Module Name: Instruction_Decoder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Instruction_Decoder is + Port ( Instruction_Bus : in STD_LOGIC_VECTOR (11 downto 0); + Reg_Check_for_Jump : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : out STD_LOGIC_VECTOR (2 downto 0); + Load_Select : out STD_LOGIC; + Immediate_value : out STD_LOGIC_VECTOR (3 downto 0); + Register_select_01 : out STD_LOGIC_VECTOR (2 downto 0); + Register_select_02 : out STD_LOGIC_VECTOR (2 downto 0); + ADD_SUB_Select : out STD_LOGIC; + Jump_Flag : out STD_LOGIC; + Address_to_jump : out STD_LOGIC_VECTOR (2 downto 0)); +end Instruction_Decoder; + +architecture Behavioral of Instruction_Decoder is +signal Instruction_Select : STD_LOGIC_VECTOR (1 downto 0); +begin + +--getting the num for Selecting the instruction +Instruction_Select<=Instruction_Bus(11 downto 10); +process begin +case Instruction_Select is --Selecting the instruction + when "00"=> + --Add values in registers Ra and Rb and store the result in Ra + Register_select_01<=Instruction_Bus(9 downto 7); + Register_select_02<=Instruction_Bus(6 downto 4); + ADD_SUB_Select<='0'; + Load_Select<='1'; --if 1 selecty the output of 4 bit addsub, if 0 select imediate value + Reg_Enable<=Instruction_Bus(9 downto 7); + + when "01"=> + --2's complement of registers R + Register_select_01<="000"; + Register_select_02<=Instruction_Bus(9 downto 7); + ADD_SUB_Select<='1'; + Load_Select<='1'; + Reg_Enable<=Instruction_Bus(9 downto 7); + + + when "10"=> + --Move immediate value d to register R + Immediate_value<=Instruction_Bus(3 downto 0); + Load_Select<='0'; + Reg_Enable<=Instruction_Bus(9 downto 7); + + when "11"=> + Register_select_01<=Instruction_Bus(9 downto 7); + if(Reg_Check_for_Jump="0000") then + Jump_Flag<='1'; + Address_to_jump<=Instruction_Bus(2 downto 0); + else + Jump_Flag<='0'; + end if; +end case; + +end process; + +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Nano_Processor.vhd b/LAB10.srcs/sources_1/new/Nano_Processor.vhd new file mode 100644 index 0000000..e69de29 diff --git a/LAB10.srcs/sources_1/new/Program_ROM.vhd b/LAB10.srcs/sources_1/new/Program_ROM.vhd new file mode 100644 index 0000000..0ce23b4 --- /dev/null +++ b/LAB10.srcs/sources_1/new/Program_ROM.vhd @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 02:41:04 PM +-- Design Name: +-- Module Name: Program_ROM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Program_ROM is + Port ( Memory_Select : in STD_LOGIC_VECTOR (2 downto 0); + Instruction_Bus : out STD_LOGIC_VECTOR (11 downto 0)); +end Program_ROM; + +architecture Behavioral of Program_ROM is +type rom_type is array (0 to 7) of std_logic_vector(11 downto 0); +signal sevenSegment_ROM : rom_type := ( + "100010001010", -- 0 + "100100000001", -- 1 + "010100000000", -- 2 + "000010100000", -- 3 + "110010000111", -- 4 + "110000000011", -- 5 + "111111111111", -- 6 + "111111111111" -- 7 + ); + +begin + +Instruction_Bus <= sevenSegment_ROM(to_integer(unsigned(Memory_Select))); + + + +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Program_counter.vhd b/LAB10.srcs/sources_1/new/Program_counter.vhd new file mode 100644 index 0000000..c5372a2 --- /dev/null +++ b/LAB10.srcs/sources_1/new/Program_counter.vhd @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/16/2022 02:34:25 PM +-- Design Name: +-- Module Name: Reg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Program_counter is + Port ( Mux_2way3_bit_out : in STD_LOGIC_VECTOR (2 downto 0); + En : in STD_LOGIC; + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + MemorySelect : out STD_LOGIC_VECTOR (2 downto 0)); +end Program_counter; + +architecture Behavioral of Program_counter is + +begin + process(Clk) + begin + if (rising_edge(Clk)) then -- respond when clock rises + if (Reset = '1') then -- reset the D flip flop + MemorySelect <= "0000"; + else + if (En = '1') then -- Enable should be set + MemorySelect <= Mux_2way3_bit_out; + end if; + end if; + + end if; + end process; +end Behavioral; diff --git a/LAB10.srcs/sources_1/new/Reg_Bank.vhd b/LAB10.srcs/sources_1/new/Reg_Bank.vhd new file mode 100644 index 0000000..e76841d --- /dev/null +++ b/LAB10.srcs/sources_1/new/Reg_Bank.vhd @@ -0,0 +1,137 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/14/2022 10:07:37 AM +-- Design Name: +-- Module Name: Reg_Bank - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Reg_Bank is + Port ( Clk : in STD_LOGIC; + Data_in : in STD_LOGIC_VECTOR (3 downto 0); + Reg_Enable : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Reg_0_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_1_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_2_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_3_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_4_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_5_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_6_out : out STD_LOGIC_VECTOR (3 downto 0); + Reg_7_out : out STD_LOGIC_VECTOR (3 downto 0) + ); +end Reg_Bank; + +architecture Behavioral of Reg_Bank is +component Reg + Port ( D : in STD_LOGIC_VECTOR (3 downto 0); + En : in STD_LOGIC; + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + +component Decoder_3_to_8 + Port ( I : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIC; + Y : out STD_LOGIC_VECTOR (7 downto 0)); +end component; +signal R_Y : STD_LOGIC_VECTOR (7 downto 0); +begin + Decoder_3_to_8_0 : Decoder_3_to_8 + PORT MAP ( + I=>Reg_Enable, + EN => '1', + Y => R_Y + ); + Register_0 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(0), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_0_out + ); + Register_1 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(1), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_1_out + ); + Register_2 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(2), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_2_out + ); + Register_3 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(3), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_3_out + ); + Register_4 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(4), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_4_out + ); + Register_5 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(5), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_5_out + ); + Register_6 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(6), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_6_out + ); + Register_7 :Reg + PORT MAP( + D=>Data_in, + En=>R_Y(7), + Reset=>Reset, + Clk=>Clk, + Q=>Reg_7_out + ); + +end Behavioral; diff --git a/LAB10.xpr b/LAB10.xpr index ebb9246..d00560c 100644 --- a/LAB10.xpr +++ b/LAB10.xpr @@ -32,7 +32,7 @@