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jakubcabaljakubcabal
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Merge branch 'fukac-alveo-u55c-fix' into 'devel'
fix(alveo-u55c): fix typo in command for generating PCIe IP See merge request ndk/ndk-fpga!310
2 parents 2e38ebf + 22152d0 commit 10d03a9

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15 files changed

+118
-147
lines changed

15 files changed

+118
-147
lines changed

‎cards/amd/alveo-u55c/constr/general.xdc‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,3 +53,12 @@ set_property IOSTANDARD LVCMOS18 [get_ports "HBM_CATTRIP"];
5353

5454
# Lock DNA_PORT2E to X0Y0 due to different Chip ID in each SLRs!!!
5555
set_property LOC CONFIG_SITE_X0Y0 [get_cells cm_i/hwid_i/usp_g.dna_port_i]
56+
57+
# ==============================================================================
58+
# Miscellaneous
59+
# ==============================================================================
60+
61+
# These LEDs are only connected and tied to 0 to ensure they are turned off.
62+
set_property PACKAGE_PIN BL13 [get_ports "QSFP_ACT_LED_G[0]"];
63+
set_property PACKAGE_PIN BK14 [get_ports "QSFP_ACT_LED_G[1]"];
64+
set_property IOSTANDARD LVCMOS18 [get_ports "QSFP_ACT_LED_G"];

‎cards/amd/alveo-u55c/constr/pcie.xdc‎

Lines changed: 0 additions & 85 deletions
This file was deleted.

‎cards/amd/alveo-u55c/constr/pcie_full.xdc‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
# pcie_full.xdc: the second half of the PCIe endpoint
2+
# Copyright (C) 2023 CESNET z. s. p. o.
3+
# Author(s): Jakub Cabal <[email protected]>
4+
#
5+
# SPDX-License-Identifier: BSD-3-Clause
6+
7+
set_property PACKAGE_PIN AV3 [get_ports {PCIE_RX_N[8]}]
8+
set_property PACKAGE_PIN AV4 [get_ports {PCIE_RX_P[8]}]
9+
set_property PACKAGE_PIN AW5 [get_ports {PCIE_RX_N[9]}]
10+
set_property PACKAGE_PIN AW6 [get_ports {PCIE_RX_P[9]}]
11+
set_property PACKAGE_PIN AW1 [get_ports {PCIE_RX_N[10]}]
12+
set_property PACKAGE_PIN AW2 [get_ports {PCIE_RX_P[10]}]
13+
set_property PACKAGE_PIN AY3 [get_ports {PCIE_RX_N[11]}]
14+
set_property PACKAGE_PIN AY4 [get_ports {PCIE_RX_P[11]}]
15+
set_property PACKAGE_PIN BA5 [get_ports {PCIE_RX_N[12]}]
16+
set_property PACKAGE_PIN BA6 [get_ports {PCIE_RX_P[12]}]
17+
set_property PACKAGE_PIN BA1 [get_ports {PCIE_RX_N[13]}]
18+
set_property PACKAGE_PIN BA2 [get_ports {PCIE_RX_P[13]}]
19+
set_property PACKAGE_PIN BB3 [get_ports {PCIE_RX_N[14]}]
20+
set_property PACKAGE_PIN BB4 [get_ports {PCIE_RX_P[14]}]
21+
set_property PACKAGE_PIN BC1 [get_ports {PCIE_RX_N[15]}]
22+
set_property PACKAGE_PIN BC2 [get_ports {PCIE_RX_P[15]}]
23+
24+
set_property PACKAGE_PIN AU6 [get_ports {PCIE_TX_N[8]}]
25+
set_property PACKAGE_PIN AU7 [get_ports {PCIE_TX_P[8]}]
26+
set_property PACKAGE_PIN AV8 [get_ports {PCIE_TX_N[9]}]
27+
set_property PACKAGE_PIN AV9 [get_ports {PCIE_TX_P[9]}]
28+
set_property PACKAGE_PIN AW10 [get_ports {PCIE_TX_N[10]}]
29+
set_property PACKAGE_PIN AW11 [get_ports {PCIE_TX_P[10]}]
30+
set_property PACKAGE_PIN AY8 [get_ports {PCIE_TX_N[11]}]
31+
set_property PACKAGE_PIN AY9 [get_ports {PCIE_TX_P[11]}]
32+
set_property PACKAGE_PIN BA10 [get_ports {PCIE_TX_N[12]}]
33+
set_property PACKAGE_PIN BA11 [get_ports {PCIE_TX_P[12]}]
34+
set_property PACKAGE_PIN BB8 [get_ports {PCIE_TX_N[13]}]
35+
set_property PACKAGE_PIN BB9 [get_ports {PCIE_TX_P[13]}]
36+
set_property PACKAGE_PIN BC10 [get_ports {PCIE_TX_N[14]}]
37+
set_property PACKAGE_PIN BC11 [get_ports {PCIE_TX_P[14]}]
38+
set_property PACKAGE_PIN BC6 [get_ports {PCIE_TX_N[15]}]
39+
set_property PACKAGE_PIN BC7 [get_ports {PCIE_TX_P[15]}]

‎cards/amd/alveo-u55c/constr/pcie_half.xdc‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,11 @@ set_property PACKAGE_PIN BF41 [get_ports {PCIE_SYSRST_N}]
4343
set_property IOSTANDARD LVCMOS18 [get_ports {PCIE_SYSRST_N}]
4444
set_property PULLUP true [get_ports {PCIE_SYSRST_N}]
4545

46+
set_property PACKAGE_PIN AL15 [get_ports {PCIE_SYSCLK0_P}]
47+
set_property PACKAGE_PIN AL14 [get_ports {PCIE_SYSCLK0_N}]
48+
4649
set_property PACKAGE_PIN AR15 [get_ports {PCIE_SYSCLK1_P}]
4750
set_property PACKAGE_PIN AR14 [get_ports {PCIE_SYSCLK1_N}]
4851

49-
create_clock -period 10.000 -name pcie_clk_p -waveform {0.000 5.000} [get_ports {PCIE_SYSCLK1_P}]
52+
create_clock -period 10.000 -name pcie_clk0_p -waveform {0.000 5.000} [get_ports {PCIE_SYSCLK0_P}]
53+
create_clock -period 10.000 -name pcie_clk1_p -waveform {0.000 5.000} [get_ports {PCIE_SYSCLK1_P}]

‎cards/amd/alveo-u55c/constr/qsfp.xdc‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,14 +8,11 @@
88
# QSFP MISC INTERFACES
99
# ==============================================================================
1010

11-
set_property PACKAGE_PIN BL13 [get_ports "QSFP_ACT_LED_G[0]"];
12-
set_property PACKAGE_PIN BK14 [get_ports "QSFP_ACT_LED_G[1]"];
1311
set_property PACKAGE_PIN BK11 [get_ports "QSFP_STA_LED_G[0]"];
1412
set_property PACKAGE_PIN BK15 [get_ports "QSFP_STA_LED_G[1]"];
1513
set_property PACKAGE_PIN BJ11 [get_ports "QSFP_STA_LED_Y[0]"];
1614
set_property PACKAGE_PIN BL12 [get_ports "QSFP_STA_LED_Y[1]"];
1715

18-
set_property IOSTANDARD LVCMOS18 [get_ports "QSFP_ACT_LED_G"];
1916
set_property IOSTANDARD LVCMOS18 [get_ports "QSFP_STA_LED_G"];
2017
set_property IOSTANDARD LVCMOS18 [get_ports "QSFP_STA_LED_Y"];
2118

‎cards/amd/alveo-u55c/constr/qsfp_disconnect.xdc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,6 @@ set_property IO_BUFFER_TYPE NONE [get_ports {QSFP0_TX_P[*]}]
88
set_property IO_BUFFER_TYPE NONE [get_ports {QSFP0_TX_N[*]}]
99
set_property IO_BUFFER_TYPE NONE [get_ports {QSFP1_TX_P[*]}]
1010
set_property IO_BUFFER_TYPE NONE [get_ports {QSFP1_TX_N[*]}]
11+
12+
set_property IO_BUFFER_TYPE NONE [get_ports {QSFP_STA_LED_G[*]}]
13+
set_property IO_BUFFER_TYPE NONE [get_ports {QSFP_STA_LED_Y[*]}]

‎cards/amd/alveo-u55c/src/Modules.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ set ARCHGRP_ARR(USE_IP_SUBDIRS) true
2828

2929
lappend IP_COMPONENTS [list "pcie" "pcie4_uscale_plus" "pcie4_uscale_plus" 0 1]
3030
if {$ARCHGRP_ARR(PCIE_ENDPOINTS) == 2 && $ARCHGRP_ARR(PCIE_ENDPOINT_MODE) == 1} {
31-
lappend IP_COMPONENTS [list "pcie" "pcie4c_uscale_plus" "pcie4_uscale_plus_1" 0 1]
31+
lappend IP_COMPONENTS [list "pcie" "pcie4_uscale_plus" "pcie4_uscale_plus_1" 0 1]
3232
}
3333

3434
lappend IP_COMPONENTS [list "mem" "axi_quad_spi" "axi_quad_spi_0" 0 1]

‎cards/amd/alveo-u55c/src/Vivado.inc.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,10 +46,10 @@ lappend HIERARCHY(COMPONENTS) [list "TOPLEVEL" $CARD_BASE/src $ARCHGRP_ALL]
4646
lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/general.xdc"
4747
lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pblock.xdc"
4848

49+
lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pcie_half.xdc"
50+
4951
if {$PCIE_ENDPOINT_MODE == 0 || $PCIE_ENDPOINT_MODE == 1} {
50-
lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pcie.xdc"
51-
} else {
52-
lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pcie_half.xdc"
52+
lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pcie_full.xdc"
5353
}
5454

5555
if {$NET_MOD_ARCH != "EMPTY"} {

‎cards/amd/alveo-u55c/src/fpga.vhd‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,9 @@ architecture FULL of FPGA is
116116
signal qsfp_modprs_n : std_logic_vector(2-1 downto 0);
117117
signal qsfp_int_n : std_logic_vector(2-1 downto 0);
118118

119+
signal qsfp_sta_led_g_int : std_logic_vector(QSFP_STA_LED_G'range);
120+
signal qsfp_sta_led_y_int : std_logic_vector(QSFP_STA_LED_Y'range);
121+
119122
signal boot_mi_clk : std_logic;
120123
signal boot_mi_reset : std_logic;
121124
signal boot_mi_addr : std_logic_vector(32-1 downto 0);
@@ -1313,8 +1316,12 @@ begin
13131316
QSFP1_TX_N <= eth_tx_n(2*ETH_LANES-1 downto 1*ETH_LANES);
13141317
QSFP0_TX_P <= eth_tx_p(1*ETH_LANES-1 downto 0*ETH_LANES);
13151318
QSFP0_TX_N <= eth_tx_n(1*ETH_LANES-1 downto 0*ETH_LANES);
1319+
1320+
QSFP_STA_LED_Y <= qsfp_sta_led_y_int;
1321+
QSFP_STA_LED_G <= qsfp_sta_led_g_int;
13161322
end generate;
13171323

1324+
-- Tied to 0 to ensure that these LEDs are turned off
13181325
QSFP_ACT_LED_G <= (others => '0');
13191326

13201327
-- =========================================================================
@@ -1496,8 +1503,8 @@ begin
14961503
ETH_TX_P => eth_tx_p(ETH_PORTS*ETH_LANES-1 downto 0),
14971504
ETH_TX_N => eth_tx_n(ETH_PORTS*ETH_LANES-1 downto 0),
14981505

1499-
ETH_LED_R => QSFP_STA_LED_Y,
1500-
ETH_LED_G => QSFP_STA_LED_G,
1506+
ETH_LED_R => qsfp_sta_led_y_int,
1507+
ETH_LED_G => qsfp_sta_led_g_int,
15011508

15021509
QSFP_I2C_SCL => open,
15031510
QSFP_I2C_SDA => open,

‎cards/amd/alveo-u55c/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ if {[string is integer -strict $last_part]} {
2424
set endpoint_idx 0
2525
}
2626

27-
puts "The index of an endpoint is $endpoint_idx"
27+
puts "Creating PCIe endpoint with index $endpoint_idx"
2828

2929
set IP [get_ips $IP_COMP_NAME]
3030

@@ -42,7 +42,7 @@ set PF0_DEVICE_ID {c000}
4242
set config_list [list \
4343
CONFIG.ext_pcie_cfg_space_enabled {true} \
4444
CONFIG.extended_tag_field {true} \
45-
CONFIG.plltype {QPLL1} \
45+
CONFIG.plltype {QPLL0} \
4646
CONFIG.axisten_freq {250} \
4747
CONFIG.AXISTEN_IF_ENABLE_CLIENT_TAG {true} \
4848
CONFIG.pf0_dev_cap_max_payload {512_bytes} \
@@ -51,8 +51,6 @@ set config_list [list \
5151
CONFIG.MSI_X_OPTIONS {None} \
5252
CONFIG.mode_selection {Advanced} \
5353
CONFIG.pf0_msix_enabled {false} \
54-
CONFIG.pf1_msi_enabled {false} \
55-
CONFIG.pf1_msix_enabled {false} \
5654
CONFIG.pf0_bar0_64bit {true} \
5755
CONFIG.pf0_bar0_prefetchable {false} \
5856
CONFIG.pf0_bar0_scale {Megabytes} \

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