Notebook 05 — Spintronic gate set, depth benchmarks, and Weyl chamber figure

[rosspeili]

Context

Issues #11–#12 implement the spintronic native gate library and depth comparison vs universal RZ + CNOT. Notebook 05 is the visual deliverable for Workstream C1 — the second research thread in this repo alongside QRC (B3).

docs/notebooks.md specifies:

• File: notebooks/05_spintronic_gate_set.ipynb
• Output: figures/gate_depth_comparison.png
• OVERVIEW also mentions Weyl chamber representation for 2-qubit gate set completeness

gates.py docstring says full operations planned for notebook 05.

Goal

Create and execute notebooks/05_spintronic_gate_set.ipynb that:

1. Introduces the spintronic gate set with physical mapping table
2. Demonstrates native gate circuits on a small chain (n_sites=3 or 4)
3. Plots circuit depth: native vs universal scaling from Issue Gate depth benchmarks — spintronic native set vs universal RZ + CNOT #12
4. Includes a 2-qubit Weyl chamber diagram (conceptual completeness visualization)
5. Saves figures/gate_depth_comparison.png (and optionally figures/weyl_chamber.png merged or separate)

Notebook structure

Cell 1 — Title and context (markdown)

• QONDRA / spintronic-qrc — Workstream C1
• Physical motivation: Larmor, RKKY exchange, SOT, damping, spin Hall injection
• Claim under test: native gates reduce depth for spin-chain simulation layers
• Cite: Sinova et al. (2015), Manchon et al. (2019), Grollier et al. (2020) — REFERENCES.md G1–G5

Cell 2 — Setup

from __future__ import annotations

import os
import warnings
warnings.filterwarnings("ignore")

import numpy as np
import matplotlib.pyplot as plt
import pennylane as qp

from spintronic_qrc.gates import SpintronicGateSet, SPINTRONIC_GATE_SET
from spintronic_qrc.depth import compare_depths, DepthResult  # Issue #12 API
from spintronic_qrc import utils

os.makedirs("../figures", exist_ok=True)
os.makedirs("../data", exist_ok=True)

Adjust imports to final Issue #11–#12 module paths.

Cell 3 — Gate set catalog

• Print SPINTRONIC_GATE_SET table (name, physical_op, pennylane_op)
• Instantiate SpintronicGateSet(n_sites=4)
• Show example gates: larmor, exchange, sot, spin_hall_pair on wires 0–3

Optional: single @qml.qnode applying one spintronic_xxz_step layer and return statevector norm check (sanity).

Cell 4 — Depth benchmark

n_list = [3, 4, 5, 6, 8, 10]
results = compare_depths(n_list)

Build DataFrame from DepthResult list. Save data/gate_depth.csv if not already committed from Issue #12 script.

Cell 5 — Depth comparison figure

Line plot or grouped bar chart:

• x-axis: n_sites
• y-axis: circuit depth
• Series: native_depth, universal_depth
• Optional third series: two-qubit gate counts

Use utils palette. This is the main panel for gate_depth_comparison.png.

Cell 6 — Weyl chamber (2-qubit gate completeness)

Conceptual visualization for C1 narrative — does not need full optimal control theory.

Minimum acceptable content:

• Sketch Weyl chamber axes (local equivalence classes of 2-qubit unitaries)
• Mark points or regions for: IsingXX / exchange, spin_hall_gate, CNOT-equivalent class
• Caption: which operations the spintronic set covers natively vs requires composition

Can be a schematic matplotlib 2D or 3D projection (see literature on Weyl chamber for SU(4)). Keep pedagogical, not publication-rigorous, with markdown disclaimer.

Combine Weyl panel + depth panel into one figure OR save weyl as inset. Final committed file: figures/gate_depth_comparison.png (multi-panel encouraged).

Cell 7 — Summary markdown

Table of depth savings at n_sites=8 and n_sites=10:

| n_sites | native_depth | universal_depth | reduction % |

State whether C1 hypothesis is supported on this benchmark unit.

Cell 8 — Sanity checks

• All depths > 0
• gate_depth_comparison.png exists
• data/gate_depth.csv exists
• native_depth < universal_depth for largest n tested (or explain exception)

Acceptance criteria

• notebooks/05_spintronic_gate_set.ipynb runs top-to-bottom
• figures/gate_depth_comparison.png committed (multi-panel with depth + Weyl schematic)
• Uses spintronic_qrc.gates and depth module (no duplicated gate definitions)
• data/gate_depth.csv present (from notebook or Issue Gate depth benchmarks — spintronic native set vs universal RZ + CNOT #12 script)
• OVERVIEW.md deliverables: check off notebook 05
• Runtime under ~10 min CPU

Files likely touched

• notebooks/05_spintronic_gate_set.ipynb (new)
• figures/gate_depth_comparison.png (new)
• data/gate_depth.csv (new or updated)
• OVERVIEW.md (optional C1 results stub)

Depends on

• Issue Spintronic gate library — custom PennyLane operations (Workstream C1) #11 (gate library) — required
• Issue Gate depth benchmarks — spintronic native set vs universal RZ + CNOT #12 (depth benchmarks) — required

Blocks

• Workstream C1 marked complete in program narrative
• Paper C1 section figures
• Issue Open-system QRC via QuTiP + Notebook 06 (Gilbert damping) #14 (open-system) is independent