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‎.github/workflows/ci.yml

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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v2
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- uses: actions/checkout@v4
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- name: setup python
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uses: actions/setup-python@v2
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uses: actions/setup-python@v5
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with:
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python-version: '3.x'
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- name: install packages
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run: tools/common/check-rst-syntax.sh
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- name: build PDFs
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run: tools/rst2pdf/generate-pdfs.sh PDFs
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- uses: actions/upload-artifact@v2
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- uses: actions/upload-artifact@v4
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with:
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name: PDFs
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path: PDFs

‎CONTRIBUTING.md

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If you want to make ABI changes that for some reason can't be discussed in
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public, you can send an email to [email protected].
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### Extension documents
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While the majority of new proposals can be added to existing
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documents. Proposals that extend the ABI, but are not yet stable are
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placed in an extension document. An example of an extension document
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is the PAuth Extension to ELF for Arm 64-bit Architecture. Extension
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documents have the following requirements:
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1. The document status must be Alpha.
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2. The document has an owner recorded in the table below. The owner
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need not be from Arm.
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3. The document must not clash with other ABI extension documents, or
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both extensions must be marked as being incompatible.
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The Arm approval process for accepting the extension is as follows:
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1. At least one person within Arm has reviewed and accepted the pull
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request.
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2. There is a consensus within Arm that the extension can be added to
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the ABI.
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Extension documents can move into the main ABI when the following conditions hold:
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1. The information in the document is stable.
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2. There is an implementation of the extension.
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3. The boundaries of when the extension applies are clear.
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An extension document that moves into the main ABI will add the
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necessary information to the main documents. In addition any design
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and rationale in the extension document will be moved to a new
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document in the design-documents folder.
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When the extension has either moved into the main ABI or has been
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withdrawn it will be moved to an archive folder.
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## Manual checking of the PDF documents and Continuous Integration
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To check the outcome of your changes, run the `tools/rst2pdf/generate-pdfs.sh`
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[Morello extensions to ELF for the Arm 64-bit Architecture](https://github.com/ARM-software/abi-aa/tree/master/aaelf64-morello) | Silviu Baranga | @sbaranga-arm
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[Morello Descriptor ABI for the Arm 64-bit Architecture](https://github.com/ARM-software/abi-aa/tree/master/descabi-morello) | Silviu Baranga | @sbaranga-arm
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[Memtag ABI Extension to ELF for the Arm 64-bit Architecture](https://github.com/ARM-software/abi-aa/tree/master/memtagabielf64) | Mitch Phillips | @hctim
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[C/C++ Atomics Application Binary Interface Standard for the Arm 64-bit Architecture](https://github.com/ARM-software/abi-aa/tree/master/atomicsabi64) | Luke Geeson | @lukeg101
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3. Merging the change
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‎README.md

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DWARF for the Arm 64-bit Architecture | [aadwarf64](aadwarf64/aadwarf64.rst) | [2020Q2](legacy-documents/aadwarf64/ihi0057_E/IHI0057_E_2020Q2_aadwarf64.pdf)
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C++ ABI for the Arm 64-bit Architecture | [cppabi64](cppabi64/cppabi64.rst) | [2020Q2](legacy-documents/cppabi64/ihi0059_E/IHI0059E_2020Q2_cppabi64.pdf)
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Vector Function ABI for the Arm 64-bit Architecture | [vfabia64](vfabia64/vfabia64.rst) | [2019Q2](legacy-documents/vfabia64/101129_1920/101129_1920_01_en.pdf)
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C/C++ Atomics ABI for the Arm 64-bit Architecture | [atomicsabi64](atomicsabi64/atomicsabi64.rst) | n/a
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System V ABI for the Arm 64-bit Architecture | [sysvabi64](sysvabi64/sysvabi64.rst) | n/a
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### ABI for the Arm 64-bit Architecture with SVE support
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specification | latest | last legacy release
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--- | --- | ---
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Procedure Call Standard for the Arm 64-bit Architecture with SVE support | content merged with [aapcs64](aapcs64/aapcs64.rst) | [SVEpcs 00bet1](legacy-documents/aapcs64-sve/100986_0000/abi_sve_aapcs64_100986_0000_00_en.pdf)
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DWARF for the Arm 64-bit Architecture with SVE support | content merged with [aadwarf64](aadwarf64/aawarf64.rst) | [SVEdwf 00bet1](legacy-documents/aadwarf64-sve/100985_0000/abi_sve_aadwarf_100985_0000_00_en.pdf)
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DWARF for the Arm 64-bit Architecture with SVE support | content merged with [aadwarf64](aadwarf64/aadwarf64.rst) | [SVEdwf 00bet1](legacy-documents/aadwarf64-sve/100985_0000/abi_sve_aadwarf_100985_0000_00_en.pdf)
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Vector Function ABI for the Arm 64-bit Architecture (identical to document in *ABI for the Arm 64-bit Architecture* section) | [vfabia64](vfabia64/vfabia64.rst) | [2019Q2](legacy-documents/vfabia64/101129_1920/101129_1920_01_en.pdf)
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### PAuth ABI Extension

‎aadwarf32/aadwarf32.rst

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..
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Copyright (c) 2003-2007, 2012, 2018, 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2003-2007, 2012, 2018, 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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See LICENSE file for details
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.. |release| replace:: 2023Q3
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.. |date-of-issue| replace:: 6\ :sup:`th` October 2023
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.. |copyright-date| replace:: 2003-2007, 2012, 2018, 2020-2023
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.. |release| replace:: 2024Q3
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.. |date-of-issue| replace:: 5\ :sup:`th` September 2024
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.. |copyright-date| replace:: 2003-2007, 2012, 2018, 2020-2024
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.. |footer| replace:: Copyright © |copyright-date|, Arm Limited and its
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affiliates. All rights reserved.
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‎aadwarf64-morello/aadwarf64-morello.rst

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..
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Copyright (c) 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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See LICENSE file for details
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.. |release| replace:: 2023Q3
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.. |date-of-issue| replace:: 6\ :sup:`th` October 2023
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.. |copyright-date| replace:: 2020-2023
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.. |date-of-issue| replace:: 5\ :sup:`th` September 2024
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.. |copyright-date| replace:: 2020-2024
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.. |footer| replace:: Copyright © |copyright-date|, Arm Limited and its
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‎aadwarf64/aadwarf64.rst

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..
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Copyright (c) 2010, 2013, 2018, 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2010, 2013, 2018, 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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See LICENSE file for details
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.. |date-of-issue| replace:: 6\ :sup:`th` October 2023
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.. |date-of-issue| replace:: 5\ :sup:`th` September 2024
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.. |copyright-date| replace:: 2010, 2013, 2018, 2020-2024
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| 2022Q3 | 20\ :sup:`th` October 2022 | - Added `Changes in vector length`_ at |
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| | | **Alpha** quality. |
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+--------+-----------------------------+----------------------------------------+
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| 2024Q3 | 5\ :sup:`th` September 2024 | In `DWARF register names_` and |
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| | | `Call frame instructions`_, add Dwarf |
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| | | support for unwinding with |
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| | | FEAT_PAuth_LR enabled. |
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+--------+-----------------------------+----------------------------------------+
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References
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.. _Note 8:
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8. The RA_SIGN_STATE pseudo-register records whether the return address has
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been signed with a PAC. This information can be used when unwinding. It
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is an unsigned integer with the same size as a general register. Only
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bit[0] is meaningful and is initialized to zero. A value of 0 indicates
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the return address has not been signed. A value of 1 indicates the return
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address has been signed.
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been signed with a PAC, and whether the value of PC has been used as a
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diversifier for the return address signing. This information can be used
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when unwinding. It is an unsigned integer with the same size as a general
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register. Only bit[0] and bit[1] are meaningful and are initialized to zero.
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Bit[0] indicates whether the return address has been signed. A value of 0
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indicates the return address has not been signed. A value of 1 indicates
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the return address has been signed.
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Bit[1] indicates whether the value of PC has been used as a diversifier for
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signing the return address. A value of 0 indicates the value of PC has not
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been used for return address signing. A value of 1 indicates the value of PC
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has been used for return address signing.
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+--------+--------+----------------------------------+
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| Bit[1] | Bit[0] | State |
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+========+========+==================================+
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| 0 | 0 | Return address not signed |
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+--------+--------+----------------------------------+
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| 0 | 1 | Return address signed with SP |
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+--------+--------+----------------------------------+
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| 1 | 1 | Return address signed with SP+PC |
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+--------+--------+----------------------------------+
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| 1 | 0 | Invalid state |
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+--------+--------+----------------------------------+
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.. _Note 9:
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Call frame instructions
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-----------------------
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This ABI defines one vendor call frame instruction
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``DW_CFA_AARCH64_negate_ra_state``.
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This ABI defines the following vendor call frame instructions:
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``DW_CFA_AARCH64_negate_ra_state`` and ``DW_CFA_AARCH64_negate_ra_state_with_pc``.
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.. class:: aadwarf64-vendor-cfa-operations
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.. table:: AArch64 vendor CFA operations
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+------------------------------------+-------------+------------+-----------+-----------+
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| Instruction | High 2 bits | Low 6 bits | Operand 1 | Operand 2 |
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+====================================+=============+============+===========+===========+
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| ``DW_CFA_AARCH64_negate_ra_state`` | 0 | ``0x2D`` | \- | \- |
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+------------------------------------+-------------+------------+-----------+-----------+
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+--------------------------------------------+-------------+------------+-----------+-----------+
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| Instruction | High 2 bits | Low 6 bits | Operand 1 | Operand 2 |
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+============================================+=============+============+===========+===========+
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| ``DW_CFA_AARCH64_negate_ra_state`` | 0 | ``0x2D`` | \- | \- |
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+--------------------------------------------+-------------+------------+-----------+-----------+
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| ``DW_CFA_AARCH64_negate_ra_state_with_pc`` | 0 | ``0x2C`` | \- | \- |
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+--------------------------------------------+-------------+------------+-----------+-----------+
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The ``DW_CFA_AARCH64_negate_ra_state`` operation negates bit[0] of the
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RA_SIGN_STATE pseudo-register. It does not take any operands.
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The ``DW_CFA_AARCH64_negate_ra_state`` must not be mixed with other DWARF
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Register Rule Instructions (GDWARF_, §6.4.2.3) on the RA_SIGN_STATE
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pseudo-register in one Common Information Entry (CIE) and Frame Descriptor
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Entry (FDE) program sequence.
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The ``DW_CFA_AARCH64_negate_ra_state_with_pc`` operation negates bit[0] and
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bit[1] of the RA_SIGN_STATE pseudo-register, and instructs the unwinder to
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capture the current code location. The code location information can be used
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for authenticating the return address.
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The ``DW_CFA_AARCH64_negate_ra_state_with_pc`` instruction must be placed within
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the debug frame in a position that refers to the exact code location of the
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signing/authenticating PAC instructions.
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The ``DW_CFA_AARCH64_negate_ra_state`` and ``DW_CFA_AARCH64_negate_ra_state_with_pc``
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instructions must not be mixed with other DWARF Register Rule Instructions
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(GDWARF_, §6.4.2.3) on the RA_SIGN_STATE pseudo-register in one Common
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Information Entry (CIE) and Frame Descriptor Entry (FDE) program sequence.
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.. _DWARF expression operations:
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‎aaelf32/aaelf32.rst

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Copyright (c) 2005-2009, 2012, 2015, 2018, 2020-2023, Arm Limited and its affiliates. All rights
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Copyright (c) 2005-2009, 2012, 2015, 2018, 2020-2024, Arm Limited and its affiliates. All rights
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reserved. CC-BY-SA-4.0 AND Apache-Patent-License See LICENSE file
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for details
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.. |date-of-issue| replace:: 6\ :sup:`th` October 2023
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.. |release| replace:: 2024Q3
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.. |footer| replace:: Copyright © |copyright-date|, Arm Limited and its
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.. |armarmv5_link| replace:: https://developer.arm.com/docs/ddi0100/latest/armv5-architecture-reference-manual
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+-------------------+---------------------------------------------------------------------+
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| ``llvm`` | The LLVM/Clang projects |
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+-------------------+---------------------------------------------------------------------+
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| ``mchp`` | Microchip Technology Inc. |
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+-------------------+---------------------------------------------------------------------+
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| ``PSI`` | PalmSource Inc. |
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+-------------------+---------------------------------------------------------------------+
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| ``RAL`` | Rowley Associates Ltd |
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+---------+----------------------------------+------------+---------------+----------------------------------------+
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| 2 | :code:`R_ARM_ABS32` | Static | Data | :code:`(S + A) | T` |
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+---------+----------------------------------+------------+---------------+----------------------------------------+
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| 3 | :code:`R_ARM_REL32` | Static | Data | :code:`((S + A) | T) | – P` |
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| 3 | :code:`R_ARM_REL32` | Static | Data | :code:`((S + A) | T) – P` |
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+---------+----------------------------------+------------+---------------+----------------------------------------+
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| 4 | :code:`R_ARM_LDR_PC_G0` | Static | Arm | :code:`S + A – P` |
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+---------+----------------------------------+------------+---------------+----------------------------------------+

‎aaelf64-morello/aaelf64-morello.rst

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Copyright (c) 2020-2023, Arm Limited and its affiliates. All rights reserved.
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Copyright (c) 2020-2024, Arm Limited and its affiliates. All rights reserved.
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CC-BY-SA-4.0 AND Apache-Patent-License
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See LICENSE file for details
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.. |release| replace:: 2024Q3
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.. |date-of-issue| replace:: 5\ :sup:`th` September 2024
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.. |copyright-date| replace:: 2020-2024
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.. |footer| replace:: Copyright © |copyright-date|, Arm Limited and its
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affiliates. All rights reserved.
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